CN209460196U - Hall measurement structure - Google Patents
Hall measurement structure Download PDFInfo
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- CN209460196U CN209460196U CN201822034082.8U CN201822034082U CN209460196U CN 209460196 U CN209460196 U CN 209460196U CN 201822034082 U CN201822034082 U CN 201822034082U CN 209460196 U CN209460196 U CN 209460196U
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- semiconductor layer
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- magnetic field
- measured
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Abstract
The utility model provides a kind of hall measurement structure, including substrate, the semiconductor layer being set on substrate and the sheet resistance induction part being set on semiconductor layer, magnetic field induction portion.Semiconductor layer has a pattern, and pattern includes that inductor section, 4 weld pads correspond to area, X font area and Ohmic contact road, and inductor section is located at the center in X font area, and weld pad corresponds to area two-by-two centered on inductor section, is arranged in the diagonal angle in X font area；Sheet resistance induction part includes 4 weld pads and space to be measured, and on the first plane, each weld pad of each weld pad covering semiconductor layer corresponds to area；Magnetic field induction portion includes that space to be measured, 2 testing cushions and the loop construction connecting with one of them testing cushion, loop construction ring are set around space to be measured, on the first plane, space to be measured expose under semiconductor layer inductor section；Another testing cushion, loop construction are contacted with the Ohmic contact road of semiconductor layer.
Description
Technical field
The utility model is to provide a kind of hall measurement structure, is especially surveyed with the Hall being formed on monolithic integrated optical circuit
Measure structure.
Background technique
It is doped with the minority carrier transport factor of carrier, carrier concentration in order to measure III-V family device of semiconductor,
Sheet resistance measurement and Hall is needed to measure.Sheet resistance, which measures, generally uses probe measuring method.Hall measurement is additional by measuring
Induction Hall voltage in magnetic field judges the concentration of conduction carrier, is generally measured using Fan get Wa (Van der Pauw)
Method, so, the geometry selection of sample seems especially important.It is generally necessary to meet following condition: thickness of sample is uniform；
Contact must be located at the periphery of sample, and contact must be fairly small.
However, when carrying out Hall metrology operation, being needed by being different from the external of integrated chip for integrated chip
Formula Hall measurement mechanism not only allows Hall amount by the Hall measurement mechanism that power source active electrically measure these circumscribeds
Survey carries out becoming complicated, and since circumscribed organization volume is necessarily large and bulky, makes Hall measurement mechanism not easy to operate.In addition, outer
Connect the factors that the equipment of formula causes magnetic field strength error in measurement in the presence of many, size, sample homogeneity comprising contact, correctly
Thermo-magnetic effect, photoconductive effect and photovoltaic effect caused by thickness of sample measurement, environment temperature etc..Each of which increases into
Cost when row Hall measures.
Utility model content
In order to improve missing mentioned by the prior art, the purpose of the utility model is to provide one kind to be formed in single-chip integration
Hall Measurement System on circuit, whereby, without using the Hall measurement equipment of circumscribed, by way of circuit integration,
By hall measurement structure microminiaturization, and be directly formed directly into the circuit comprising determinand on a piece of Silicon Wafer (i.e. with
External circuit monolithic (monolithic) formation).It is subsequent directly by after external power supply electric shock contact, measurement voltage, resistance and
Magnetic field can save Hall and measure cost and reduce error in measurement.
In order to achieve the above object, the hall measurement structure of the utility model is formed on monolithic integrated optical circuit, including substrate,
The semiconductor layer being set on substrate and the sheet resistance induction part being set on semiconductor layer, magnetic field induction portion.Semiconductor layer tool
There is a pattern, pattern includes that inductor section, 4 weld pads correspond to area, X font area and Ohmic contact road, and inductor section is located at X font area
Center, weld pad correspond to area two-by-two centered on inductor section, are arranged in the diagonal angle in X font area；Sheet resistance induction part includes 4 welderings
Pad and space to be measured, on the first plane, each weld pad of each weld pad covering semiconductor layer correspond to area；Magnetic field induction portion
Sky to be measured is set including space to be measured, 2 testing cushions and the loop construction connecting with one of them testing cushion, loop construction ring
Between around, on the first plane, space to be measured expose under semiconductor layer inductor section；Another testing cushion, coil knot
Structure is contacted with the Ohmic contact road of semiconductor layer.
Based on above-mentioned, the utility model can be measured directly by the hall measurement structure being formed on monolithic integrated optical circuit
The sheet resistance and Hall voltage of semiconductor layer, without in addition using Hall measurement equipment.
Detailed description of the invention
Fig. 1 is technology according to the present utility model, indicates circuit arrangement map of the hall measurement structure in the second plane；
Fig. 2 is technology according to the present utility model, indicates structural schematic diagram of the semiconductor layer in the second plane；
Fig. 3 is technology according to the present utility model, indicates circuit arrangement map of the magnetic field induction portion in the second plane；
Fig. 4 is technology according to the present utility model, and indicating hall measurement structure, AA ' line is on the first plane along Fig. 3
Schematic diagram；
Fig. 5 is technology according to the present utility model, indicates flow chart of the Hall Measurement System in running；
Fig. 6 is technology according to the present utility model, indicates that an embodiment measures the schematic diagram of sheet resistance；And
Fig. 7 is technology according to the present utility model, indicates that an embodiment measures the schematic diagram of magnetic field vector and Hall voltage.
Specific embodiment
In order to make the purpose of this utility model, technical characteristic and advantage, can more correlative technology field personnel understood, and
It is carried out the utility model, cooperates appended schema herein, specifically illustrate the technical characteristics of the utility model and embodiment,
And enumerate preferred embodiment further explanation.It is related with the utility model feature to express with the schema hereinafter compareed
Signal does not need completely to draw according to practical situation.And the those skilled in the art involved in the explanation of this case embodiment
Technology contents known to member, are also no longer stated.
In the present invention, the X-axis, Y-axis and Z axis system use the cassette coordinate system (Cartesian of dextrorotation
coordinate system).X-axis, Y-axis, Z axis and origin detailed direction in the present invention, be according in each schema
Appearance is indicated, and defining X-axis with the plane that Z axis is constituted is the first plane, and the plane that X-axis and Y-axis are constituted is the second plane, Y
The plane that axis and Z axis are constituted is third plane.
The circuit arrangement map that first, referring to fig. 1, Fig. 1 shows hall measurement structure in the second plane.As shown in Figure 1,
Hall measurement structure H-shaped is on monolithic integrated optical circuit (monolithic integrated circuit), monolithic integrated optical circuit
For the component of all electronic circuits, including interconnection line or logic gate etc., entirely on same silicon wafer or in same chip
The circuit of completion.From the point of view of the circuit layout on the second plane (overlooking face), hall measurement structure H includes substrate W, is set to
Semiconductor layer S and the sheet resistance induction part 1 being set on semiconductor layer S and magnetic field induction portion 2 on substrate W.Substrate W can be
Silicon, silicon carbide, gallium nitride or GaAs are formed.Substrate W is to electrically isolate peripheral integrated circuit, isolation method by groove
By the way of dry ecthing or ion implant.
Then referring to figure 2., Fig. 2 indicates structural schematic diagram of the semiconductor layer in the second plane.As shown in Fig. 2, partly leading
Body layer S has pattern, and pattern includes that inductor section SC, 4 weld pads correspond to area S1 (including S01, S02, S03, S04), X font area
And Ohmic contact road O X,.Inductor section SC is located at the center of X font area X, and weld pad corresponds to area S1 two-by-two centered on the SC of inductor section,
It is arranged in the diagonal angle of X font area X.Inductor section be long side be 100~2000 μm, broadside is 5~500 μm of rectangle.Partly lead
Body layer can be aluminium gallium nitride alloy, InGaN or aluminum indium gallium nitride, and semiconductor layer preferably penetrates Metalorganic chemical vapor deposition
Epitaxial layer.
It continues to refer to figure 1, sheet resistance induction part 1 is set on semiconductor layer S, including 4 weld pads 10 and space to be measured
11.On the first plane, each weld pad of each weld pad 10 covering semiconductor layer S corresponds to area S1, and space 11 to be measured is position
In the top of the inductor section SC relative to semiconductor layer S, and space to be measured 11 is identical as the size of inductor section SC.When to sheet resistance
When the weld pad 10 of induction part 1 passes to voltage, each weld pad 10 area's S1 Ohmic contact corresponding with each weld pad and be electrically connected,
The sheet resistance of the inductor section SC positioned at 11 lower section of space to be measured, semiconductor layer S can be measured using probe.
It continues to refer to figure 1, magnetic field induction portion is also set on semiconductor layer S, including 11,2, space to be measured testing cushion
20 and the loop construction 21 (as shown in Figure 3) that is connect with one of them testing cushion 20A.21 ring of loop construction sets space to be measured
Around 11, on the first plane, space 11 to be measured exposes the inductor section SC of beneath semiconductor layer S1.Another testing cushion
20B, loop construction 21A are contacted with the Ohmic contact road O of semiconductor layer S1.Sheet resistance induction part 1 and magnetic field induction portion 2 be
On same plane (such as first plane), on the first plane, each testing cushion 20 is set between 2 weld pads 10, and respectively
In the two sides of loop construction 21.And the projection of loop construction 21 on the first plane is rectangular-ambulatory-plane.Weld pad 10 and testing cushion 20
It is all metal, and size is identical.
Then referring to figure 3., Fig. 3 indicates circuit arrangement map of the magnetic field induction portion 2 in the second plane.In second plane
Circuit layout from the point of view of, the testing cushion 20A of the first coil 211 of loop construction 21 and 11 side of space to be measured is electrically connected, line
The Ohmic contact road O of second coil 212 and semiconductor layer S1 of coil structures 21 is electrically connected, and forms contact P1, Ohmic contact road O
It is electrically connected with the testing cushion 20B of 11 other side of space to be measured, forms contact P2.Loop construction 21 is around the outer of space 11 to be measured
It is a rectangle in online 21 area encompassed of coil structures of the second plane, and long side is 100~2000 μm, broadside after enclosing
It is 5~500 μm.
Then referring to figure 4., Fig. 4 indicates the hall measurement structure schematic diagram of AA ' line on the first plane along Fig. 3.Such as
Shown in Fig. 4, semiconductor layer S1 is set on substrate W, and from the point of view of AA ' line is along Fig. 3 with the first plane, semiconductor layer S1 includes electricity
Sensillary area SC and Ohmic contact road O, magnetic field induction portion 2 are set to above semiconductor layer S1, and space 11 to be measured exposes beneath electricity
Sensillary area SC.The testing cushion 20A of the first coil 211 of loop construction 21 and 11 side of space to be measured is electrically connected, loop construction 21
The Ohmic contact road O of the second coil 212 and semiconductor layer S1 be electrically connected, form contact P1, Ohmic contact road O and sky to be measured
Between 11 other sides testing cushion 20B be electrically connected, formed contact P2.
In one embodiment, through electric current is applied, make magnetic field induction portion 2 to the inductance of 11 lower semiconductor layer of space to be measured
Portion generates magnetic field vector (B).Referring to formula 1, the value of magnetic field vector (B) and loop-length R (the i.e. length of long side of loop construction 21
The length of degree or broadside) (PLSCONFM) be inversely proportional, and it is directly proportional to total current (NI) of loop construction 21.Therefore, design lines loop knot
It, must also be in view of the size of the value of magnetic field vector in addition to the size in consideration space 11 to be measured when structure 21.
B=NI/R, formula 1, B are magnetic field vectors, and NI is total current, and R is loop-length.
The direction of magnetic field vector (B) and the inductor section SC of semiconductor layer S1 are orthogonal, and pass through space 11 to be measured, magnetic field
Induction part 2 thus forms inductor.After forming inductor, 4 weld pads to sheet resistance induction part 1 or to magnetic field induction portion 2
2 testing cushions 20 apply electric current, the Hall voltage of semiconductor layer can be obtained.Obtain monolithic integrated optical circuit core piece semiconductor-on-insulator
After the sheet resistance of layer, magnetic field vector (B) and Hall voltage, by calculating with obtain the minority carrier concentration of semiconductor layer with
Minority carrier transport factor.
Then referring to figure 5., Fig. 5 indicates flow chart of the Hall Measurement System in running.As shown in figure 5, and please together
Referring to figs. 1 to Fig. 4, the operation steps of Hall Measurement System include:
Step G1: voltage is applied to sheet resistance induction part 1, to obtain sheet resistance.The measurement for first carrying out no magnetic field, through pair
2 weld pads 10 apply voltage, and electric current flow to space 11 to be measured via interconnection line from one of weld pad 10, finally flow to another
Weld pad 10 can measure the electric current between 2 weld pads 10.The ratio of voltage verses current is resistance value (R), referring to formula 2 by resistance value
(Rf) sheet resistance (R can be calculatedS)。
RS=Rf* π/ln2, formula 2, RSIt is sheet resistance, RfIt is resistance value.
Step G2: electric current is applied to magnetic field induction portion 2, to obtain magnetic field vector and Hall voltage.First to 2 testing cushions
Apply electric current A1, carry out the measurement for having magnetic field, so that hall measurement structure H is generated magnetic field vector (B), magnetic field vector (B) can be obtained.
Electric current A2 is applied to online 2 weld pads diagonal in sheet resistance induction part 1 again, measures other 2 weld pads 10 in sheet resistance induction part 1
Between voltage AC and voltage CA.The voltage BD and voltage DB between diagonal online 2 weld pads 10 can be measured in the same way,
Voltage EF (the V between 2 testing cushions 20 can also be measuredEF) and voltage FE (VFE), take the one of the average value of six voltage value summations
Half, referring to the namely voltage AC (V of formula 3AC), voltage CA (VCA), voltage BD (VBD), voltage DB (VDB), voltage EF (VEF), voltage
FE(VFE) summation average value (AVE) half, be defined as Hall voltage (VH)。
VH=AVE (VAC、VCA、VBD、VDB、VEF、VFE)/2, formula 3, VACIt is voltage AC, VCAIt is voltage CA, VBDIt is voltage
BD、VDBIt is voltage DB, VEFIt is voltage EF, VFEIt is voltage FE.
Step G3: sheet resistance, magnetic field vector and Hall voltage is taken to carry out operation.Preferably use computer, mobile phone, PDA
Etc. tool screen, mountable operation program software carry out operation.
Step G4: the data transmitted according to sheet resistance induction part 1 and magnetic field induction portion 2 obtains minority carrier after operation
Concentration (NS).Minority carrier concentration (NS) with the product of electric current A2 (I), magnetic field vector (B) that 2 weld pads 10 are applied at
Direct ratio, with the quantity of electric charge (q), Hall voltage (VH) product be inversely proportional.Through mode 4, which is made to calculate, can obtain minority carrier concentration
(NS)。
NS=(I*B)/(q*VH), formula 4, I is electric current A2, and B is magnetic field vector, and q is the quantity of electric charge, VHIt is Hall voltage.
Step G5: according to minority carrier concentration, operation generates minority carrier transport factor (μ).Minority carrier migration
Rate (μ) and the quantity of electric charge (q), minority carrier concentration (NS), sheet resistance (RS) product be inversely proportional.Through mode 5, which calculates, to be obtained
Minority carrier transport factor (μ).
μ=1/ (q*NS*RS), formula 5, q is the quantity of electric charge, NSIt is minority carrier concentration, RSIt is sheet resistance.
The detailed content of the utility model difference embodiment presented below, definitely to illustrate the utility model, however
The utility model is not limited to following embodiments.
Fig. 6 is please referred to first, and Fig. 6 indicates that an embodiment measures the schematic diagram of sheet resistance.As shown in fig. 6, using the first
One weld pad 31, the second weld pad 33, third weld pad 34, the 4th weld pad 36 carry out without magnetic field the sample to be tested in space 39 to be measured
It measures, voltage is applied to adjacent 2 weld pads, then measures the electric current between other 2 weld pads.Therefore, to the first weld pad 31,
Second weld pad 33 applies voltage, then utilizes the electric current between ampere meter measurement third weld pad 34, the 4th weld pad 36.Referring to formula 6
Resistance value (R can be calculated to the ratio of measured electric current by the voltage appliedf), referring to formula 2 by resistance value (Rf) can calculate
Sheet resistance (RS)。
Rf=V31,33/I34,36, formula 6, V31,33It is the voltage between the first weld pad 31, the second weld pad 33, I34,36It is third
Electric current between weld pad 34, the 4th weld pad 36.
Then Fig. 7 is please referred to, figure indicates that an embodiment measures the schematic diagram of magnetic field vector and Hall voltage.As shown in fig. 7,
Electric current A1 first is applied to the first testing cushion 32, the second testing cushion 35, the amount for having magnetic field is carried out to the sample to be tested in space 39 to be measured
It surveys, so that hall measurement structure H is generated magnetic field vector (B), magnetic field vector (B) can be obtained.Again to diagonally existing in sheet resistance induction part 1
The first weld pad of line 31, third weld pad 34 apply electric current A2, measure sheet resistance induction part 1 in the second weld pad 33, the 4th weld pad 36 it
Between voltage AC and voltage CA.The voltage between diagonal online first weld pad 31, third weld pad 34 can be measured in the same way
BD and voltage DB, can also measure between the first testing cushion 32, the second testing cushion 35, take the average value of six voltage value summations,
Namely voltage AC (VAC), voltage CA (VCA), voltage BD (VBD), voltage DB (VDB), voltage EF (VEF), voltage FE (VFE) it is total
The half of the average value of sum is defined as Hall voltage (VH)。
After obtaining sheet resistance, magnetic field vector, the value of Hall voltage, it can be obtained on sample to be tested after being calculated using arithmetic unit
The minority carrier concentration and minority carrier transport factor of semiconductor layer.Arithmetic unit is to obtain minority carrier according to formula 4 and formula 5
Concentration and minority carrier transport factor.
Using Hall Measurement System provided by the present invention, the photoelectric properties for assessing III-V family device of semiconductor have
It is many to help, the cost for measuring time and measurement equipment can be saved.
The foregoing is merely the preferred embodiment of the utility model, the interest field that is not intended to limit the utility model；
Above description simultaneously, should can be illustrated and implement for the special personage of correlative technology field, therefore other are practical without departing from this
The lower equivalent change or modification completed of novel disclosed spirit, should be included in claim.
Claims (10)
1. a kind of hall measurement structure characterized by comprising
Substrate；
Semiconductor layer is set on the substrate, and the semiconductor layer has pattern, and the pattern includes inductor section, 4 weld pads
Corresponding area, X font area and Ohmic contact road, the inductor section are located at the center in X font area, and the weld pad corresponds to area two
Two centered on the inductor section, is arranged in the diagonal angle in X font area；
Sheet resistance induction part is set on the semiconductor layer, including 4 weld pads and space to be measured, on the first plane, often
Each weld pad that one weld pad covers the semiconductor layer corresponds to area；And
Magnetic field induction portion is set on the semiconductor layer, including the space to be measured, 2 testing cushions and with one of them institute
The loop construction of testing cushion connection is stated, the loop construction ring is set around the space to be measured, in first plane, institute
State space to be measured expose under the semiconductor layer the inductor section, another testing cushion, the loop construction with
The Ohmic contact road of the semiconductor layer contacts.
2. hall measurement structure as described in claim 1, which is characterized in that the sheet resistance induction part and the magnetic field induction
Portion is that in the same plane, on the plane, each testing cushion is set between 2 weld pads, and respectively in institute
State the two sides of loop construction.
3. hall measurement structure as described in claim 1, which is characterized in that in the second plane, the institute of the semiconductor layer
State inductor section be long side be 100~2000 μm, broadside is 5~500 μm of rectangle, wherein second plane is by X-axis and Y
The plane that axis is constituted.
4. hall measurement structure as described in claim 1, which is characterized in that the inductor section of the semiconductor layer with it is described
The size in space to be measured is identical.
5. hall measurement structure as described in claim 1, which is characterized in that logical to the weld pad of the sheet resistance induction part
With voltage, to measure the sheet resistance of the inductor section of the semiconductor layer.
6. hall measurement structure as described in claim 1, which is characterized in that the weld pad to the sheet resistance induction part or
The testing cushion in the magnetic field induction portion passes to electric current, to obtain the Hall voltage of the inductor section of the semiconductor layer.
7. hall measurement structure as described in claim 1, which is characterized in that logical to the testing cushion in the magnetic field induction portion
With electric current, to generate the magnetic field vector of the inductor section of the semiconductor layer.
8. hall measurement structure as claimed in claim 7, which is characterized in that the loop construction in the magnetic field induction portion with
The Ohmic contact road of the semiconductor layer is electrically connected.
9. the hall measurement structure as described in claim 1,2 or 8, which is characterized in that the loop construction is on the plane
Projection be rectangular-ambulatory-plane.
10. hall measurement structure as described in claim 1, which is characterized in that the semiconductor layer is aluminium gallium nitride alloy, indium nitride
Gallium or aluminum indium gallium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822034082.8U CN209460196U (en) | 2018-12-05 | 2018-12-05 | Hall measurement structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822034082.8U CN209460196U (en) | 2018-12-05 | 2018-12-05 | Hall measurement structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209460196U true CN209460196U (en) | 2019-10-01 |
Family
ID=68038832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822034082.8U Active CN209460196U (en) | 2018-12-05 | 2018-12-05 | Hall measurement structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN209460196U (en) |
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2018
- 2018-12-05 CN CN201822034082.8U patent/CN209460196U/en active Active
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Legal Events
| Date | Code | Title | Description |
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| TR01 | Transfer of patent right |
Effective date of registration: 20191118 Address after: Room 01, 13 / F, central city, 11 Haisheng Road, Tsuen Wan, New Territories, Hong Kong, China Patentee after: Gemini semiconductor manufacturing (Hong Kong) Co., Ltd Address before: Second floor, No.38 Keyi street, Zhunan Town, miaoso County, Taiwan, China Patentee before: JET TECHNOLOGY AND TECHNOLOGY CO., LTD. |
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| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210913 Address after: Room 2208, New Technology Plaza, 34 Dayou street, San Po Kong, Kowloon, China Patentee after: Huipu Co.,Ltd. Address before: Room 01, 13 / F, central city, 11 Haisheng Road, Tsuen Wan, New Territories, Hong Kong, China Patentee before: Gemini semiconductor manufacturing (Hong Kong) Co.,Ltd. |
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| TR01 | Transfer of patent right |