CN209401606U - A kind of semiconductor devices - Google Patents
A kind of semiconductor devices Download PDFInfo
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- CN209401606U CN209401606U CN201920083386.5U CN201920083386U CN209401606U CN 209401606 U CN209401606 U CN 209401606U CN 201920083386 U CN201920083386 U CN 201920083386U CN 209401606 U CN209401606 U CN 209401606U
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Abstract
The utility model provides a kind of semiconductor devices, comprising: wafer, including wafer frontside and backside of wafer, backside of wafer include the metal plating layer on back carrying on the back gold process and being formed；And it is attached to the metal patch in at least partly region of backside of wafer；Wherein, the center of metal patch is overlapped with the center of wafer, and plane formula is integrally presented in the backside of wafer for being pasted with metal patch.Metal patch is attached in backside of wafer, the intensity of wafer is improved, effectively prevent silicon wafer warpage phenomenon occur, reduces the risk of wafer damage in handling process.Backside of wafer is plane on the whole after attaching metal patch, can test on traditional tester table wafer, improve the utilization rate of tester table, reduce the cost of wafer test.After test, without removing the metal patch, subsequent cutting encapsulation process can be entered.
Description
Technical field
The utility model relates to technical field of integrated circuits, more particularly to semiconductor power device manufacturing field, more
Body it is related to a kind of semiconductor devices.
Background technique
In integrated circuits, semiconductor devices, especially power device are an important application fields.Power device system
During making, the back process processing procedure of wafer all has a major impact the reduction of device resistance and subsequent encapsulation.For the back side
The grinding technics of manufacturing process mainly has Taiko technique and traditional non-Taiko (non-Taiko) grinding work in the prior art
Skill.When grinding using Taiko technique to wafer, the form peripheral edge portions of wafer will be retained, only to grinding in wafer
Slimming.The technique can reduce the carrying risk of slim wafer, and can reduce wafer caused by traditional grinding technics and stick up
Qu Xianxiang improves the intensity of wafer.
However, since wafer (the abbreviation Taiko wafer) back side after Taiko process is there are depressed area, and it is traditional
Non-Taiko grinding technics treated the back side wafer (abbreviation non-Taiko) is plane formula, this results in testing traditional wafer
Probe station can not placing Taiko wafer, otherwise can test the probe station of Taiko wafer can not placing tradition wafer.
In order to test Taiko wafer, currently used method is all to cooperate absorption to place by changing the pattern of chuck
Taiko wafer, such as set card to there is boss corresponding with the depressed area of Taiko backside of wafer.This change chuck
Mode be related to scrap build, will definitely increase testing cost, and after being transformed can not zero cost reduction, therefore can not be compatible with
Test traditional wafer.Thus leading to the utilization rate of wafer test board reduces, wafer test increased costs.
Utility model content
In view of the drawbacks described above and deficiency of the prior art, the utility model provides a kind of semiconductor devices, the semiconductor device
The backside of wafer of part is in plane formula, and either Taiko wafer or traditional non-Taiko wafer can be in traditional test
It is tested on board, without making any change to tester table, to improve the utilization rate of wafer test board, is reduced brilliant
Circle testing cost.
According to the utility model, a kind of semiconductor devices is provided, the semiconductor devices includes:
Wafer, including wafer frontside and backside of wafer, the backside of wafer include the back metal plating carrying on the back gold process and being formed
Layer；And
It is attached to the metal patch in at least partly region of the backside of wafer；
Wherein, the center of the metal patch is overlapped with the center of the wafer, and is pasted with the metal patch
Plane formula is integrally presented in the backside of wafer.
Optionally, the metal patch includes disc shape metal patch, and the metal patch is in gold, silver and copper sheet
Any one.
Optionally, the thickness of the intermediate region of the backside of wafer is less than the thickness of peripheral edge, the intermediate region shape
As depressed area, the metal patch is attached on the surface of the depressed area, and the shape of the metal patch, size with
Shape, the size of the depressed area, which are coincide, to be worked as.
Optionally, the diameter of the metal patch is between 190mm~290mm or 200mm~300mm, the metal patch
Thickness between 0.3mm~0.8mm.
Optionally, the semiconductor devices further includes coated in the tin cream between the backside of wafer and the metal patch
Layer, the metal patch are bonded in the backside of wafer by the tin paste layer.
The third aspect according to the present utility model, the utility model provide a kind of semiconductor devices, the semiconductor devices
Including the individual crystal grain being cut into from wafer and it is attached to the metal patch at the crystal grain back side.
Fourth aspect according to the present utility model, the utility model provide a kind of semiconductor devices, the semiconductor devices
The metal patch including the multiple grain combination being cut into from wafer and the back side for being attached to the multiple grain combination, it is described
The metal patch at multiple grain combination and the back side for being attached to the multiple grain combination is carried out in the form of power modules
Encapsulation, wherein in the power modules, the metal patch is not completely cut through.
As described above, the semiconductor devices of the utility model has the following technical effect that
1, by attaching metal patch in backside of wafer, the intensity of wafer is improved, while can reduce in handling process
The risk of wafer damage, for traditional non-Taiko wafer, attaching metal patch can also effectively prevent silicon wafer warpage occur
Phenomenon.
2, after backside of wafer attaches metal patch, backside of wafer is plane on the whole, particularly with Taiko wafer,
The depressed area at its back side attaches metal patch, and the thickness of patch is consistent with the depth of depressed area, so that the back of Taiko wafer
Face is integrally in plane formula.Wafer can be tested directly on traditional tester table in this way.Improve the benefit of tester table
With rate, the cost of wafer test is reduced.
3, after being pasted with the wafer of metal patch after tested, without removing the metal patch, subsequent cutting can be entered
Encapsulation process, that is, the paster technique before cutting encapsulation is moved to wafer test by the method, semi-conductor device manufacturing method of the utility model
Processing procedure before, this will not both pollute the environment of test phase, while be suitble to subsequent cutting and encapsulation procedure.
Detailed description of the invention
Can be more clearly understood the feature and advantage of the utility model by reference to attached drawing, attached drawing be schematically without
It is interpreted as carrying out any restrictions to the utility model, in the accompanying drawings:
Fig. 1 is shown as the radial cross section of the wafer after TAIKO process.
Fig. 2 is shown as testing the radial cross section of the chuck of wafer shown in FIG. 1 in the prior art.
Fig. 3 is shown as the flow chart of method, semi-conductor device manufacturing method described in the utility model embodiment one.
The radial cross section for the wafer that the preferred embodiment that Fig. 4 is shown as embodiment one provides.
Fig. 5 is shown as carrying the radial cross section of the chuck of wafer shown in Fig. 4.
The radial cross section for the wafer that the more preferred embodiment that Fig. 6 is shown as embodiment one provides.
Fig. 7 is shown as the radial cross section of the wafer of the offer of method, semi-conductor device manufacturing method described in embodiment two.
Fig. 8 is shown as the schematic diagram of wafer cutting mode in the method, semi-conductor device manufacturing method of the offer of embodiment three.
Fig. 9 is shown as the schematic diagram of another wafer cutting mode in the method, semi-conductor device manufacturing method of the offer of embodiment three.
Figure 10 is shown as the enlarged diagram in region shown in box A in Fig. 9.
Appended drawing reference
10 wafers
101 wafer frontsides
102 backside of wafers
The depressed area of 103 backside of wafers
The peripheral edge of 106 wafers
The chuck of 20 improved tester tables
201 boss
The chuck of 20 ' traditional test boards
30 crystal grain
40 wafers
401 wafer frontsides
402 backside of wafers
403 sunk areas
404 metal patches
405 metal plating layer on back
The peripheral edge of 406 wafers
50 power modules
70 wafers
701 wafer frontsides
702 backside of wafers
704 metal patches
705 metal plating layer on back
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Based on the implementation in the utility model
Example, those skilled in the art's every other embodiment obtained without creative efforts, belongs to this reality
With novel protected range.
In fabrication of semiconductor device, need to carry out wafer a series of processing, such as grinding back surface reduction processing,
Back gold processing etc..In the prior art, wafer reverse side grinding reduction process mainly includes Taiko technique and traditional non-Taiko
Technique.Traditional non-Taiko technique carries out grinding to the whole wafer back side and is thinned, since wafer thickness reduces after being thinned, easily
There is silicon wafer warpage phenomenon.To prevent silicon wafer warpage, Taiko technique is generallyd use.Compared to traditional non-Taiko technique,
Taiko technique carrying out grinding to wafer or when grinding, retains the peripheral edge part of wafer, only on the inside of the peripheral edge
Between region carry out grinding slimming.As shown in Figure 1, showing the radial section signal of the wafer 10 after Taiko process
Figure, it can be seen that, wafer frontside 101 is still plane formula, and the peripheral edge 106 of wafer 10 is retained, peripheral edge 106
The intermediate region of inside will appear depressed area 103.Taiko technique can reduce silicon wafer warpage, and it is strong to improve wafer to a certain extent
Degree, however some column problems are but faced when wafer test.
When testing above-mentioned Taiko wafer, in order to better adapt to the back side shape of wafer 10 and support wafer 10,
Usually the chuck 20 of traditional wafer test board of support wafer is transformed, as shown in Fig. 2, chuck 20 is designed as having
There is the construction of boss 201.The form and dimension of the depressed area 103 of the boss 201 and backside of wafer 102 is adapted, so as to more
It is firm more uniformly to support wafer, carry out subsequent middle survey.
However, being transformed as shown in Figure 2 to chuck, it is related to scrap build, will definitely increase testing cost, and change
After making can not zero cost reduction, also can not compatibility test tradition non-Taiko wafer.Thus lead to the utilization of wafer test board
Rate reduces, wafer test increased costs.
Embodiment one
The problems such as in order to overcome the low utilization rate of wafer test board existing in the prior art, testing cost increase, this
Embodiment provides a kind of method, semi-conductor device manufacturing method, as shown in figure 3, this method comprises the following steps:
One wafer, including wafer frontside and backside of wafer are provided, grinding back surface reduction processing and back are carried out to the wafer
Gold processing；
Metal patch, the center of the metal patch and the wafer are attached in at least partly region of the backside of wafer
Center be overlapped；Wherein, plane formula is integrally presented in the backside of wafer for attaching the metal patch.
In a preferred embodiment of the present embodiment, the metal patch includes disc shape metal patch, the metal patch
Any one of piece in gold, silver and copper sheet.It is highly preferred that considering for economic cost, which can be selected as copper
Piece.
It include following step in the step of patch is arranged in the back side of the wafer in another preferred embodiment of the present embodiment
It is rapid:
In the back side brushing tin cream of the wafer；
The metal patch is attached on the tin cream；
The wafer is heated, the metal patch is bonded together by tin cream and the wafer.
In the present embodiment, the back side of wafer is pasted with metal patch, can effectively prevent silicon wafer warpage phenomenon occur, improves
The intensity of wafer reduces the risk of wafer damage in handling process.And the metal patch will not influence the subsequent survey of wafer
Examination can directly carry out subsequent cutting encapsulation after the completion of test.The tin cream is common solder in semiconductor field, is had
Good electric conductivity will not influence the follow-up test of wafer.And tin cream enables to wafer and patch to be firmly combined, subsequent
In the techniques such as carrying or cutting, wafer will not be made to damage.
In a preferred embodiment of the present embodiment, as shown in figure 4, the wafer 40 provided includes wafer frontside 401, wafer
The back side 402 carries out grinding reduction processing to the backside of wafer using taiko technique, described in reservation in the preferred embodiment
The peripheral edge 406 of wafer 40 is ground along intermediate region of the inside of the peripheral edge 406 to the backside of wafer 402
Wear away thin until required thickness, forms depressed area 403 in the intermediate region of the backside of wafer 402.In the table of the recess 403
The attached interior metal patch 404 of face paste, the diameter of the metal patch 404 is between 190mm~290mm, the thickness of the metal patch
Between 0.3mm~0.8mm.The width of the peripheral edge 406 is generally between 3mm~5mm.
In the further embodiment of above preferred embodiment, wafer 40 includes 8 " and 12 " wafer, described 8 "
Wafer 40 in, the diameter of the depressed area 403 is about 190mm, and depth is between 0.3mm~0.8mm.In the 8 " wafer
In, the diameter of the metal patch 404 is about 190mm, and thickness is between 0.3mm~0.8mm.In described 12 " wafer, institute
The diameter for stating depressed area is about 290mm, and depth is between 0.3mm~0.8mm.In the 12 " wafer, the metal patch
404 diameter is about 290mm, and thickness is between 0.3mm~0.8mm.The institute of the depressed area of the wafer is as above set
To state metal patch can be filled up completely the depressed area 403, so that the back side of wafer plane formula on the whole.For above-mentioned metal
The diameter and thickness of patch 404, can be according to the wafer size of actual test and its size of depressed area in above-mentioned diameter and thickness
It spends and chooses suitably sized value or size range in range.
As shown in figure 5, the wafer 40 being pasted with after the metal patch 404 can be directly placed at traditional test board
It on chuck 20 ', is tested on traditional tester table, change described in Fig. 2 without the chuck 20 ' tester table
It makes.Scrap build step is thereby reduced, testing cost is reduced, improves the utilization rate of tester table.
In the more preferred embodiment of the present embodiment, as shown in fig. 6, backside of wafer 402 includes being carried on the back gold process to be formed
Metal plating layer on back 405.Wherein, the sum of thickness of the metal patch 404 and metal plating layer on back 405 and the depressed area
403 depth is suitable.
The backside of wafer for the semiconductor devices that the present embodiment obtains is plane formula, can be directly placed at conventional measurement test-run a machine
It on the chuck of platform, is tested on traditional tester table, carries out any transformation without the chuck to tester table.Thus subtract
Lack scrap build step, reduced testing cost, improves the utilization rate of tester table.
Embodiment two
The present embodiment equally provides a kind of method, semi-conductor device manufacturing method, repeats no more with the something in common of embodiment one,
The difference is that:
In the present embodiment, it as shown in fig. 7, the wafer 70 provided includes wafer frontside 701, backside of wafer 702, uses
Non-taiko technique carries out grinding reduction processing to the backside of wafer 702 until required thickness, backside of wafer 702 are pasted with
Metal patch 704.In this embodiment, metal patch 704 covers the whole wafer back side 702, and the diameter of the metal patch is situated between
In 200mm~300mm, the thickness of the metal patch is between 0.3mm~0.8mm.
In the further embodiment of the present embodiment, wafer 70 includes 8 " and 12 " wafer, in described 8 " wafer
In 70, the diameter of metal patch 704 is about 200mm, and thickness is between 0.3mm~0.8mm.In described 12 " wafer 70, gold
The diameter for belonging to patch 704 is about 300mm, and thickness is between 0.3mm~0.8mm.For the diameter and thickness of above-mentioned metal patch 704
Degree, equally can choose conjunction according to the wafer size of actual test and its size of depressed area in above-mentioned diameter and thickness range
Suitable size value or size range.
The backside of wafer 702 is completely covered in metal patch as described above, and backside of wafer 702 is still plane formula on the whole
's.Still as shown in fig. 7, the backside of wafer 702 of wafer 70 includes the metal plating layer on back 705 through carrying on the back gold process formation.
In other preferred embodiments of the present embodiment, metal patch can be pasted with the back side of endless all standing wafer
It is attached in the partial region of backside of wafer.At this point it is possible to carry out that place is thinned to the region that backside of wafer needs to attach metal patch
Reason, then attaches metal patch again.And guarantee that be provided with the backside of wafer of patch is still plane formula on the whole.
As described above, attaching metal patch in backside of wafer, the intensity of wafer is improved, can effectively prevent wafer occur
Warping phenomenon, while can reduce the risk that wafer damages in handling process.And the metal patch will not influence wafer
Follow-up test.
Embodiment three
The present embodiment equally provides a kind of method, semi-conductor device manufacturing method, no longer superfluous with the something in common of embodiment one or two
It states, the difference is that:
The method of the present embodiment further includes testing the wafer for being pasted with the metal patch；
The wafer for being pasted with the metal patch is cut and encapsulated after the completion of test.
Before carrying out the cutting encapsulation of wafer, grinding back surface can also be carried out to the wafer for being pasted with metal patch and subtracted
It is thin.
In a preferred embodiment of the present embodiment, as shown in figure 8, can be by wafer together with the metal patch one at its back side
Cutting is played, independent crystal grain 30 is formed, then independent crystal grain 30 is packaged.
In another preferred embodiment of the present embodiment, by taking wafer shown in Fig. 7 as an example, to the gold of wafer and backside of wafer
Belong to patch 704 to be cut, still, in the preferred embodiment, in the form of multiple grain combination to wafer and metal patch 704
It is cut, such as is cut in the form of shown in the box A in Fig. 93 × 3 die combinations, the multiple grain group being cut into
It closes as shown in Figure 10.In multiple grain combination, the metal patch 704 at each crystal grain back side is not exclusively cut through, and the multiple grain
Combination is packaged in the form of power modules 50.
In the present embodiment, as described above, after being pasted with the wafer of metal patch after tested, without removing metal patch
Piece is directly entered subsequent cutting encapsulation process, that is, the method, semi-conductor device manufacturing method of the utility model will be before cutting encapsulation
Paster technique moves to the processing procedure before wafer test, this will not both pollute the environment of test phase, while be suitble to subsequent
Cutting and encapsulation procedure.
Example IV
The present embodiment provides a kind of semiconductor devices, which includes:
Wafer, the wafer include wafer frontside and backside of wafer, and the backside of wafer includes the back side carrying on the back gold process and being formed
The coat of metal；And
It is attached to the patch in at least partly region of the backside of wafer；
Wherein, the center of the metal patch is overlapped with the center of the wafer, and is pasted with the metal patch
Plane formula is integrally presented in the backside of wafer.
In a preferred embodiment of the present embodiment, the metal patch includes disc shape metal patch, the metal patch
Any one of piece in gold, silver and copper sheet.It is highly preferred that considering for economic cost, which can be selected as copper sheet.
In another preferred embodiment of the present embodiment, the semiconductor devices further includes being coated in the backside of wafer
Tin paste layer at least partly between region and the metal patch, the metal patch are bonded in the crystalline substance by the tin paste layer
The circle back side.
Referring again to Fig. 4, in another preferred embodiment of the present embodiment, the thickness of the peripheral edge 406 of wafer 40 is big
Thickness in intermediate region, the intermediate region form depressed area 403, and metal patch 404 is attached to the surface of depressed area 403
On, in general, the width of the peripheral edge 406 is between 3mm~5mm.In the preferred embodiment, the diameter of metal patch 404 with
The diameter of the depressed area 403 is suitable, and thickness is suitable with the depth of depressed area 403, the diameter of the metal patch 404 between
190mm~290mm, the thickness of the metal patch is between 0.3mm~0.8mm.For example, in 8 " wafers, metal patch 404
Diameter is approximately 190mm or 200mm, and thickness is between 0.3mm~0.8mm；In 12 " wafers, the diameter of metal patch 404 is approximate
290mm or 300mm, thickness is between 0.3mm~0.8mm.
It, can wafer size according to actual test and its depressed area for the diameter and thickness of above-mentioned metal patch 404
Size suitably sized value or size range are chosen in above-mentioned diameter and thickness range.
Referring again to Fig. 6, in another preferred embodiment of the present embodiment, the backside of wafer 402 further includes passing through back
The metal plating layer on back 405 that gold process is formed.
Referring again to Fig. 7, in another preferred embodiment of the present embodiment, the wafer 70 of semiconductor devices include wafer just
Face 701, backside of wafer 702.Be pasted with metal patch 704 in backside of wafer 702, the diameter of the metal patch 704 between
200mm~300mm, the thickness of the metal patch is between 0.3mm~0.8mm.In this embodiment, metal patch 704 covers
The entire back side 702.
Wafer 70 includes 8 " and 12 " wafer, and in described 8 " wafer 70, the diameter of metal patch 704 is about
200mm, thickness is between 0.3mm~0.8mm.In described 12 " wafer 70, the diameter of metal patch 704 is about 300mm,
Thickness is between 0.3mm~0.8mm.As above the back side 702 is completely covered in the metal patch that the wafer is arranged in, so that wafer
The back side is still plane formula on the whole.It, equally can be according to actual test for the diameter and thickness of above-mentioned metal patch 704
The size of wafer size and its depressed area chooses suitably sized value or size range in above-mentioned diameter and thickness range.Still
As shown in fig. 7, backside of wafer 702 further includes the metal plating layer on back 705 through carrying on the back gold process formation.
In the preferred embodiment, metal patch can also be arranged and be carried on the back in wafer with the back side of endless all standing wafer
In the partial region in face.At this point it is possible to which the region for needing to be arranged patch to backside of wafer carries out reduction processing, then patch is set again
Piece.And guarantee that be provided with the backside of wafer of patch is still plane formula on the whole.
The semiconductor devices of the present embodiment, backside of wafer are in plane formula on the whole, can be directly placed at traditional test
It on the chuck of board, is tested on traditional tester table, carries out one institute of embodiment without the chuck to tester table
The transformation stated.Scrap build step is thereby reduced, testing cost is reduced, improves the utilization rate of tester table.
Embodiment five
The present embodiment provides a kind of semiconductor devices, and referring again to Fig. 8, which includes being cut into from wafer
Individual crystal grain 30, and it is attached to the metal patch at 30 back side of crystal grain.The crystal grain 30 is packaged with independent granular form.
Embodiment six
The present embodiment provides a kind of semiconductor devices, and referring again to Figure 10, which includes being cut into from wafer
Multiple grain combination, such as 3 × 3 die combinations shown in Fig. 10.Multiple grain combination and described it is attached to multiple grain combination
The metal patch at the back side be packaged in the form of power modules 50, wherein in the power modules 50, the gold
Belong to patch not completely cut through.
To sum up, the utility model semiconductor devices provided by the above embodiment has the following technical effect that
1, by attaching metal patch in backside of wafer, the intensity of wafer is improved, while can reduce in handling process
The risk of wafer damage, for traditional non-Taiko wafer, attaching metal patch can also effectively prevent silicon wafer warpage occur
Phenomenon.
2, after backside of wafer attaches metal patch, backside of wafer is plane on the whole, particularly with Taiko wafer,
The depressed area at its back side attaches metal patch, and the thickness of patch is consistent with the depth of depressed area, so that the back of Taiko wafer
Face is integrally in plane formula.Wafer can be tested directly on traditional tester table in this way.Improve the benefit of tester table
With rate, the cost of wafer test is reduced.
3, after being pasted with the wafer of metal patch after tested, without removing the metal patch, subsequent cutting can be entered
Encapsulation process, that is, the paster technique before cutting encapsulation is moved to wafer test by the method, semi-conductor device manufacturing method of the utility model
Processing procedure before, this will not both pollute the environment of test phase, while be suitble to subsequent cutting and encapsulation procedure.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type, those skilled in the art can various modification can be adapted and becomes in the case where not departing from the spirit and scope of the utility model
Type, such modifications and variations are each fallen within be defined by the appended claims within the scope of.
Claims (7)
1. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Wafer, including wafer frontside and backside of wafer, the backside of wafer include the metal plating layer on back carrying on the back gold process and being formed；With
And
It is attached to the metal patch in at least partly region of the backside of wafer；
Wherein, the center of the metal patch is overlapped with the center of the wafer, and is pasted with the described of the metal patch
Plane formula is integrally presented in backside of wafer.
2. semiconductor devices according to claim 1, which is characterized in that the metal patch includes disc shape metal patch
Piece, any one of the metal patch in gold, silver and copper sheet.
3. semiconductor devices according to claim 1, which is characterized in that the thickness of the intermediate region of the backside of wafer is small
In the thickness of peripheral edge, the intermediate region is formed as depressed area, and the metal patch is attached to the surface of the depressed area
On, and the shape of the metal patch, size and shape, the size of the depressed area are coincide and are worked as.
4. semiconductor devices according to claim 1, which is characterized in that the diameter of the metal patch between 190mm~
290mm or 200mm~300mm, the thickness of the metal patch is between 0.3mm~0.8mm.
5. semiconductor devices described in any one of -4 according to claim 1, which is characterized in that the semiconductor devices further includes
Coated in the tin paste layer between the backside of wafer and the metal patch, the metal patch is bonded in by the tin paste layer
The backside of wafer.
6. a kind of semiconductor devices, which is characterized in that including the list being cut into from wafer of any of claims 1-5
Only crystal grain and the metal patch for being attached to the crystal grain back side.
7. a kind of semiconductor devices, which is characterized in that more including being cut into from wafer of any of claims 1-5
Die combinations and the metal patch for being attached to the back side that the multiple grain combines, the multiple grain are combined and are attached to described more
The metal patch at the back side of die combinations is packaged in the form of power modules, wherein in the power modules, institute
Metal patch is stated not completely cut through.
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| CN201920083386.5U CN209401606U (en) | 2019-01-18 | 2019-01-18 | A kind of semiconductor devices |
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| CN201920083386.5U CN209401606U (en) | 2019-01-18 | 2019-01-18 | A kind of semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863596A (en) * | 2020-07-21 | 2020-10-30 | 绍兴同芯成集成电路有限公司 | Manufacturing process of copper column and thick film copper plating structure of wafer |
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2019
- 2019-01-18 CN CN201920083386.5U patent/CN209401606U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863596A (en) * | 2020-07-21 | 2020-10-30 | 绍兴同芯成集成电路有限公司 | Manufacturing process of copper column and thick film copper plating structure of wafer |
| CN111863596B (en) * | 2020-07-21 | 2023-05-26 | 绍兴同芯成集成电路有限公司 | Manufacturing process of copper column and thick film copper plating structure of wafer |
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