CN114937615A - Method for realizing packaging structure of ultrathin wafer level wafer - Google Patents
Method for realizing packaging structure of ultrathin wafer level wafer Download PDFInfo
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- CN114937615A CN114937615A CN202210604005.XA CN202210604005A CN114937615A CN 114937615 A CN114937615 A CN 114937615A CN 202210604005 A CN202210604005 A CN 202210604005A CN 114937615 A CN114937615 A CN 114937615A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 239000010931 gold Substances 0.000 claims abstract description 34
- 229910052737 gold Inorganic materials 0.000 claims abstract description 33
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000003292 glue Substances 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 239000000126 substance Substances 0.000 claims abstract description 9
- 235000012431 wafers Nutrition 0.000 claims description 103
- 239000010410 layer Substances 0.000 claims description 64
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 239000011368 organic material Substances 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 19
- 239000011521 glass Substances 0.000 claims description 18
- 239000007788 liquid Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000000178 monomer Substances 0.000 claims description 6
- 238000002791 soaking Methods 0.000 claims description 6
- 229920001187 thermosetting polymer Polymers 0.000 claims description 6
- 239000004634 thermosetting polymer Substances 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229920001169 thermoplastic Polymers 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000009736 wetting Methods 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000227 grinding Methods 0.000 abstract description 8
- 239000012634 fragment Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
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- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for realizing a packaging structure of an ultrathin wafer level wafer, and belongs to the technical field of semiconductor packaging. The front bump of the chip is protected by coating the temporary bonding glue on the front surface of the wafer, the wafer is loaded by a temporary bonding slide way, and then the slide is separated by a chemical de-bonding way, so that the packaging way can overcome the problems of fragments and warping caused by directly grinding the wafer into an ultrathin sheet and a series of problems of incapability of operating a back gold layer due to overlarge warping, and therefore, the production line process can meet the requirement of operating the ultrathin sheet and obtain lower packaging resistance.
Description
Technical Field
The invention relates to a method for realizing a packaging structure of an ultrathin wafer, belonging to the technical field of semiconductor packaging.
Background
At present, with the continuous development of 5G industry, consumer electronics and power electronics, the performance requirements of electronic products are continuously improved. For power supply products such as MOSFET, the front surface of a chip is provided with a photoresist protection layer and a metal bump, the back surface of the chip is provided with a metal layer, namely a back gold layer for short, and the reduction of resistance and the improvement of product performance are realized by continuously reducing the packaging thickness of the chip and increasing the thickness of the back gold layer; along with the trend of ever-decreasing product resistance, the client is also developing towards the trend of thinner and thinner chips.
The method for realizing the packaging structure of the ultrathin wafer level comprises the following steps: and forming a protective layer on the front surface of the wafer through photoetching, forming a metal bump through electroplating or chemical plating, and then directly grinding the back surface of the wafer and then arranging a back gold layer.
The existing packaging method has the following problems: the mechanical strength of the wafer is directly related to the thickness of the wafer, the wafer after grinding is extremely fragile along with the reduction of the thickness of the wafer, the risk of fragments and the like in the subsequent process is easily caused, the thinner the thickness of the wafer is, the larger the warpage after the corresponding grinding is, and the large warpage can cause the problems that the subsequent process cannot be operated or the hidden cracks/fragments and the like occur during wafer loading and vacuum adsorption. In view of the above problems, the thinnest grinding sheet thickness supported by directly grinding 8inch and 12inch wafers by the current packaging method is 6mil, which cannot meet the requirement of ultra-thin sheet packaging in the production process.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a method for realizing a packaging structure of an ultrathin wafer, which solves the problems of fragments and warping.
The technical scheme of the invention is as follows:
the invention provides a method for realizing a packaging structure of an ultrathin wafer, which comprises the following process steps:
the method comprises the following steps: arranging a protective layer and a protective layer opening on the upper surface of the wafer through a photoetching process, wherein the protective layer opening corresponds to the chip electrode of the wafer, and the chip electrode of the wafer is embedded in the silicon substrate;
step two: arranging a metal bump at the opening of the protective layer of the wafer through an electroplating or chemical plating process;
step three: forming semi-solid temporary bonding glue on the upper surface of the wafer, wherein the thickness of the temporary bonding glue is greater than the sum of the heights of the protective layer and the metal bump;
step four: preparing a slide glass, pretreating the slide glass, coating a first organic material layer in an annular width range of 2.5-3 mm of the edge of the inner surface of the slide glass, and coating a second organic material layer on the whole inner circle surface of the slide glass;
step five: bonding the inner surface of the slide glass, the temporary bonding glue and the wafer together by a temporary bonding method at a certain temperature and pressure to form a temporary wafer body;
step six: thinning the silicon substrate on the back of the temporary wafer body by a lapping method to achieve the lapping target thickness of the wafer;
step seven: arranging a back gold layer on the back of the temporary wafer body through sputtering, electroplating or evaporation process;
step eight: sequentially carrying out gluing, exposure and development processes to form a photoresist pattern and a photoresist pattern opening on the back gold layer, removing redundant back gold layers and redundant photoresist in the photoresist pattern opening in a corrosion mode to form a specific metal pattern, wherein the photoresist pattern opening I of the photoresist pattern is in a transverse and longitudinal strip shape which is vertically staggered and communicated with each other, so that the back gold layer is pre-divided into a plurality of chip monomers according to the size of a chip, and one corner of each chip monomer is provided with a photoresist pattern opening II; removing the back gold layers in the photoresist pattern opening I and the photoresist pattern opening II through a corrosion process, and forming transverse and longitudinal scribing channels and circular identification points on the back gold layers after removing the photoresist;
step nine: separating the slide glass in a chemical bonding-breaking mode, and removing the temporary bonding glue on the front surface of the wafer;
the bonding-debonding manner is as follows:
erecting a temporary wafer body, placing the temporary wafer body in a device for supporting bonded wafers, clamping the temporary wafer body front and back, suspending the temporary wafer body on the upper edge of a groove body for preventing soaking solution, rotatably soaking the edge position of the temporary wafer body in organic solution for about 1-2 hours, and carrying out chemical reaction for removing viscosity between the organic solution and a first organic material layer;
taking out the soaked temporary wafer body, placing the temporary wafer body on a hot plate, wherein the temperature of the hot plate is 80-100 ℃, then sucking the exposed surface of the slide glass by adopting a tool with certain specific suction force, and then manually removing the slide glass, or separating the slide glass by adopting an automatic machine;
step ten: and cleaning the surface of the wafer with the slide glass removed to form the ultrathin wafer with the scribing channels and the identification points.
Further, in the second step, the metal bump is made of one or a combination of Cu, Sn, Ni, Pd, and Au.
Further, in the second step, a tin layer for soldering is electroplated or chemically plated on the top of the metal bump.
Further, in the third step, the material of the temporary bonding glue is a liquid thermoplastic polymer organic material.
Further, in the fourth step, the material of the first organic material layer is a liquid thermosetting polymer material.
Further, in the fourth step, the material of the second organic material layer is a liquid thermosetting polymer material, and has a property of not wetting with the first organic material layer.
Further, in the sixth step, the lapping target thickness of the 12inch wafer is 4 mils, and the lapping target thickness of the 8inch wafer is 3 mils.
Further, in the seventh step, the material of the back gold layer is one or a combination of several metals of Cu, Cr, Ti, Ni, and Ag.
Further, in the eighth step, the photoresist pattern opening ii is circular.
Advantageous effects
The front surface of the wafer is coated with the temporary bonding glue, so that the front surface of the chip is protected from being protruded, the wafer is loaded in a temporary bonding slide way, the packaging mode can solve the problems of fragments and warping caused by the fact that the wafer is directly ground into an ultrathin sheet, and a series of problems that a back gold layer cannot be operated due to too large warping, and therefore the production line process can meet the requirement of operating the ultrathin sheet, and lower packaging resistance is obtained.
Drawings
FIG. 1 is a flow chart of a method for implementing a package structure of an ultra-thin wafer according to the present invention;
fig. 2 to 16 are flow charts of processes of an embodiment of a method for implementing a package structure of an ultra-thin wafer according to the present invention;
wherein: wafer 100
Protective layer opening 123
Silicon based 130
First organic material layer 610
Second organic material layer 620
A back gold layer 700.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
The invention discloses a flow chart of a method for realizing a packaging structure of an ultrathin wafer, which is shown in figure 1:
step S1: arranging a protective layer and a protective layer opening thereof on the upper surface of the wafer through a photoetching process;
step S2: arranging a metal bump at the opening of the protective layer of the wafer;
step S3: forming semi-solid temporary bonding glue on the upper surface of the wafer;
step S4: preparing a carrier, coating a first organic material layer in the annular width range of the edge of the inner surface of the carrier, and coating a second organic material layer on the whole inner surface of the carrier;
step S5: bonding the inner surface of the slide glass, the temporary bonding glue and the wafer together by a temporary bonding method to form a temporary wafer body;
step S6: thinning the silicon substrate on the back of the temporary wafer body to achieve the target thickness of the abrasive disc;
step S7: arranging a back gold layer on the back of the temporary wafer body through sputtering, electroplating or evaporation process;
step S8: forming transverse and longitudinal scribing lanes and identification points on the back gold layer;
step S9: separating the slide glass in a chemical bonding-debonding mode, and removing the temporary bonding glue on the front side of the wafer;
step S10: and cleaning the surface of the wafer with the slide glass removed to form the ultrathin wafer with the scribing channels and the identification points.
The examples are as follows:
the invention discloses a method for realizing a packaging structure of an ultrathin wafer, which comprises the following processing steps as shown in fig. 2 to 16:
the method comprises the following steps: referring to fig. 2, a passivation layer 120 and a passivation layer opening 123 thereof are disposed on the upper surface of the wafer 100 through a photolithography process, the passivation layer opening 123 corresponds to the chip electrode 110 of the wafer 100, and the chip electrode 110 of the wafer 100 is embedded in the silicon substrate 130. The material of the protective layer 120 is, for example, polyimide resin, which is not sensitive to the photolithography process, and negative photoresist is selected to form a desired polyimide film image.
Step two: referring to fig. 3, a metal bump 140 is disposed at the passivation opening 123 of the wafer 100 by an electroplating or chemical plating process, and the metal bump 140 is one or a combination of Cu, Sn, Ni, Pd, and Au, such as Cu/Sn, Ni/Au, or Ni/Pd/Au. Generally, a solder tin layer is plated or electrolessly plated to a predetermined thickness on top thereof.
Step three: referring to fig. 4, a layer of temporary bonding glue 200 is coated on the upper surface of the wafer 100, and the material of the temporary bonding glue 200 is a liquid thermoplastic polymer organic material, such as HT10.10 glue of HiTachi, japan, or other organic materials with the same function.
After the temporary bonding glue 200 is coated, baking at 180 ℃ is carried out, and the baking lasts for 3 minutes to enable the temporary bonding glue 200 to form a semisolid state with the thickness larger than the sum of the heights of the protective layer 120 and the metal bump 140, so that the protective layer 120 and the metal bump 140 which are arranged on the front side can be protected from being damaged and influenced in the processes of grinding and subsequent processes;
step four: referring to fig. 5, 6 and 7, a carrier sheet 500 is prepared, wherein the carrier sheet 500 is a glass sheet, a silicon sheet or other non-conductor sheet with sufficient rigidity; the slide 500 is pre-treated to increase the bonding force with the temporary bonding adhesive 200, thereby preventing the two from delaminating during the subsequent process.
Pretreatment of slide 500:
carrying out pretreatment such as cleaning and baking on the slide 500;
the first organic material layer 610 is coated within an annular width range of 2.5mm to 3mm of the edge of the inner surface of the carrier 500, as shown in fig. 6, the material of the first organic material layer 610 is a liquid thermosetting polymer material, and it may be other organic materials having the same function.
Then, a second organic material layer 620 is coated on the inner circular surface of the slide 500, as shown in fig. 7, the material of the second organic material layer 620 is a liquid thermosetting polymer material, which may also be an organic material having the same function. Since the first organic material layer 610 is pre-coated in the annular width of the edge of the carrier sheet 500, and the second organic material layer 620 and the first organic material layer 610 have non-wetting properties, for example, the first organic material layer 610 is made of EM glue from hitachi corporation of japan, and the second organic material layer 620 is made of 510 glue from hitachi corporation of japan, the second organic material layer 620 cannot be coated any more in the annular width.
Step five: referring to fig. 8, by a temporary bonding method, the bonding temperature is selected to be 100 ℃ to 200 ℃, and the inner surface of the slide 500, the temporary bonding adhesive 200 and the wafer 100 are bonded together under the bonding pressure of 3000N to 6000N to form a temporary wafer body 600, so that the strength and reliability are enhanced;
step six: referring to fig. 9, the si groups 130 on the back side of the temporary wafer body 600 are thinned by the lapping method to achieve a lapping target thickness of the si groups 130 of the wafer 100, specifically, a lapping target thickness of 4mil for a 12inch wafer and 3mil for an 8inch wafer. The thickness of the grinding sheet target is reduced, and lower packaging resistance can be obtained.
Step seven: referring to fig. 10, a back gold layer 700 is disposed on the back surface of the temporary wafer 600 by sputtering, electroplating or evaporation, and the material of the back gold layer may be one or a combination of several metals selected from Cu, Cr, Ti, Ni and Ag, such as a Cr/Cu combination or a Ti/Ni/Ag/Ni combination or a Cu/Ag combination.
Step eight: referring to fig. 11, 12 and 13, a photoresist pattern 710 and a photoresist pattern opening are formed on the back gold layer 700 through processes of glue coating, exposure and development in sequence, and then the redundant back gold layer 700 and the redundant photoresist in the photoresist pattern opening are removed in a corrosion manner to form a specific metal pattern 770, wherein the metal pattern is used for a subsequent fan-out process; fig. 12 is a bottom view of fig. 11, for example, in order to form dicing streets for four chips, the photoresist pattern openings i 713 of the photoresist pattern 710 are in a shape of a horizontal and a vertical strip which are vertically staggered and communicated, so as to pre-divide the back gold layer 700 into a plurality of chip monomers according to the size of the chip, a photoresist pattern opening ii 714 is arranged at one corner of each chip monomer, and the photoresist pattern opening ii 714 is in a circular shape; the back gold layer 700 in the photoresist pattern opening i 713 and the photoresist pattern opening ii 714 is removed by a corrosion process, and after the photoresist is removed, a transverse scribe lane 740 and a longitudinal scribe lane 740 and a circular identification point 760 are formed on the back gold layer 700, as shown in fig. 13, the size of the scribe lane 740 is determined according to the requirements of a client, and the identification point 760 is used in the subsequent processes.
Step nine: referring to fig. 14, the carrier film 500 is separated by chemical debonding, and the temporary bonding glue 200 on the front side of the wafer 100 is removed;
the bonding-debonding manner is as follows:
erecting the temporary wafer body 600, placing the temporary wafer body in a device for supporting bonded wafers, clamping the temporary wafer body 600 in front and back, suspending the temporary wafer body in a tank body for preventing soaking solution, and rotatably soaking the edge position of the temporary wafer body 600 in organic solution for about 1-2 hours as shown in fig. 14 until the organic solution and the first organic material layer 610 have a chemical reaction for releasing viscosity;
taking out the immersed temporary wafer 600 and placing the temporary wafer on a hot plate, wherein the temperature of the hot plate is 80-100 ℃, then adopting a tool with a certain specific suction force to suck the exposed surface of the slide 500, and then manually removing the slide 500, or adopting an automatic machine to separate the slide 500, as shown in fig. 15.
Step ten: the surface of the wafer 100 with the carrier 500 removed is dissolved with alcohol or IPA solution to form the solid temporary bonding adhesive 200, and then is cleaned with deionized water to form an ultra-thin wafer with the scribe streets 740 and the identification points 760, and in the subsequent process, the wafer 100 may be diced along the scribe streets 740 in a scribe manner to form single ultra-thin chips, as shown in fig. 16.
The above description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the embodiments of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. The invention relates to a method for realizing a packaging structure of an ultrathin wafer, which comprises the following process steps:
the method comprises the following steps: arranging a protective layer (120) and a protective layer opening (123) thereof on the upper surface of the wafer (100) through a photoetching process, wherein the protective layer opening (123) corresponds to the chip electrode (110) of the wafer (100), and the chip electrode (110) of the wafer (100) is embedded in the silicon substrate (130);
step two: arranging metal bumps (140) at the protective layer openings (123) of the wafer (100) by an electroplating or chemical plating process;
step three: forming semi-solid temporary bonding glue (200) on the upper surface of the wafer (100), wherein the thickness of the temporary bonding glue (200) is greater than the sum of the heights of the protective layer (120) and the metal bump (140);
step four: preparing a carrier sheet (500), pretreating the carrier sheet (500), coating a first organic material layer (610) in an annular width range of 2.5 mm-3 mm of the edge of the inner surface of the carrier sheet (500), and coating a second organic material layer (620) on the whole inner circle surface of the carrier sheet (500);
step five: bonding the inner surface of the slide (500), the temporary bonding glue (200) and the wafer (100) together by a temporary bonding method at a certain temperature and pressure to form a temporary wafer body (600);
step six: thinning the silicon base (130) on the back surface of the temporary wafer body (600) by a lapping method to achieve a lapping target thickness of the wafer (100);
step seven: arranging a back gold layer (700) on the back surface of the temporary wafer body (600) through sputtering, electroplating or evaporation process;
step eight: sequentially performing glue coating, exposure and development processes to form a photoresist pattern (710) and a photoresist pattern opening on the back gold layer (700), removing redundant back gold layer (700) and redundant photoresist in the photoresist pattern opening in a corrosion mode to form a specific metal pattern (770), wherein the photoresist pattern opening I (713) of the photoresist pattern (710) is in a transverse and longitudinal strip shape which is vertically staggered and communicated with each other, the back gold layer (700) is pre-divided into a plurality of chip monomers according to the size of a chip, and one corner of each chip monomer is provided with a photoresist pattern opening II (714); removing the back gold layer (700) in the photoresist pattern opening I (713) and the photoresist pattern opening II (714) through an etching process, and forming transverse and longitudinal scribing streets (740) and circular identification points (760) on the back gold layer (700) after the photoresist is removed;
step nine: separating the slide glass (500) in a chemical debonding mode, and removing the temporary bonding glue (200) on the front side of the wafer (100);
the bonding solution is as follows:
erecting a temporary wafer body (600), placing the temporary wafer body in a device for supporting bonded wafers, clamping the temporary wafer body (600) front and back to suspend in a groove body for preventing soaking solution, rotatably soaking the edge position of the temporary wafer body (600) in an organic solution for about 1-2 hours, and allowing the organic solution and a first organic material layer (610) to generate a chemical reaction for removing viscosity;
taking out the soaked temporary wafer (600) and placing the temporary wafer on a hot plate, wherein the temperature of the hot plate is 80-100 ℃, then adopting a tool with a certain specific suction force to suck the exposed surface of the slide glass (500), and then manually removing the slide glass (500) or adopting an automatic machine table to separate the slide glass (500);
step ten: the surface of the wafer (100) with the carrier (500) removed is cleaned to form an ultra-thin wafer level with scribe streets (740) and identification points (760).
2. The method according to claim 1, wherein in the second step, the material of the metal bump (140) is one or a combination of Cu, Sn, Ni, Pd, and Au.
3. The method according to claim 1 or 2, wherein in step two, a layer of tin for soldering is electroplated or electrolessly plated on top of the metal bump (140).
4. The method of claim 1, wherein in step three, the material of the temporary bonding glue (200) is a liquid thermoplastic polymer organic material.
5. The method of claim 1, wherein in step four, the material of the first organic material layer (610) is a liquid thermosetting polymer material.
6. The method of claim 1, wherein in the fourth step, the second organic material layer (620) is made of a liquid thermosetting polymer material and has a property of not wetting with the first organic material layer (610).
7. The realization method of claim 1, wherein in step six, the lapping target thickness of 12inch wafers is 4 mils, and the lapping target thickness of 8inch wafers is 3 mils.
8. The implementation method of claim 1, wherein in the seventh step, the material of the back gold layer is one or a combination of Cu, Cr, Ti, Ni, and Ag.
9. The method of claim 1, wherein in step eight, the photoresist pattern opening II (714) is circular.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210604005.XA CN114937615A (en) | 2022-05-31 | 2022-05-31 | Method for realizing packaging structure of ultrathin wafer level wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210604005.XA CN114937615A (en) | 2022-05-31 | 2022-05-31 | Method for realizing packaging structure of ultrathin wafer level wafer |
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| Publication Number | Publication Date |
|---|---|
| CN114937615A true CN114937615A (en) | 2022-08-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115863241A (en) * | 2023-01-17 | 2023-03-28 | 吾拾微电子(苏州)有限公司 | Wafer bonding method and bonding structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863241A (en) * | 2023-01-17 | 2023-03-28 | 吾拾微电子(苏州)有限公司 | Wafer bonding method and bonding structure |
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