CN209375635U - A kind of rf analog front-end system of Internet of Things information Perception SOC chip - Google Patents

Abstract

The utility model discloses a kind of rf analog front-end systems of Internet of Things information Perception SOC chip, including transmitting module, receiving module and LDO module, the transmitting module includes ASK modulation control module, power amplifier module and antenna-matching circuit, and the receiving module includes IQ clock generator, four phase clock sampling modules, VGA and bandpass filtering modules block, subcarrier demodulation module and the road IQ power determination module.The utility model effectively realizes the launching effect of carrier cancellation, variable signal bandwidths, the receiver of anti-monkey chatter and the inhibition of high neighboring trace, low band stray by transmitting module and receiving module, and the utility model can effectively reduce chip area, substantially reduce chip power-consumption.The utility model can be widely applied in SOC chip field.

Description

A kind of rf analog front-end system of Internet of Things information Perception SOC chip

Technical field

The utility model relates to IC technical field more particularly to a kind of radio frequency analogs of Internet of Things information Perception SOC chip Front end system.

Background technique

Using Intelligent terminal for Internet of things SOC chip as the technology of Internet of things of representative, it is widely used in the identification of people now, Perhaps it is used as the individual identification in logistical applications or as stored value card substitution cash, intelligent label therein is more carried on a shoulder pole In the presence of technology role of the substitution bar code as commodity sign from now on, and as in intelligent label and computer data information system The intelligent reader terminal of Jie, even more plays an extremely important role.With the deep development of Internet of Things interconnection technique and skill Art cost constantly declines, and world commerce will enter electronic tag commodity and identify the epoch, and in the manufacturing field of product, commodity The field of circulation will also introduce electronic label technology comprehensively, and market blowout phenomenon will occur to the demand of label card and card reader, To this, we must pay much attention to and accelerate industrial pattern.Exactly because electronic tag application demand pushes, so that electronic tag And corresponding Intelligent terminal for Internet of things SOC chip technology has been no longer limited in new high-tech industry, it directly expands industrial chain Open up advanced manufacturing industry and modern service industry.It may be said that Intelligent terminal for Internet of things SOC chip technology is not only related to how to keep And the industrial advantage of traditional manufacture is promoted, and push modern logistics industry, modern trade, the technology of modern commerce for great Innovation and industrial upgrading, modern exhibition industry, Modern Physical Education industry, modern cultural travel industry, present information consumption industry etc. are new The modern service industry of type is also its service object.Its automatic identification and automatic payment function will push traditional service industries to now The significant technology and key means marched for service trade.

Currently, Chinese Intelligent terminal for Internet of things SOC chip industry still faces huge challenge, essentially consist in industry still with Based on " centreless ", handling the core realms such as chip in high-end Intelligent terminal for Internet of things SOC chip can not industrialization.Grasp core Science and technology pushes IC design ability energetically, adds " core " consumption reduction also to become industry development for Intelligent terminal for Internet of things SOC chip Key.

The communication of RFID reader and label is carried out according to principal and subordinate's principle.Reader and label are established communication and are used Semiduplex mode, i.e. the two can only have a transmission, another reception.Reader is responsible for sending carrier signal starting label core Piece and firing order, label only respond the instruction that reader is issued, not active transmission instruction query reader.It is marked according to the world Quasi- ISO/IEC14443 regulation, the modulation depth that RFID reader transmission carrier frequency is 13.56MHz is 10% and 100% ASK signal, feeding digital state machine is handled after label chip receives and demodulates the signal, returns to MANCHESTER signal. Emit after the MANCHESTER signal load-modulated of return from label antenna；Reading and writing device antenna receives the signal and is demodulated After be sent into numerical portion, complete the reception of signal.

By above-mentioned analysis it is found that the AFE(analog front end) of reader must have the function of the following aspects: (1) generating high The transmission power of frequency, to start label chip and provide energy for it；(2) it is sent to after transmitting signal modulation by antenna It goes out；(3) it is properly received and demodulates the high-frequency signal from label.Very due to the coupling between reading and writing device antenna and label antenna Weak, the voltage fluctuation of the useful signal sensed on reading and writing device antenna is more much smaller than the output voltage of reader on the order of magnitude. In practice, for the system of 13.56MHz, when reading and writing device antenna voltage is about 100V (increasing voltage by resonance), It can only obtain the about useful signal of 10mV.This is one larger for the design of the demodulator circuit of Reader AFE(analog front end) Challenge.

Utility model content

In order to solve the above-mentioned technical problem, the purpose of the utility model is to provide a kind of Internet of Things information Perception SOC chips Rf analog front-end system.

Technical solution adopted in the utility model is:

A kind of rf analog front-end system of Internet of Things information Perception SOC chip, including transmitting module, receiving module and LDO module, the transmitting module include ASK modulation control module, power amplifier module and antenna-matching circuit, the reception mould Block includes that IQ clock generator, four phase clock sampling modules, VGA and bandpass filtering modules block, subcarrier demodulation module and the road IQ are strong Weak determination module, the output end of the ASK modulation control module are defeated by power amplifier module and antenna-matching circuit Enter end connection, the first output end of the IQ clock generator is connect with the input terminal of ASK modulation control module, the IQ clock The second output terminal of generator passes sequentially through four phase clock sampling modules, VGA and bandpass filtering modules block and subcarrier demodulation module And then it is connect with the input terminal of the road IQ power determination module, the electricity of the output end of the LDO module and four phase clock sampling modules The connection of source input terminal.

The LDO module includes start-up circuit, band-gap reference circuit, double electricity as a further improvement of the utility model, Press domain reference current source conversion circuit, bias-voltage generating circuit and error to amplify operational amplifier, the start-up circuit it is defeated Outlet is put by band-gap reference circuit, dual voltage domains reference current source conversion circuit and bias-voltage generating circuit and error The input terminal of macrooperation amplifier connects.

The start-up circuit includes the first PMOS tube, the first NMOS tube and the as a further improvement of the utility model, The source electrode of two NMOS tubes, first PMOS tube is connect with power end, the grid of first PMOS tube and the second NMOS tube Grid connection, the drain electrode of first PMOS tube are connected with the drain electrode of the grid of the first NMOS tube and the second NMOS tube respectively, The source electrode of first NMOS tube and the source electrode of the second NMOS tube are connected to ground, the drain electrode and second of first NMOS tube The grid of NMOS tube is connected with band-gap reference circuit.

As a further improvement of the utility model, the band-gap reference circuit include the second PMOS tube, third PMOS tube, 4th PMOS tube, first resistor, second resistance, 3rd resistor, the 4th resistance, the first triode, the second triode, first capacitor With the first operational amplifier, the source electrode of the source electrode of second PMOS tube, the source electrode of third PMOS tube and the 4th PMOS tube with The drain electrode of power end connection, second NMOS tube is defeated with the reverse phase of the drain electrode of the second PMOS tube, the first operational amplifier respectively Entering end to be connected with the emitter of the first triode, the drain electrode of second NMOS tube is connected to ground by first resistor, First NMOS tube drain electrode respectively with the grid of the second PMOS tube, the grid of third PMOS tube, the 4th PMOS tube grid It is connected with the output end of the first operational amplifier, the leakage of the non-inverting input terminal and third PMOS tube of first operational amplifier Pole connection, the drain electrode of the third PMOS tube are connect by second resistance with the emitter of the second triode, the third The drain electrode of PMOS tube is connected to ground by 3rd resistor, and the grid of the 4th PMOS tube passes through first capacitor and ground Connection, the drain electrode of the 4th PMOS tube are connected to ground by the 4th resistance, the drain electrode of the 4th PMOS tube and double electricity Press the input terminal connection of domain reference current source conversion circuit, the base stage of first triode, the collector of the first triode, the The collector of the base stage of two triodes and the second triode is connected to ground.

The four phase clocks sampling module includes that carrier circuit and gain is gone to put as a further improvement of the utility model, Big device, the second output terminal of the IQ clock generator pass sequentially through carrier circuit and gain amplifier so that with VGA and band Pass filtering module is connected.

It is described as a further improvement of the utility model, that carrier circuit is gone to include the 5th resistance, first diode, second Diode, the second capacitor, third capacitor, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 3rd NMOS Pipe, the 4th NMOS tube, the 5th NMSO pipe and the first phase inverter, the anode of the positive terminal of the first diode and the second diode End is connect with receiving end, source electrode of the positive terminal of the first diode by the 5th resistance and the 5th PMOS tube, institute The source electrode for stating the 5th PMOS tube is connect by third capacitor with power end, and the grid of the 5th PMOS tube is respectively with the 6th The grid of the grid of PMOS tube, the output end of the first phase inverter and the 5th NMOS tube is connected, the drain electrode of the 5th PMOS tube It is connected respectively with the source electrode of the drain electrode of the 7th PMOS tube and third NMOS tube, the drain electrode of the 6th PMOS tube is respectively with the 7th The source electrode of PMOS tube and the source electrode of the 4th NMOS tube are connected, the input terminal of first phase inverter respectively with the 7th PMOS tube The grid of grid, the grid of third NMOS tube and the 4th NMOS tube is connected, the drain electrode of the third NMOS tube and the 5th NMOS The drain electrode of pipe connects, and the drain electrode of the 4th NMOS tube connects with the drain electrode of the source electrode of the 5th NMOS tube and the 8th PMOS tube respectively It connects, the drain electrode of the 8th PMOS tube is connect by the second capacitor with power end, the grid and IQ of the 8th PMOS tube The second output terminal of clock generator is connected, and the source electrode of the 8th PMOS tube is connected to ground, the leakage of the 8th PMOS tube The connection of the input terminal of pole and gain amplifier.

The subcarrier demodulation module includes first comparator, the second reverse phase as a further improvement of the utility model, Device, third phase inverter, the 4th phase inverter, the 6th resistance, the 4th capacitor, the first NAND gate and the second NAND gate, first ratio Input terminal compared with device is connect with the output end of VGA and bandpass filtering modules block, and the output end of the first comparator is anti-by second Phase device is connect with the first input end of the first NAND gate in turn, the input of the output end and third phase inverter of first NAND gate End connection, the output end of first NAND gate connect with the first input end of the second NAND gate, the third phase inverter it is defeated Outlet is connect by the 6th resistance with the second input terminal of the second NAND gate, the output end of second NAND gate respectively with The input terminal connection of the second input terminal and the 4th phase inverter of first NAND gate, the second input terminal of second NAND gate pass through 4th capacitor is connected to ground in turn.

The beneficial effects of the utility model are:

A kind of rf analog front-end system of Internet of Things information Perception SOC chip of the utility model is by transmitting module and connects Receipts module effectively realizes carrier cancellation, variable signal bandwidths, the receiver of anti-monkey chatter and high neighboring trace and inhibits, is miscellaneous outside low strap Scattered launching effect, and the utility model can effectively reduce chip area, substantially reduce chip power-consumption.

Detailed description of the invention

Fig. 1 is a kind of principle box of the rf analog front-end system of Internet of Things information Perception SOC chip of the utility model Figure；

Fig. 2 is the circuit diagram of transmitting module in the utility model embodiment；

Fig. 3 is the circuit diagram of start-up circuit and band-gap reference circuit in the utility model；

Fig. 4 is the circuit diagram of Q clock generation circuit in the utility model embodiment；

Fig. 5 is the circuit diagram that carrier circuit is removed in the utility model embodiment；

Fig. 6 is the circuit diagram of four phase orthogonal clock generating circuits in the utility model embodiment；

Fig. 7 is the circuit diagram of the road IQ power decision circuit in the utility model embodiment；

Fig. 8 is the circuit diagram of subcarrier demodulation module in the utility model embodiment.

Specific embodiment

Specific embodiment of the present utility model is described further with reference to the accompanying drawing:

With reference to Fig. 1, a kind of rf analog front-end system of Internet of Things information Perception SOC chip of the utility model, including hair Module, receiving module and LDO module are penetrated, the transmitting module includes ASK modulation control module, power amplifier module and antenna With circuit, the receiving module includes IQ clock generator, four phase clock sampling modules, VGA and bandpass filtering modules block, subcarrier Demodulation module and the road IQ power determination module, the output end of the ASK modulation control module by power amplifier module with The input terminal of antenna-matching circuit connects, the first output end of the IQ clock generator and the input of ASK modulation control module End connection, the second output terminal of the IQ clock generator pass sequentially through four phase clock sampling modules, VGA and bandpass filtering modules block It is connect with subcarrier demodulation module and then with the input terminal of the road IQ power determination module, output end and four phases of the LDO module The power input of clock sampling module connects.

The utility model embodiment is mainly made of transmitting module and the big module of receiving module two, and transmitting module mainly wraps Include ASK modulation module, power amplifier module and Matching and modification circuit；When receiving module mainly includes IQ clock generator, four phases Clock sampling module, VGA and bandpass filtering modules block, subcarrier demodulation module and the road IQ power determination module.The IQ clock generates Device is made of oscillator and Q clock generator, and the oscillator is realized using 13.56MHZ oscillator, when being mainly used for generating I Clock signal.By SOC chip in this present embodiment using SMIC0.18um technique, and chip exterior voltage is powered by 5V, is Guarantee the transmission power of transmitting terminal, transmitting terminal is still powered by 5V；It is used to reduce overall power and chip area receiving module 1.8V power supply；So being also added into LDO module in this SOC chip, which provides supply voltage AVDD for entire receiving module, Various required reference voltages are provided simultaneously for receiving module.

Signal is received by the way that after envelope detected, only the filtering Jing Guo rear class and amplifying circuit are to recover original base band letter Number, therefore the demodulation of signal depends on envelope detector and filter, this proposes higher requirement to filter, and It is required that received signal signal-to-noise ratio with higher, can not achieve the demodulation compared with small-signal, to largely limit The distance of radio frequency identification.This chip solves the problems, such as this using the mode of quadrature demodulation, and Q clock required for demodulating is by this Clock shake by 90 ° of phase shift generations.In order to not influence the signal-to-noise ratio for receiving signal, to oscillator phase stability and sideband noise It is more demanding, clock jitter is the smaller the better.Here the local clock of 13.56MHz is generated using external crystal oscillator.

Q clock generator is mainly made of delay controller and delay array.Wherein, delay array is for when adjusting Q Delay of the clock ClkQ relative to I clock ClkI makes Q clock and 90 degree of I clock skew；Delay controller is for controlling delay In array whether the access of delay unit.

Chip electrification reset cause reset signal change or numerical portion control the port Calib generate an arteries and veins Q clock generation circuit will be triggered by rushing signal.There is a counter and decoder in delay controller, Q clock generation circuit opens Every to pass through an I clock after dynamic, the numerical value of counter is sent to decoder, generates new delay array control signal, make Q clock Phase certain change occurs.In this way after several delay units, delay controller detects Q clock and I clock phase When potential difference reaches 180 degree, controller just takes the half of counter values as the delay of final delay array, and controls delay battle array Column generate Q clock.Delay [4:0] signal is used to preset delay numerical value, postpones to share 30 groups of delay unit in array, It ensure that the precision of Q clock Yu 90 degree of phase differences of I clock.

The delay unit mainly selects 1 multi-channel data selector and phase inverter to form by 2.Delay unit generates one instead The delay of phase device, the delay are determined by the P pipe and N pipe breadth length ratio of phase inverter.The level of control signal determines the delay unit Input is the output of I clock or upper level delay unit.When number by changing concatenated delay unit changes total Q The delay of clock.

With reference to Fig. 2, in the present embodiment, MPReader, MNReader are CMOS power tube in parallel in transmitting module, by more A PMOS tube and NMOS tube composition, the number of CMOS tube in parallel are mainly determined by the signal modulation depth of transmitting module.By frequency It is connected to the grid of MPReader, MNReader for the signal of 13.56MHz, exports tx signal after subsequent conditioning circuit is handled To generate carrier wave, frequency is also 13.56MHz.Since signal still includes various harmonic waves, it is therefore desirable to by Lemc and Cemc The filter of composition further removes harmonic wave；Connect matching network capacitor Csreader and matching network capacitor Cpreader in parallel Collectively constitute impedance matching network.Radio-frequency interface circuit is mainly used to match antenna and impedance, and generates resonance and by energy Label antenna is passed to by Mutual Inductance Coupling, while can also adjust antenna quality factor and transmission signal bandwidth.

Wherein, the method for chip interior change transmission power size is as follows: 1, changing the size of supply voltage, this chip branch The operating voltage of 3.3V-5V is held, operating voltage is bigger, and in the case that other configurations are the same, transmission power is bigger；It 2, is to pass through tune The size of whole MPReader adjusts transmitting impedance, the size variation of Lai Shixian transmission power, while this is also to adjust ASK tune The method of depth processed.

It is further used as preferred embodiment, the LDO module includes start-up circuit, band-gap reference circuit, twin voltage Domain reference current source conversion circuit, bias-voltage generating circuit and error amplify operational amplifier, the output of the start-up circuit Amplified by band-gap reference circuit, dual voltage domains reference current source conversion circuit and bias-voltage generating circuit and error at end The input terminal of operational amplifier connects.

With reference to Fig. 3, it is further used as preferred embodiment, the start-up circuit includes the first PMOS tube P1, first NMOS tube N1 and the second NMOS tube N2, the source electrode of the first PMOS tube P1 are connect with power end, the first PMOS tube P1's Grid is connect with the grid of the second NMOS tube N2, the first PMOS tube P1 drain electrode respectively with the grid of the first NMOS tube N1 and The drain electrode of second NMOS tube N2 is connected, and the source electrode of the first NMOS tube N1 and the source electrode of the second NMOS tube N2 connect with ground It connects, the drain electrode of the first NMOS tube N1 and the grid of the second NMOS tube N2 are connected with band-gap reference circuit.

It is further used as preferred embodiment, the band-gap reference circuit includes the second PMOS tube P2, third PMOS tube P3, the 4th PMOS tube P4, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the first triode Q1, second The source of the source electrode of triode Q2, first capacitor C1 and the first operational amplifier U1, the second PMOS tube P2, third PMOS tube P3 The source electrode of pole and the 4th PMOS tube P4 are connect with power end, the drain electrode of the second NMOS tube N2 respectively with the second PMOS tube P2 Drain electrode, the first operational amplifier U1 inverting input terminal be connected with the emitter of the first triode Q1, the 2nd NMOS The drain electrode of pipe N2 is connected to ground by first resistor R1, the drain electrode of the first NMOS tube N1 respectively with the second PMOS tube P2 Grid, the grid of third PMOS tube P3, the grid of the 4th PMOS tube P4 and the first operational amplifier U1 output end be connected, The non-inverting input terminal of the first operational amplifier U1 is connect with the drain electrode of third PMOS tube P3, the leakage of the third PMOS tube P3 Pole is connect by second resistance R2 with the emitter of the second triode Q2, and the drain electrode of the third PMOS tube P3 passes through third Resistance R3 is connected to ground in turn, and the grid of the 4th PMOS tube P4 is connected to ground by first capacitor C1, and the described 4th The drain electrode of PMOS tube P4 is connected to ground by the 4th resistance R4, the drain electrode of the 4th PMOS tube P4 and dual voltage domains benchmark The input terminal of current source conversion circuit connects, the base stage of the first triode Q1, the collector of the first triode Q1, the two or three The collector of the base stage of pole pipe Q2 and the second triode Q2 are connected to ground.

Wherein, the first PMOS tube P1, the first NMOS tube N1 and the second NMOS tube N2 constitute start-up circuit, access electricity After the VHD of source, with the raising of VHD, the gate source voltage VGS of the first PMOS tube P1 is gradually increased, when the voltage reaches the first PMOS When the cut-in voltage VTH of pipe P1, the first PMOS tube P1 conducting, the grid voltage of the first NMOS tube N1 follows VDD to rise, when first The gate source voltage of NMOS tube N1 reaches cut-in voltage, the first NMOS tube N1 open by the second PMOS tube P2 of cascode structure, The grid voltage of third PMOS tube P3 and the 4th PMOS tube P4 conducting starting, the first PMOS tube P1 and the second NMOS tube N2 rise, The grid voltage of first NMOS tube N1 is drawn to 0 rapidly, closes the first NMOS tube N1, start completion by the second NMOS tube N2 conducting. First PMOS tube P1 and the second NMOS tube N2 belong to down than pipe, and internal resistance is very big, reduces the quiescent dissipation of start-up circuit.One or three pole Pipe Q1 and the electric current that the second triode Q2 and second resistance R2 constitutes a PTAT reference voltage and absolute temperature is proportional Generator.The electricity of a CTAT reference voltage and absolute temperature complementarity is generated by addition first resistor R1 and 3rd resistor R3 Stream, CTAT current and PTAT current are summed.With the rising of temperature, triode pressure drop is reduced, so that flowing through 3rd resistor The electric current of R3 reduces (meeting CTAT).

It is further used as preferred embodiment, the four phase clocks sampling module includes that carrier circuit and gain is gone to amplify Device, the second output terminal of the IQ clock generator pass sequentially through carrier circuit and gain amplifier so that with VGA and band logical Filter module is connected.

It is further used as preferred embodiment, described to remove carrier circuit include the 5th resistance R5, first diode D1, the Two diode D2, the second capacitor C2, third capacitor C3, the 5th PMOS tube P5, the 6th PMOS tube P6, the 7th PMOS tube P7, the 8th PMOS tube P8, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and the first phase inverter I1, the first diode The positive terminal of the positive terminal of D1 and the second diode D2 are connect with receiving end, and the positive terminal of the first diode D1 passes through the The source electrode with the 5th PMOS tube P5, the source electrode of the 5th PMOS tube P5 pass through third capacitor C3 and electricity to five resistance R5 in turn Source connection, the grid of the 5th PMOS tube P5 output end with the grid of the 6th PMOS tube P6, the first phase inverter I1 respectively Be connected with the grid of the 5th NMOS tube N5, the drain electrode of the 5th PMOS tube P5 respectively with the drain electrode of the 7th PMOS tube P7 and the The source electrode of three NMOS tube N3 is connected, the source electrode and the 4th with the 7th PMOS tube P7 respectively that drains of the 6th PMOS tube P6 The source electrode of NMOS tube N4 is connected, the input terminal of the first phase inverter I1 respectively with the grid of the 7th PMOS tube P7, third The grid of the grid of NMOS tube N3 and the 4th NMOS tube N4 are connected, the drain electrode of the third NMOS tube N3 and the 5th NMOS tube N5 Drain electrode connection, the drain electrode drain electrode with the source electrode and the 8th PMOS tube P8 of the 5th NMOS tube N5 respectively of the 4th NMOS tube N4 Connection, the drain electrode of the 8th PMOS tube P8 are connect by the second capacitor C2 with power end, the 8th PMOS tube P8's Grid is connected with the second output terminal of IQ clock generator, and the source electrode of the 8th PMOS tube P8 is connected to ground, and the described 8th The drain electrode of PMOS tube P8 and the input terminal of gain amplifier connect.

It goes carrier circuit series connection to realize using two in the present embodiment to handle CLK1 and CLK2 signal, it is described to unload Wave circuit is demodulated according to sampling thheorem using switching capacity sample circuit.The process of sampling is equivalent to baseband signal frequency Repeat replication is composed in entire frequency range, the signal after sampling can be restored into base-band data signal by low-pass filter. Sampled clock signal samples aerial signal RX, and the clock frequency of sampling should be higher than that twice of frequency data signal could nothing Restore data-signal in distortion ground.Wherein Vmid is the intermediate dc level of VDD and GND, and the output signal of all demodulation will all fold It is added in the DC level, is equivalent to AC deposition；RX is the reception signal of antenna, and C0 is samples storage capacitor, the second capacitor C2 To shift capacitor；The 5th PMOS tube P5, the 6th PMOS tube P6, the 7th PMOS tube P7, the 8th PMOS tube P8, third NMOS tube N3 and the 4th NMOS tube N4 composition increases the complementary high-frequency transmission door of virtual device, and CLK1 and CLK2 are transmission gate control terminal.It adopts The principle of sample demodulation are as follows: when CLK1 is high level (duration was 1/4 period), on first transmission gate conducting sampling RX Signal simultaneously stores it on capacitor, after 36.9ns (i.e. half period) CLK2 be high level, and CLK1 be already reduced to it is low Level, therefore first transmission gate cut-off, second transmission gate conducting complete signal in the electric charge transfer to C1 on C0 Demodulation.Since the sequence of sampling clock is followed successively by CLK1, CLK3, CLK2 and CLK4, I_channel and Q_ in a cycle Channel is alternately accomplished the sampling and transfer of respective signal, is finally completed carrier wave demodulation.The result of demodulation is with baseband signal Subcarrier signal.

The sampling clock CLK1 and CLK2 of control switch want mutually orthogonal, since this demodulator circuit is using orthogonal solution It adjusts, so the sampled clock signal for needing four roads mutually orthogonal in total.Using circuit shown in figure to generate in the present embodiment Four phase quadrature clock signals.

Since sampling goes the obtained subcarrier signal amplitude of carrier wave demodulator circuit smaller, need by amplification so as to it It is further processed.Here variable gain amplifier (VGA) Lai Shixian is used, the control of gain is by adjusting resistance Ratio is realized.Vmid is AC deposition in figure, and Amp_out is the output end of amplifier, expression formula are as follows:

The ratio of resistance is adjusted by being inserted into a transmission gate in the proportional amplifier of standard.The control terminal of transmission gate It is connected with digital register, to adjust the decision threshold of rear stage comparison module, reaches best reception.Due to amplifier Output and input need by resistance realize feed back, here use common source and common grid amplifier.

With reference to Fig. 7, in the present embodiment, the road IQ power decision circuit can allow circuit without road in the case where any phase difference Can select it is most strong that signal is useful signal all the way, greatly improve reader performance and stability.In the present embodiment before this Shaping is carried out to carrier wave and obtains square wave Vck, CLKI, CLKQ are negated respectively to obtain CLKI_ and CLKQ_；By CLKI, CLKQ, CLKI_, CLKQ_ respectively with Vck phase with, obtain DI, DQ, NI, NQ waveform signal；Pulsewidth width D I, DQ, NI, NQ are converted into Corresponding 4 voltage values；Pulsewidth width is exactly to represent to receive both clocks that the signal to come and crystal oscillator generate by antenna Between existing phase difference.This is that phase difference is randomness, with card close to the time point of reader and the characteristic of antenna Etc. there is very big relationship.It, which can use pulsewidth and controls respectively, obtains 4 voltage values to the charge and discharge of same value capacitor, i.e. DI, DQ, NI, NQ, which are converted, corresponding voltage value, is finally respectively compared two voltage values of I, Q two-way, selects the larger value, so Two the larger value are compared again afterwards and select maximum value, therefore, it is determined which road signal of I, Q two-way is stronger out.

With reference to Fig. 8, it is further used as preferred embodiment, the subcarrier demodulation module includes first comparator COM1, the second phase inverter I2, third phase inverter I3, the 4th phase inverter I4, the 6th resistance R6, the 4th capacitor C4, the first NAND gate The output end of the input terminal of NAND1 and the second NAND gate NAND2, the first comparator COM1 and VGA and bandpass filtering modules block Connection, the output end of the first comparator COM1 are first defeated by the second phase inverter I2 and the first NAND gate NAND1's Enter end connection, the output end of the first NAND gate NAND1 is connect with the input terminal of third phase inverter I3, first NAND gate The output end of NAND1 is connect with the first input end of the second NAND gate NAND2, and the output end of the third phase inverter I3 passes through the Six resistance R6 are connect with the second input terminal of the second NAND gate in turn, and the output end of the second NAND gate NAND2 is respectively with The input terminal connection of the second input terminal and the 4th phase inverter I4 of one NAND gate NAND1, the second of the second NAND gate NAND2 Input terminal is connected to ground by the 4th capacitor C4.

The rate of low speed 106K and high speed 848K are compatible in the present embodiment, the rate of all supported protocols is all negative Encoding and decoding are carried out under the premise of carrier wave, therefore, the utility model chip realizes compatibility in the form of demodulating subcarrier.This mould Block is to be demodulated the amplified signal of VGA.It by the amplified output of the VGA on the road the I road Q and is referred to using four road comparators Level VH, VL are respectively compared, and the output of formation uses pulsewidth shaping circuit to adjust output pulse width to 7 clock cycle, arteries and veins again Wide degree is determined by RC retardation ratio unit.By the output of comparator by negate after RC retardation ratio cell delay again with original signal phase With, form a fixed pulsewidth, may be implemented no matter the wide or narrow situation of pulsewidth of comparator output can be into The effective shaping of row, so as to substantially reduce influence of noise, reduce false triggering, digital circuit is facilitated to be decoded signal, It can be compatible with each different emission rates simultaneously.The road Zai You IQ power selecting module selects strongest signal output.

From the foregoing it can be that the utility model carrier cancellation is effectively realized by transmitting module and receiving module, can The launching effect of varying signal bandwidth, the receiver of anti-monkey chatter and the inhibition of high neighboring trace, low band stray, and the utility model Chip area can be effectively reduced, chip power-consumption is substantially reduced.

It is to be illustrated to the preferable implementation of the utility model, but the utility model creation is not limited to institute above State embodiment, those skilled in the art can also make various etc. without departing from the spirit of the present invention With deformation or replacement, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.

Claims (7)

1. a kind of rf analog front-end system of Internet of Things information Perception SOC chip, it is characterised in that: including transmitting module, connect It receives module and LDO module, the transmitting module includes ASK modulation control module, power amplifier module and antenna-matching circuit, institute Stating receiving module includes IQ clock generator, four phase clock sampling modules, VGA and bandpass filtering modules block, subcarrier demodulation module Pass through power amplifier module and antenna match with the output end of the road IQ power determination module, the ASK modulation control module The input terminal of circuit connects, and the first output end of the IQ clock generator is connect with the input terminal of ASK modulation control module, institute The second output terminal for stating IQ clock generator passes sequentially through four phase clock sampling modules, VGA and bandpass filtering modules block and subcarrier Demodulation module is connect with the input terminal of the road IQ power determination module in turn, and the output end of the LDO module and four phase clocks sample The power input of module connects.

2. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 1, feature exist In: the LDO module includes start-up circuit, band-gap reference circuit, dual voltage domains reference current source conversion circuit, bias voltage production Raw circuit and error amplify operational amplifier, and the output end of the start-up circuit passes through band-gap reference circuit, dual voltage domains benchmark Current source conversion circuit and bias-voltage generating circuit are connect with the input terminal of error amplification operational amplifier in turn.

3. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 2, feature exist In: the start-up circuit includes the first PMOS tube, the first NMOS tube and the second NMOS tube, the source electrode and electricity of first PMOS tube Source connection, the grid of first PMOS tube are connect with the grid of the second NMOS tube, the drain electrode difference of first PMOS tube It is connected with the drain electrode of the grid of the first NMOS tube and the second NMOS tube, the source electrode of first NMOS tube and the second NMOS tube Source electrode is connected to ground, and the drain electrode of first NMOS tube and the grid of the second NMOS tube are connected with band-gap reference circuit.

4. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 3, feature exist In: the band-gap reference circuit include the second PMOS tube, third PMOS tube, the 4th PMOS tube, first resistor, second resistance, the Three resistance, the 4th resistance, the first triode, the second triode, first capacitor and the first operational amplifier, second PMOS tube Source electrode, the source electrode of third PMOS tube and the source electrode of the 4th PMOS tube connect with power end, the drain electrode of second NMOS tube It is connected respectively with the emitter of the drain electrode of the second PMOS tube, the inverting input terminal of the first operational amplifier and the first triode, The drain electrode of second NMOS tube is connected to ground by first resistor, and the drain electrode of first NMOS tube is respectively with second The grid of PMOS tube, the grid of third PMOS tube, the grid of the 4th PMOS tube and the output end of the first operational amplifier are connected, The non-inverting input terminal of first operational amplifier is connect with the drain electrode of third PMOS tube, and the drain electrode of the third PMOS tube passes through Second resistance is connect with the emitter of the second triode in turn, and the drain electrode of the third PMOS tube passes through 3rd resistor and ground Connection, the grid of the 4th PMOS tube is connected to ground by first capacitor, and the drain electrode of the 4th PMOS tube passes through the Four resistance are connected to ground in turn, and the drain electrode of the 4th PMOS tube and the input terminal of dual voltage domains reference current source conversion circuit connect It connects, the base stage of first triode, the collector of the first triode, the base stage of the second triode and the current collection of the second triode Extremely it is connected to ground.

5. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 1, feature exist In: the four phase clocks sampling module includes removing carrier circuit and gain amplifier, the second output of the IQ clock generator End passes sequentially through carrier circuit and gain amplifier and then is connected with VGA with bandpass filtering modules block.

6. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 5, feature exist In: it is described that carrier circuit is gone to include the 5th resistance, first diode, the second diode, the second capacitor, third capacitor, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMSO pipe and the The positive terminal of one phase inverter, the positive terminal of the first diode and the second diode is connect with receiving end, and the described 1st For the positive terminal of pole pipe by the source electrode of the 5th resistance and the 5th PMOS tube, it is electric that the source electrode of the 5th PMOS tube passes through third Hold so connect with power end, the grid of the 5th PMOS tube respectively with the grid of the 6th PMOS tube, the first phase inverter it is defeated Outlet is connected with the grid of the 5th NMOS tube, the drain electrode drain electrode and third with the 7th PMOS tube respectively of the 5th PMOS tube The source electrode of NMOS tube is connected, the source with the source electrode of the 7th PMOS tube and the 4th NMOS tube respectively that drains of the 6th PMOS tube Pole is connected, the input terminal of first phase inverter grid and the 4th with the grid of the 7th PMOS tube, third NMOS tube respectively The grid of NMOS tube is connected, and the drain electrode of the third NMOS tube is connect with the drain electrode of the 5th NMOS tube, the 4th NMOS tube Drain electrode connect respectively with the drain electrode of the source electrode and the 8th PMOS tube of the 5th NMOS tube, the drain electrode of the 8th PMOS tube passes through the Two capacitors are connect with power end in turn, and the grid of the 8th PMOS tube is connected with the second output terminal of IQ clock generator, The source electrode of 8th PMOS tube is connected to ground, and the drain electrode of the 8th PMOS tube and the input terminal of gain amplifier connect.

7. a kind of rf analog front-end system of Internet of Things information Perception SOC chip according to claim 1, feature exist In: the subcarrier demodulation module includes first comparator, the second phase inverter, third phase inverter, the 4th phase inverter, the 6th electricity Resistance, the 4th capacitor, the first NAND gate and the second NAND gate, the input terminal and VGA and bandpass filtering modules block of the first comparator Output end connection, the first input end that the output end of the first comparator passes through the second phase inverter and the first NAND gate Connection, the output end of first NAND gate connect with the input terminal of third phase inverter, the output end of first NAND gate and The first input end of second NAND gate connects, and the output end of the third phase inverter passes through the 6th resistance and the second NAND gate The second input terminal connection, the output end of second NAND gate respectively with the second input terminal of the first NAND gate and the 4th reverse phase The input terminal of device connects, and the second input terminal of second NAND gate is connected to ground by the 4th capacitor.