CN209375582U

CN209375582U - A kind of novel switched capacitor trims digital controlled oscillator

Info

Publication number: CN209375582U
Application number: CN201920267434.6U
Authority: CN
Inventors: 李富华; 吴庆; 李昶; 徐大为
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2019-03-04
Filing date: 2019-03-04
Publication date: 2019-09-10
Anticipated expiration: 2029-03-04

Abstract

In order to improve the control precision of the current digital oscillator based on inductance capacitance resonant cavity oscillator, and the parasitic capacitance C of the common NMOS transistor used_dInfluence to degree of regulation.The utility model proposes a kind of novel switched capacitors to trim digital controlled oscillator, it includes RC pierce circuit, digital control end, coarse adjustment capacitor array, wherein digital control end is connect with coarse adjustment capacitor array, control the on-off of the NMOS transistor containing MIM capacitor in coarse adjustment capacitor array in each parallel branch, to be adjusted to realize to the frequency of RC pierce circuit come the capacitor for changing entire RC pierce circuit.

Description

A kind of novel switched capacitor trims digital controlled oscillator

Technical field

The utility model relates to arrive the LC oscillator with frequency regulation function, more specifically, being related to a kind of novel Switching capacity trims digital controlled oscillator.

Background technique

As Digital Signal Processing is more and more widely used, digital phase-locked loop is also more next in modern integrated circuits design It is more universal, and part most crucial in digital servo-control ring design is the design of digital oscillator.Digital oscillator can mainly divide Be three kinds: the first digital oscillator is the combined digital oscillator of analog-to-digital conversion and voltage controlled oscillator, second of number vibration Swinging device is the digital oscillator based on ring oscillator, the third digital oscillator is based on inductance capacitance resonant cavity oscillator Digital oscillator.It is main to use the digital oscillation based on inductance capacitance resonant cavity oscillator for the application field of 4~5GHz Device.

As shown in Figure 1, be the current relatively stable digital oscillator based on inductance capacitance resonant cavity oscillator of performance, It includes RC pierce circuit, coarse tuning circuit and fine tuning circuit, wherein RC pierce circuit includes power supply VCC, first capacitor C1, the second capacitor C2, the first inductance L1, the second inductance L2, power supply VCC use direct current, the first NMOS transistor M1, second NMOS transistor M2, wherein the first inductance L1 and first capacitor C1 is in parallel, and one end of the first inductance L1 and first capacitor C1 with Power supply VCC is connected, and other end is connected with the grid G end of the second NMOS transistor M2；Second inductance L2 and the second capacitor C2 are simultaneously Connection, and one end of the second inductance L2 and the second capacitor C2 are connected with power supply VCC, the grid of other end and the first NMOS transistor M1 The pole end G is connected, and the drain D end of the first NMOS transistor M1 is connected with the other end of the first inductance L1 and first capacitor C1, the The source S end of one NMOS transistor M1 is grounded；The drain D end of second NMOS transistor M2 and the second inductance L2 and the second capacitor C2 Other end be connected, the source S end of the second NMOS transistor M2 ground connection.The working principle of this RC pierce circuit is by the One inductance L1 and first capacitor C1 generates the higher-order of oscillation, while generating high frequency using symmetrical second inductance L2 and the second capacitor C2 Oscillation promotes the stability of RC pierce circuit, reduces noise；Due in the first inductance L1 and the second inductance L2 there are resistance, So the part energy exchanged between capacitor and inductance is lost in the form of heat in electrical resistance in each cycle of oscillation , this amplitude for just directly resulting in the higher-order of oscillation of generation can periodically decay, until last no longer generate oscillation, to understand Certainly this problem introduces the first NMOS transistor and the second NMOS transistor, and according to above-mentioned connection structure that the first NMOS is brilliant Body pipe and the second NMOS transistor are added to containing power supply VCC, the first inductance L1, first capacitor C1, the second inductance L2, the second electricity In the basic RC pierce circuit for holding C2, one is generated in the circuit of the first NMOS transistor and the second NMOS transistor at this time and is born Resistance, the negative resistance are just offset with resistance present in basic RC pierce circuit, ensure that RC pierce circuit in this way Periodic dyingout.

Coarse tuning circuit includes digital control end and a route or the array structure containing multiple parallel lines, and described one A route or array structure containing multiple parallel lines are the line construction containing NMOS transistor and capacitor, are drawn in Fig. 1 Array out containing 6 routes, it is practical to put one or more according to demand during circuit design, it is not necessarily 6.Herein, it states for convenience, circuit connection structure and rendering circuit work is described according to the array containing 6 routes Make principle.In coarse tuning circuit comprising digital control end, first route, Article 2 route, Article 3 route, Article 4 route, Article 5 route and Article 6 route include third capacitor C3, third NMOS transistor M3, Article 2 route in first route In include the 4th capacitor C4, the 4th NMOS transistor M4, include the 5th capacitor C5, the 5th NMOS transistor in Article 3 route M5, includes the 6th capacitor C6, the 6th NMOS transistor M6 in Article 4 route, and the 7th capacitor C7, the are included in Article 5 route Seven NMOS transistor M7 include the 8th capacitor C8, the 8th NMOS transistor M8 in Article 6 route；Wherein, first route Connection type is that one end of third capacitor C3 is connected to the drain electrode of the first inductance L1, first capacitor C1 and the first NMOS transistor M1 Between the end D, the other end of third capacitor C3 is connect with the drain D end of third NMOS transistor M3, third NMOS transistor M3 Source S end ground connection, the grid G end of third NMOS transistor M3 is connected to digital control end；Article 2 route and Article 3 line Road and first route are arranged side by side, and connection type is identical with first route；The connection type of Article 4 route is the 6th One end of capacitor C6 is connected between the second inductance L2, the second capacitor C2 and the drain D end of the second NMOS transistor M2, the 6th electricity The other end for holding C6 is connect with the drain D end of the 6th NMOS transistor M6, the source S end ground connection of the 6th NMOS transistor M6, The grid G end of 6th NMOS transistor M6 is connected to digital control end；Article 5 route and Article 6 route and Article 4 route Side by side, and connection type is identical with Article 4 route.The working principle of coarse tuning circuit is to adjust the by digital control end The third NMOS transistor NMOS transistor M8's of M3~the 8th on one article of route to Article 6 route is switched on and off, Lai Zengjia Capacitor in RC pierce circuit, thus to reduce dither frequencies.More specifically, being illustrated below, if digital Control terminal provides a high level to the grid G end of third NMOS transistor M3, then the drain D end of third NMOS transistor M3 It is connected between source S end, under the working environment of direct current, third capacitor C3 is in parallel with first capacitor C1, then for entire For pierce circuit, then equivalent to increase a capacitor C3.And according to frequency of oscillation formula f=1/ (k* √ lc), wherein f Indicate frequency, k indicates that coefficient, l indicate induction reactance, and c indicates capacitive reactance, it is known that frequency can be according to certain when capacitor increases Ratio reduces；And there are two kinds of situations in each route, i.e., digital control end provides high level and provides low level situation, When drain D end and source S the end conducting for providing the high level then NMOS transistor of corresponding route, entire RC oscillator electricity can be given Road increases a corresponding capacitor；When providing low level, between the drain D end and source S end of corresponding NMOS transistor not It is connected, then entire RC pierce circuit will not be had an impact；Currently, there is six routes, there are two types of can on every route The adjusting situation of energy property generates, so just having 2 on 6 routes⁶=64 kinds of capacitance adjustment modes, that is to say, that have 64 kinds of frequencies Situation is adjusted, entire frequency of oscillation has thus been divided into 64 regions.Reality is during designing circuit, according to practical need It asks to set the size of the quantity of route and capacitor.

Fine tuning circuit includes variable capacitance VCTR, and one end of variable capacitance VCTR is connected to the first inductance L1, first capacitor Between C1 and the drain D end of the first NMOS transistor M1, the other end of variable capacitance VCTR is connected to the second inductance L2, the second electricity Hold between C2 and the drain D end of the second NMOS transistor M2.The working principle of fine tuning circuit are as follows: due to the one of variable capacitance VCTR End keeps connecting between first capacitor C1, third capacitor C3, the 4th capacitor C4 and the 5th capacitor C5 respectively, variable capacitance VCTR Other end keep connecting between the second capacitor C2, the 6th capacitor C6, the 7th capacitor C7 and the 8th capacitor C8, so variable Capacitor VCTR can reduce the capacitor of entire RC pierce circuit, can thus promote the frequency of entire RC pierce circuit, Frequency after coarse adjustment can be adjusted into a part further back.Simultaneously as the part of readjustment also can using variable capacitance It is adjusted.

More than, it is the relatively advanced digital oscillator based on inductance capacitance resonant cavity oscillator in current technology, Carry out frequency adjusting function it is very powerful, still, due to its coarse adjustment during be adjusted using NMOS transistor, And NMOS transistor is due to the limitation of working condition, itself is internal to contain parasitic capacitance C_d, and the size of NMOS transistor is got over Greatly, internal parasitic capacitance C_dAlso bigger, due to parasitic capacitance C_dLimitation, allow for originally it is designed based on electricity Electrification holds the degree of regulation accuracy decline of the frequency of the digital oscillator of resonator oscillator, is certain to generate deviation, and The deviation is relatively large, and the later period when the practical practical digital oscillator being somebody's turn to do based on inductance capacitance resonant cavity oscillator, needs It to be adjusted based on experience value, determine actual degree of regulation.Also, the utility model people of the application thinks that this is based on electricity The digital oscillator that electrification holds resonator oscillator can also increase adjusting on the basis of not increasing original adjusting circuit Region quantity, that is, increase the degree of regulation of frequency.

Utility model content

In view of this, the utility model proposes a kind of novel switched capacitors to trim digital controlled oscillator comprising RC oscillator Circuit, digital control end, coarse adjustment capacitor array, wherein RC pierce circuit includes: power supply VCC, first capacitor C1, the second capacitor C2, the first inductance L1, the second inductance L2, the first NMOS transistor M1, the second NMOS transistor M2, power supply VCC are direct current, the One inductance L1 and first capacitor C1 are in parallel, and one end of the first inductance L1 and first capacitor C1 is connected with power supply VCC, other end It is connected with the grid G end of the second NMOS transistor M2；Second inductance L2 and the second capacitor C2 are in parallel, and the second inductance L2 and second One end of capacitor C2 is connected with power supply VCC, and other end is connected with the grid G end of the first NMOS transistor M1, and the first NMOS is brilliant The drain D end of body pipe M1 is connected with the other end of the first inductance L1 and first capacitor C1, the source S of the first NMOS transistor M1 End ground connection；The drain D end of second NMOS transistor M2 is connected with the other end of the second inductance L2 and the second capacitor C2, and second The source S end of NMOS transistor M2 is grounded；It is characterized by: including the 9th NMOS in first article of circuit in coarse adjustment capacitor array Transistor M9, the tenth NMOS transistor M10, the 11st NMOS transistor M11, the first PMOS transistor MP1, wherein the 9th NMOS The grid G end of transistor M9, the grid G end of the tenth NMOS transistor M10, the grid G end of the 11st NMOS transistor M11 and The grid G end of one PMOS transistor MP1 is connected to digital control end, the source S end and the 11st of the tenth NMOS transistor M10 The source S end of NMOS transistor M11 connects, and the drain D end of the tenth NMOS transistor M10 is with the 11st NMOS transistor M11's The connection of drain D end, the drain D end of the 9th NMOS transistor M9 are connected to the drain D end of the tenth NMOS transistor M10, and the 9th The source S end of NMOS transistor M9 is connected to the drain D end of the 11st NMOS transistor M11；The source of first PMOS transistor MP1 The pole end S is connect with power supply VCC, and the drain D end of the first PMOS transistor MP1 is connected to the drain D end of the tenth NMOS transistor M10 Between the drain D end of the 11st NMOS transistor M11；The drain D end of tenth NMOS transistor M10 and the first PMOS transistor The drain D of the first inductance L1, first capacitor C1 and the first NMOS transistor M1 are connected between the drain D end of MP1 by lead Between position 1；Pass through between the drain D end of 11st NMOS transistor M11 and the drain D end of the first PMOS transistor MP1 Lead is connected to the position 1 ' between the second inductance L2, the second capacitor C2 and the drain D of the second NMOS transistor M2；And the tenth The length of NMOS transistor M10, the 11st NMOS transistor M11 and the first PMOS transistor MP1 are 7~100nm, the 9th NMOS The length of transistor M9 is 350~600nm, and includes MIM capacitor in the 9th NMOS transistor M9.

It is more preferred, the tenth NMOS transistor M10, the 11st NMOS transistor M11 and the first PMOS transistor MP1's Length is 7~10nm.

Further, first only containing first circuit, or containing multiple parallel connections is contained in coarse adjustment capacitor array Circuit.

Further, connect between the drain D end of the tenth NMOS transistor M10 and the drain D end of the first PMOS transistor MP1 It is connected to first resistor R1, is connected between the drain D end of the 11st NMOS transistor M11 and the drain D end of the first PMOS transistor MP1 It is connected to second resistance R2, and the resistance value of first resistor R1 and second point group R2 are equal.

Further, between the drain D end of the tenth NMOS transistor M10 and the drain D end of the first PMOS transistor MP1 When being connected to the position 1 between the first inductance L1, first capacitor C1 and the drain D of the first NMOS transistor M1 by lead, Increase by the 9th capacitor C9 on lead；In the drain D end of the 11st NMOS transistor M11 and the drain D of the first PMOS transistor MP1 The position between the second inductance L2, the second capacitor C2 and the drain D of the second NMOS transistor M2 is connected to by lead between end When 1 ', increase by the tenth capacitor C10 on lead；And the 9th capacitor C9 and the tenth capacitor C10 capacitance it is equal.

The working principle of the above coarse adjustment capacitor array is as follows: when the output signal at digital control end is high level, first The drain D end of the tenth NMOS transistor M10 on article circuit and the conducting of source S end, the drain D of the 11st NMOS transistor M11 End and the conducting of source S end, the drain D end of the 9th NMOS transistor M9 and the conducting of source S end, the first PMOS transistor MP1 cut-off, At this point, due to the tenth NMOS transistor M10, the 11st NMOS transistor M11 and the first PMOS transistor MP1 size very It is small, therefore its parasitic capacitance C_dIt can be ignored, and use MIM capacitor in the 9th NMOS transistor M9, when the 9th NMOS crystal After pipe M9 conducting, maximum capacitor Cmax is generated in entire coarse tuning circuit at this time.When the output signal at digital control end is low electricity Usually, source S end and drain D the end conducting of the first PMOS transistor MP1, the 9th NMOS transistor M9, the tenth NMOS transistor M10 and the 11st NMOS transistor M11 is by this point, since the size of the first PMOS transistor MP1 is very small, therefore first The parasitic capacitance C of PMOS transistor MP1_dCan be ignored, and the 9th NMOS transistor M9 conducting with by moment produce A small capacitances Cmin, the smallest capacitor Cmin generated in as entire coarse tuning circuit are given birth to, therefore there are two on first circuit A novel switched capacitor of adjustment trims the chance of digital controlled oscillator, and the NMOS transistor containing MIM capacitor is cleverly utilized Bulky capacitor, may not need and introduce other capacitors, the variation of the capacitor of coarse adjustment capacitor array can be realized, it is final to realize switch electricity Hold the adjusting for trimming the frequency of digital controlled oscillator.Meanwhile avoiding parasitism of the conventional use of NMOS transistor as switch when Capacitor C_dInfluence.

Further, it further includes middle tune capacitor array that the novel switched capacitor, which trims in digital controlled oscillator, middle tune electricity Hold manually electric comprising the first difference transmission lines, second differential transmission line, multiple numerical control artificial dielectrics and switch, numerical control in array Medium is metal strip, and every metal strip requires the lower section for being fitted in difference transmission lines, and the two of every metal strip according to equal proportion End is exposed to the outside of difference transmission lines, by the metal on the metal strip and second differential transmission line on the first difference transmission lines Item is sequentially connected one by one using switch；In addition one end of first difference transmission lines is connected to the first inductance L1 and first capacitor C1 One end, the other end of the first difference transmission lines are connected to the drain D end of the first NMOS transistor M1；Second differential transmission line One end is connected to the other end of the second inductance L2 and the second capacitor C2, and the other end of second differential transmission line is connected to second The drain D end of NMOS transistor M2.

Further, the first difference transmission lines are connect with multiple artificial dielectrics structure and second differential transmission line and more The structure of a artificial dielectric's connection is identical.

Further, the structure of switch is brilliant by the 9th NMOS transistor M9, the tenth NMOS transistor M10 and the 11st NMOS Body pipe M11 is constituted, and digital control end is connected to the grid at the grid G end of the 9th NMOS transistor M9, the tenth NMOS transistor M10 The end G and the 11st NMOS transistor M11 grid G end, the source S end ground connection of the tenth NMOS transistor M10, the 11st NMOS crystal Pipe M11 source S end ground connection, the drain D end of the tenth NMOS transistor M10 and the source S end of the 9th NMOS transistor M9 are connected to On a wherein metal strip for first difference transmission lines, the drain D end of the 11st NMOS transistor M11 and the 9th NMOS transistor The drain D end of M9 is connected on one of metal of second differential transmission line；The rest may be inferred, will be on the first difference transmission lines Metal strip is consecutively connected to through the above structure on the metal strip in second differential transmission line.

Further, the first difference transmission lines of unit distance and the capacitor of second differential transmission line in middle tune capacitor array Less than the MIM capacitor of third NMOS transistor.

Using the above middle tune capacitor array, compared to coarse adjustment capacitor array, reduction has used the 9th NMOS transistor M9, That is not using the NMOS transistor containing MIM capacitor to trim, but utilize the first difference transmission lines and the second difference Capacitor on transmission line between corresponding numerical control artificial dielectric is adjusted.And the structure of numerical control artificial dielectric is simpler It is single while also lower to the sensibility of technique.This structure can provide a linear discrete frequency and trim range, eliminate The shortcomings that non-linear bigoted tuning introduced due to the NMOS transistor containing MIM capacitor and high phase noise.

Adjust the working principle of capacitor array as follows in above: when digital control end provides high level, the 9th NMOS crystal The source S end of pipe M9 and the conducting of drain D end, the source S end of the tenth NMOS transistor M10 and the conducting of drain D end, the 11st NMOS The source S end of transistor M11 and the conducting of drain D end, and the 9th NMOS transistor M9, the tenth NMOS transistor M10 and the 11st The size of NMOS transistor M11 is all very small, therefore the parasitic capacitance C of the above NMOS transistor_dIt can be ignored.Due to The drain D end of ten NMOS transistor M10 and the source S end of the 9th NMOS transistor M9 are connected to the first difference transmission lines wherein On a piece metal strip, the drain D end of the drain D end of the 11st NMOS transistor M11 and the 9th NMOS transistor M9 are connected to On one of metal of two difference transmission lines, a metal strip and the second difference on the first difference transmission lines are allowed in this way Metal strip conducting on transmission line, and there are the first difference transmission lines of unit distance and second in the above circuit structure Capacitor between difference transmission lines is certain.Thus can by adjust multiple switch on-off so that multiple units away from From the first difference transmission lines and second differential transmission line between be connected, generate shunt capacitance, thus can be further The novel switched capacitor for adjusting the utility model trims the precision that the frequency of digital controlled oscillator is adjusted.

Further, it further includes fine tuning capacitor array that the novel switched capacitor, which trims in digital controlled oscillator, wherein carefully Adjust the structure of capacitor array identical with the structure of coarse adjustment capacitor array, unique distinctive points be in fine tuning capacitor array unit away from From the first difference transmission lines and second differential transmission line capacity ratio in adjust capacitor array in unit distance the first difference pass Defeated line and the capacitor of second differential transmission line are small.It may be implemented to trim the novel switched capacitor of the utility model numerical control vibration in this way The more accurate precision for swinging the frequency of device is adjusted.

Detailed description of the invention

Fig. 1 is that the structure of the current relatively stable digital oscillator based on inductance capacitance resonant cavity oscillator of performance is shown It is intended to.

Fig. 2 is that the novel switched capacitor of the utility model trims the structural schematic diagram of digital controlled oscillator.

Fig. 3 is the structural schematic diagram of coarse adjustment capacitor array.

Fig. 4 is the middle structural schematic diagram for adjusting capacitor array and fine tuning capacitor array.

Fig. 5 is the middle structural schematic diagram for adjusting capacitor array and fine tuning capacitor array.

Main element symbol description

First inductance	L1
		Second inductance	L2
First capacitor	C1
		Second capacitor	C2
Third capacitor	C3
		4th capacitor	C4
5th capacitor	C5
		6th capacitor	C6
7th capacitor	C7
		8th capacitor	C8
9th capacitor	C9
		Tenth capacitor	C10
Variable capacitance	VCTR
		First NMOS transistor	M1
Second NMOS transistor	M2
		Third NMOS transistor	M3
4th NMOS transistor	M4
		5th NMOS transistor	M5
6th NMOS transistor	M6
		7th NMOS transistor	M7
8th NMOS transistor	M8
		9th NMOS transistor	M9
Tenth NMOS transistor	M10
		11st NMOS transistor	M11
First PMOS transistor	MP1
		First resistor	R1
Second resistance	R2
		Grid	G
Source electrode	S
		Drain electrode	D

The following detailed description will be further explained with reference to the above drawings the utility model.

Specific embodiment

Case 1 is embodied:

As shown in Fig. 2, trimming the structural schematic diagram of digital controlled oscillator for the novel switched capacitor of the utility model.It is a kind of new Type switching capacity trims digital controlled oscillator comprising RC pierce circuit, digital control end, coarse adjustment capacitor array, wherein RC shakes Swinging device circuit includes: power supply VCC, first capacitor C1, the second capacitor C2, the first inductance L1, the second inductance L2, the first NMOS crystal Pipe M1, the second NMOS transistor M2, power supply VCC are direct current, and the first inductance L1 and first capacitor C1 are in parallel, and the first inductance L1 It is connected with one end of first capacitor C1 with power supply VCC, other end is connected with the grid G end of the second NMOS transistor M2；Second Inductance L2 and the second capacitor C2 are in parallel, and one end of the second inductance L2 and the second capacitor C2 are connected with power supply VCC, other end and The grid G end of first NMOS transistor M1 is connected, the drain D end of the first NMOS transistor M1 and the first inductance L1 and first capacitor The other end of C1 is connected, the source S end ground connection of the first NMOS transistor M1；The drain D end of second NMOS transistor M2 and the The other end of two inductance L2 and the second capacitor C2 are connected, the source S end ground connection of the second NMOS transistor M2；It is characterized by: It include the 9th NMOS transistor M9, the tenth in first article of circuit in (coarse adjustment capacitor array is as shown in Figure 3) coarse adjustment capacitor array NMOS transistor M10, the 11st NMOS transistor M11, the first PMOS transistor MP1, wherein the grid of the 9th NMOS transistor M9 The pole end G, the grid G end of the tenth NMOS transistor M10, the grid G end of the 11st NMOS transistor M11 and the first PMOS transistor The grid G end of MP1 is connected to digital control end, the source S end of the tenth NMOS transistor M10 and the 11st NMOS transistor M11 The connection of source S end, the drain D end of the tenth NMOS transistor M10 connect with the drain D end of the 11st NMOS transistor M11, the The drain D end of nine NMOS transistor M9 is connected to the drain D end of the tenth NMOS transistor M10, the source of the 9th NMOS transistor M9 The pole end S is connected to the drain D end of the 11st NMOS transistor M11；The source S end of first PMOS transistor MP1 and power supply VCC connect It connects, the drain D end of the first PMOS transistor MP1 is connected to drain D end and the 11st NMOS crystal of the tenth NMOS transistor M10 Between the drain D end of pipe M11；Between the drain D end of tenth NMOS transistor M10 and the drain D end of the first PMOS transistor MP1 The position 1 between the first inductance L1, first capacitor C1 and the drain D of the first NMOS transistor M1 is connected to by lead；Tenth The second electricity is connected to by lead between the drain D end of one NMOS transistor M11 and the drain D end of the first PMOS transistor MP1 Feel the position 1 ' between L2, the second capacitor C2 and the drain D of the second NMOS transistor M2；And the tenth NMOS transistor M10, the tenth The length of one NMOS transistor M11 and the first PMOS transistor MP1 are 8nm, and the length of the 9th NMOS transistor M9 is 400nm, And the 9th includes MIM capacitor in NMOS transistor M9.

The length of tenth NMOS transistor M10, the 11st NMOS transistor M11 and the first PMOS transistor MP1 are 7nm. Contain first circuit of multiple parallel connections in coarse adjustment capacitor array.And the tenth NMOS transistor M10 drain D end and the first PMOS First resistor R1, the drain D end of the 11st NMOS transistor M11 and the first PMOS are connected between the drain D end of transistor MP1 Second resistance R2 is connected between the drain D end of transistor MP1, and the resistance value of first resistor R1 and second point group R2 are equal.? First is connected to by lead between the drain D end of tenth NMOS transistor M10 and the drain D end of the first PMOS transistor MP1 When position 1 between inductance L1, first capacitor C1 and the drain D of the first NMOS transistor M1, increase by the 9th capacitor on lead C9；It is connected between the drain D end of the 11st NMOS transistor M11 and the drain D end of the first PMOS transistor MP1 by lead When to position 1 ' between the second inductance L2, the second capacitor C2 and the drain D of the second NMOS transistor M2, increase by lead Ten capacitor C10；And the 9th capacitor C9 and the tenth capacitor C10 capacitance it is equal.

It further includes middle tune capacitor array that the novel switched capacitor, which trims in digital controlled oscillator, the middle knot for adjusting capacitor array Structure is as shown in Figure 4 and Figure 5, artificial comprising the first difference transmission lines, second differential transmission line, multiple numerical controls in middle tune capacitor array Dielectric and switch, numerical control artificial dielectric are metal strip, and every metal strip requires to be fitted in difference transmission lines according to equal proportion Lower section, and the both ends of every metal strip are exposed to the outside of difference transmission lines, by the metal strip on the first difference transmission lines It is sequentially connected one by one with the metal strip in second differential transmission line using switch；One end of first difference transmission lines is connected to first The other end of inductance L1 and first capacitor C1, the other end of the first difference transmission lines are connected to the first NMOS transistor M1's Drain D end；One end of second differential transmission line is connected to the other end of the second inductance L2 and the second capacitor C2, and the second difference passes The other end of defeated line is connected to the drain D end of the second NMOS transistor M2.

The structure and second differential transmission line and multiple artificial electricity that first difference transmission lines are connect with multiple artificial dielectrics The structure of medium connection is identical.

The structure of switch is by the 9th NMOS transistor M9, the tenth NMOS transistor M10 and the 11st NMOS transistor M11 structure At digital control end is connected to the grid G end and the tenth at the grid G end of the 9th NMOS transistor M9, the tenth NMOS transistor M10 One NMOS transistor M11 grid G end, the source S end ground connection of the tenth NMOS transistor M10, the 11st NMOS transistor M11 source electrode The end S ground connection, the drain D end of the tenth NMOS transistor M10 and the source S end of the 9th NMOS transistor M9 are connected to the first difference biography On a wherein metal strip for defeated line, the drain D end of the 11st NMOS transistor M11 and the drain D of the 9th NMOS transistor M9 End is connected on one of metal of second differential transmission line；And so on, the metal strip on the first difference transmission lines is led to It crosses on the metal strip that the above structure is consecutively connected in second differential transmission line.

The first difference transmission lines of unit distance and the capacitor of second differential transmission line are less than third in middle tune capacitor array The MIM capacitor of NMOS transistor.

It further includes fine tuning capacitor array, the knot of fine tuning capacitor array that the novel switched capacitor, which trims in digital controlled oscillator, Structure is as shown in Figure 4 and Figure 5, and wherein the structure of fine tuning capacitor array is identical with the structure of coarse adjustment capacitor array, unique distinctive points It is to adjust capacitor battle array in the first difference transmission lines of unit distance in fine tuning capacitor array and the capacity ratio of second differential transmission line The first difference transmission lines of unit distance and the capacitor of second differential transmission line are small in column.It is may be implemented in this way to the utility model The more accurate precision of the novel switched capacitor frequency that trims digital controlled oscillator adjust.

Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed, But it should not be understood as limiting the scope of the patent of the utility model.It should be pointed out that for the common of this field For technical staff, without departing from the concept of the premise utility, various modifications and improvements can be made, these all belong to In the protection scope of the utility model.Therefore, the scope of protection shall be subject to the appended claims for the utility model patent.

Claims

1. a kind of novel switched capacitor trims digital controlled oscillator comprising RC pierce circuit, digital control end, coarse adjustment capacitor battle array Column, wherein RC pierce circuit includes: power supply VCC, first capacitor C1, the second capacitor C2, the first inductance L1, the second inductance L2, First NMOS transistor M1, the second NMOS transistor M2, power supply VCC are direct current, and the first inductance L1 and first capacitor C1 are in parallel, And first one end of inductance L1 and first capacitor C1 be connected with power supply VCC, the grid G of other end and the second NMOS transistor M2 End is connected；Second inductance L2 and the second capacitor C2 are in parallel, and one end of the second inductance L2 and the second capacitor C2 and power supply VCC phase Even, other end is connected with the grid G end of the first NMOS transistor M1, the drain D end of the first NMOS transistor M1 and the first electricity Sense L1 is connected with the other end of first capacitor C1, the source S end ground connection of the first NMOS transistor M1；Second NMOS transistor M2 Drain D end be connected with the other end of the second inductance L2 and the second capacitor C2, the source S of the second NMOS transistor M2 termination Ground；It is characterized by: including the 9th NMOS transistor M9, the tenth NMOS transistor in first article of circuit in coarse adjustment capacitor array M10, the 11st NMOS transistor M11, the first PMOS transistor MP1, wherein the grid G end of the 9th NMOS transistor M9, the tenth The grid G at the grid G end of NMOS transistor M10, the grid G end of the 11st NMOS transistor M11 and the first PMOS transistor MP1 End is connected to digital control end, and the source S end of the tenth NMOS transistor M10 and the source S end of the 11st NMOS transistor M11 connect It connects, the drain D end of the tenth NMOS transistor M10 is connect with the drain D end of the 11st NMOS transistor M11, the 9th NMOS crystal The drain D end of pipe M9 is connected to the drain D end of the tenth NMOS transistor M10, and the source S end of the 9th NMOS transistor M9 is connected to The drain D end of 11st NMOS transistor M11；The source S end of first PMOS transistor MP1 is connect with power supply VCC, the first PMOS The drain D end of transistor MP1 is connected to the drain D end of the tenth NMOS transistor M10 and the drain electrode of the 11st NMOS transistor M11 Between the end D；Connected between the drain D end of tenth NMOS transistor M10 and the drain D end of the first PMOS transistor MP1 by lead It is connected to the position between the first inductance L1, first capacitor C1 and the drain D of the first NMOS transistor M1；11st NMOS transistor The second inductance L2, the second capacitor are connected to by lead between the drain D end of M11 and the drain D end of the first PMOS transistor MP1 Position between C2 and the drain D of the second NMOS transistor M2；And the tenth NMOS transistor M10, the 11st NMOS transistor M11 It is 7~100nm with the length of the first PMOS transistor MP1, the length of third NMOS transistor M3 is 350~600nm, and third It include MIM capacitor in NMOS transistor.

2. novel switched capacitor as described in claim 1 trims digital controlled oscillator, it is characterised in that: the tenth NMOS transistor The length of M10, the 11st NMOS transistor M11 and the first PMOS transistor MP1 are 7~10nm.

3. novel switched capacitor as described in claim 1 trims digital controlled oscillator, it is characterised in that: contain in coarse adjustment capacitor array Have only containing first circuit, or first circuit containing multiple parallel connections.

4. novel switched capacitor as described in claim 1 trims digital controlled oscillator, it is characterised in that: the tenth NMOS transistor First resistor R1, the 11st NMOS transistor are connected between the drain D end of M10 and the drain D end of the first PMOS transistor MP1 Second resistance R2, and first resistor R1 and are connected between the drain D end of M11 and the drain D end of the first PMOS transistor MP1 The resistance value of two point group R2 is equal.

5. novel switched capacitor as described in claim 1 trims digital controlled oscillator, it is characterised in that: in the tenth NMOS transistor The first inductance L1, first capacitor are connected to by lead between the drain D end of M10 and the drain D end of the first PMOS transistor MP1 When position between C1 and the drain D of the first NMOS transistor M1, increase by the 9th capacitor C9 on lead；In the 11st NMOS crystalline substance The second inductance L2, second are connected to by lead between the drain D end of body pipe M11 and the drain D end of the first PMOS transistor MP1 When position between capacitor C2 and the drain D of the second NMOS transistor M2, increase by the tenth capacitor C10 on lead；And the 9th is electric The capacitance for holding C9 and the tenth capacitor C10 is equal.

6. novel switched capacitor as described in claim 1 trims digital controlled oscillator, it is characterised in that: further include middle tune capacitor battle array Column, comprising the first difference transmission lines, second differential transmission line, multiple numerical control artificial dielectrics and switch in middle tunes capacitor array, Numerical control artificial dielectric is metal strip, and every metal strip requires the lower section for being fitted in difference transmission lines, and every according to equal proportion The both ends of metal strip are exposed to the outside of difference transmission lines, by the metal strip and the second differential transfer on the first difference transmission lines Metal strip on line is sequentially connected one by one using switch；One end of first difference transmission lines is connected to the electricity of the first inductance L1 and first Hold the other end of C1, the other end of the first difference transmission lines is connected to the drain D end of the first NMOS transistor M1；Second is poor The other end for dividing one end of transmission line to be connected to the second inductance L2 and the second capacitor C2, the other end of second differential transmission line It is connected to the drain D end of the second NMOS transistor M2.

7. novel switched capacitor as claimed in claim 6 trims digital controlled oscillator, it is characterised in that: the first difference transmission lines with The structure of multiple artificial dielectric's connections is identical with the structure that second differential transmission line is connect with multiple artificial dielectrics.

8. novel switched capacitor as claimed in claim 6 trims digital controlled oscillator, it is characterised in that: the structure of switch is by the 9th NMOS transistor M9, the tenth NMOS transistor M10 and the 11st NMOS transistor M11 are constituted, and digital control end is connected to the 9th The grid G end of NMOS transistor M9, the grid G end of the tenth NMOS transistor M10 and the 11st NMOS transistor M11 grid G end, The source S end of tenth NMOS transistor M10 is grounded, the 11st NMOS transistor M11 source S end ground connection, the tenth NMOS transistor The drain D end of M10 and the source S end of the 9th NMOS transistor M9 are connected to a wherein metal strip for the first difference transmission lines On, the drain D end of the 11st NMOS transistor M11 and the drain D end of the 9th NMOS transistor M9 are connected to the second differential transfer On one of metal of line；The rest may be inferred, and the metal strip on the first difference transmission lines is consecutively connected to through the above structure On metal strip in second differential transmission line.

9. novel switched capacitor as claimed in claim 6 trims digital controlled oscillator, it is characterised in that: single in middle tune capacitor array Position the first difference transmission lines of distance and MIM capacitor of the capacitor less than the 9th NMOS transistor M9 of second differential transmission line.

10. novel switched capacitor as claimed in claim 6 trims digital controlled oscillator, it is characterised in that: further include fine tuning capacitor Array, wherein the structure of fine tuning capacitor array is identical with the structure of coarse adjustment capacitor array, and unit distance in fine tuning capacitor array The first difference transmission lines and second differential transmission line capacity ratio in adjust capacitor array in unit distance the first differential transfer Line and the capacitor of second differential transmission line are small.