CN214480518U

CN214480518U - Low-power-consumption large-bandwidth high-resolution low-phase noise digital controlled oscillator

Info

Publication number: CN214480518U
Application number: CN202120469309.0U
Authority: CN
Inventors: 白雪飞; 邵亚年
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-10-22
Anticipated expiration: 2031-03-04

Abstract

The utility model discloses a low-power consumption big bandwidth high resolution low phase noise numerical control oscillator, include: the device comprises a complementary differential MOS tube compensation circuit, a three-stage capacitance tuning circuit, a capacitance inductance filter circuit and a capacitive degeneration circuit, wherein a coarse tuning and a middle tuning capacitor array are connected between drain electrodes of a compensation NMOS tube and a PMOS tube in parallel, the capacitive degeneration circuit is connected between source electrodes of the two compensation NMOS tubes, and the complementary differential MOS tube compensation circuit provides negative resistance to compensate the resistance of a resonant cavity so that oscillation of the resonant cavity can be continuous; the three-stage capacitance tuning circuit is used for providing variable capacitance under different tuning accuracies to realize frequency change; the capacitance-inductance filter circuit guides thermal noise into a ground end through a capacitor and provides impedance through an inductor to inhibit the flow of flicker noise so as to filter the flicker noise of the circuit; the capacitance degradation circuit realizes smaller change capacitance by connecting the tuning capacitor array to the source electrode of the compensation MOS tube and converting the tuning capacitor array to the drain electrode in proportion, thereby realizing higher resolution.

Description

Low-power-consumption large-bandwidth high-resolution low-phase noise digital controlled oscillator

Technical Field

The utility model relates to a semiconductor integrated circuit field especially relates to a low-power consumption large bandwidth high resolution ratio low phase noise numerical control oscillator.

Background

The oscillator has very wide application in the fields of mobile communication, wireless intelligent terminals and the like. Currently, an analog oscillator is mainly used as an oscillator, and the oscillator has high power consumption, high cost, low portability and is easily influenced by digital signals in a circuit. In recent years, with the continuous decrease of the power supply voltage, the realization of the digitization of the oscillator is gradually becoming a trend.

The numerically controlled oscillator is composed of a capacitor array and a control circuit, and frequency tuning is carried out by changing a tuning capacitor through a control word. At present, oscillators improve the phase noise performance through inductance or mutual inductance tuning, but the oscillators have large power consumption and area, and are difficult to meet the requirement of mobile communication on low power consumption, so that a numerical control oscillator with low power consumption, large bandwidth, high resolution and low phase noise is indispensable.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a low-power consumption large bandwidth high resolution low phase noise numerical control oscillator is applicable to all-digital phase-locked loop IP nuclear, can be extensive be applied to low-power consumption occasions such as mobile communication, simultaneously because large bandwidth, the portability of this design is high, the integration is good, can reduce application cost.

The utility model aims at realizing through the following technical scheme: a low power, high bandwidth, high resolution, low phase noise digitally controlled oscillator comprising:

complementary difference MOS pipe compensating circuit, tertiary capacitance tuning circuit, capacitance inductance filter circuit and capacitive degeneration circuit, wherein coarse adjusting and middle adjusting capacitor array connect in parallel between the drain electrode of compensation NMOS pipe and PMOS pipe, and capacitive degeneration circuit connects between the source electrode of two compensation NMOS pipes, between the common mode point of biasing resistance R1, R2 and ground, and between PMOS pipe source electrode and power, all is connected with capacitance inductance filter circuit respectively, wherein: the complementary differential MOS tube compensation circuit provides negative resistance to compensate the resistance of the resonant cavity, so that the oscillation of the resonant cavity can be continued; the three-stage capacitance tuning circuit is used for providing variable capacitance under different tuning accuracies to realize frequency change; the capacitance-inductance filter circuit guides thermal noise into a ground end through a capacitor and provides impedance through an inductor to inhibit the flow of flicker noise so as to filter the flicker noise of the circuit; the capacitive degeneration circuit realizes smaller variable capacitance by connecting the tuning capacitor array to the source electrode of the compensation MOS tube and converting the source electrode to the drain electrode in proportion, thereby realizing higher resolution.

Furthermore, the complementary differential MOS tube compensation circuit comprises two NMOS tubes which are in cross coupling connection, the source electrodes of the two NMOS tubes are connected together, the grid electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, and the drain electrode of the first NMOS tube is connected to the grid electrode of the second NMOS tube, so that a cross coupling structure is formed.

Furthermore, the three-stage capacitance tuning circuit comprises coarse tuning, medium tuning and fine tuning capacitance arrays, the coarse tuning and medium tuning capacitance arrays are connected in parallel with drain electrodes of a compensation NMOS tube and a PMOS tube, the fine tuning capacitance arrays are connected in parallel between source electrodes of the two NMOS tubes, biasing resistors R1 and R2 are connected in series with the source electrodes of the NMOS tubes, and coarse tuning, medium tuning and fine tuning control words are respectively connected with control ends of the coarse tuning, medium tuning and fine tuning capacitance arrays.

Further, a coarse tuning capacitor in the three-stage capacitor tuning circuit is a switched capacitor circuit.

Furthermore, the medium tuning capacitor in the three-stage capacitance tuning circuit is a varactor diode capacitor circuit.

Furthermore, the fine tuning capacitor in the three-stage capacitor tuning circuit is an MOS (metal oxide semiconductor) tube capacitor, the source and drain electrodes of the two MOS tubes are connected together, high and low voltages are applied to the grid electrode, and high and low capacitors are induced between the source electrode and the grid electrode, so that smaller capacitance change is realized.

Furthermore, four groups of switch capacitors are distributed in an equal ratio to form a coarse tuning capacitor array, five groups of varactor diode capacitors and one group of MOS capacitors form a medium tuning capacitor array, and four groups of varactor diode capacitor circuits and two groups of MOS capacitors form a fine tuning capacitor array.

Further, the capacitance-inductance filter circuit specifically includes: the filter capacitor and the inductor at the ground end are connected between the common-mode point of the bias resistors R1 and R2 and the ground, the filter capacitor and the inductor at the source end are connected between the power supply and the sources of the two PMOS tubes, and the capacitors are respectively connected between the sources of the NMOS tubes M3 and M4 and the ground.

Furthermore, the resolution is further improved by converting the capacitance array connected to the source electrode to the drain electrode in proportion to realize smaller capacitance variation, and the capacitive degeneration circuit achieves higher resolution by converting the capacitance of the source electrode to the drain electrode in proportion to realize smaller capacitance variation.

The utility model discloses the principle lies in: a low power, high bandwidth, high resolution, low phase noise digitally controlled oscillator comprising: negative resistance compensation circuit, capacitance tuning circuit, capacitive degeneration circuit, noise filter circuit. The capacitance tuning circuit is connected with the drain electrode of the MOS tube of the negative resistance compensation circuit to form a resonant cavity, the capacitance degradation circuit is connected with the source electrode of the negative resistance compensation MOS tube, and the noise filter circuit is formed by a capacitance inductor connected with the source electrode of the MOS tube. Wherein:

the negative resistance compensation circuit is formed by a pair of NMOS tubes and a pair of PMOS tubes to form a complementary differential pair so as to compensate the resistance loss of the resonant cavity.

The capacitance tuning circuit is composed of three stages of tuning capacitor arrays of coarse tuning, medium tuning and fine tuning, capacitance changes of different sizes are achieved respectively, and capacitances in the capacitor arrays of each stage are distributed in an equal ratio.

The capacitive degeneration circuit is formed by connecting a fine tuning capacitor array on the source electrode of the compensation MOS tube, and the source electrode capacitance is converted into the drain electrode resonant cavity to realize degeneration.

The noise filter circuit is composed of a capacitor and an inductor, wherein the capacitor filters thermal noise, and the inductor filters flicker noise.

Has the advantages that:

the utility model provides a low-power consumption, big bandwidth, high resolution, low phase noise numerical control oscillator's realization, through the complementary difference structure of current multiplexing reduce the oscillator consumption by a wide margin; meanwhile, the circuit has a wide tuning range by adjusting the working state of the three-level tuning capacitor array, can work in a navigation mode, a communication mode and a radar mode and conforms to the communication protocol standard; finally, the application of the filter circuit makes the phase noise of the circuit easy to meet the requirements of mobile communication.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a single port oscillator;

fig. 2 is a schematic diagram of negative resistance provided by an example of the present invention, in which fig. 2(a) is a negative resistance structure of a cross-coupled MOS transistor, and fig. 2(b) is a small-signal equivalent circuit;

fig. 3 is a schematic diagram of a low power consumption, large bandwidth and high resolution digitally controlled oscillator according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a coarse tuning capacitor according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a medium-tuning capacitor according to an embodiment of the present invention;

fig. 6 is a schematic diagram of fine tuning capacitor provided by an embodiment of the present invention;

fig. 7 is a schematic diagram of a capacitive degeneration circuit provided by an embodiment of the present invention, wherein fig. 7(a) is the schematic diagram of the capacitive degeneration circuit, and fig. 7(b) is the equivalent circuit of fig. 7 (a);

fig. 8 is a schematic diagram of circuit noise according to an embodiment of the present invention;

fig. 9 is a schematic diagram of noise suppression according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

Fig. 1 shows a schematic diagram of a single-port oscillator according to the present invention, in which a resonant cavity is composed of a capacitor Cp and an inductor Lp, but the parasitic resistance Rp existing in the capacitor inductor continuously loses energy in the resonant cavity until the oscillation completely stops. At this time, if an external Circuit (Active Circuit) provides a negative resistance-Rp to compensate the parasitic resistance, the oscillation can be maintained.

Fig. 2 shows the principle of negative resistance formation, and fig. 2(a) shows the negative resistance structure of the cross-coupled MOS transistor according to the present invention. As shown in fig. 2(a), a pair of cross-coupled NMOS transistors are formed, where the sources of M1 and M2 are connected together, the gate of M1 is connected to the drain of M2, and the drain of M1 is connected to the gate of M2, thereby forming a cross-coupled structure. When a positive voltage is applied to port X, Y, the current decreases as the voltage increases, and then port X, Y appears as a negative resistance to the outside.

Fig. 2(b) is a small-signal equivalent circuit, as can be seen,

V₂-V₁＝V_x (1)

I_X＝g_m1V₁＝-g_m2V₂ (2)

wherein, g_m1、g_m2The transconductances of M1 and M2 in FIG. 2 (a); wherein M1 and M2 are NMOS tubes; v1 and V2 are gate-source voltages of MOS transistors M1 and M2;

namely, the cross-coupled MOS transistor shown in FIG. 2(a) shows a negative resistance R outside, the magnitude is shown in formula (4),

fig. 3 is a schematic circuit diagram of a low power consumption, large bandwidth and high resolution digitally controlled oscillator according to an embodiment of the present invention. The method mainly comprises the following steps: the circuit comprises a negative resistance compensation circuit, a capacitance tuning array, a capacitive degeneration circuit and a noise filter circuit. Wherein:

the embodiment of the utility model provides an in negative resistance compensating circuit constitutes complementary difference circuit by a pair of NMOS cross coupling pipe and a pair of PMOS cross coupling pipe and realizes, the electric current flows through PMOS pipe M1, M2 by the power and flows through NMOS pipe M3, M4 again as shown in FIG. 3, has been used twice, produces double negative resistance under same electric current to this realizes the low-power consumption design. As shown in FIG. 3, a pair of NMOS and a pair of PMOS are cross-coupled, an inductor, a COARSE tuning (COARSE) and a medium tuning (MIDDLE) precision capacitor array are connected in parallel with the drains of the compensation NMOS and PMOS, a filter capacitor C2 and an inductor L2 are connected between the power supply and the sources of the PMOS tubes M1 and M2, a FINE tuning capacitor array (FINE) is connected in parallel with the sources of the NMOS tubes, bias resistors R1 and R2 are connected in series with the sources of the NMOS tubes, a ground terminal filter capacitor C1 and an inductor L1 are connected between the common mode point of the bias resistors R1 and R2 and the ground, and COARSE tuning and medium tuning FINE tuning control words (FCW) are respectively connected with the control terminals of the COARSE tuning, medium tuning and FINE tuning capacitor arrays.

The embodiment of the utility model provides an in, the harmonious array circuit of electric capacity is based on the tertiary electric capacity array of coarse tuning, well mediation fine setting that switched capacitor circuit, varactor electric capacity circuit and MOS pipe electric capacity circuit constitute.

Fig. 4 shows a switched capacitor circuit, when the control word FCW is 1, the MOS transistors M1, M2, and M3 are all turned on, two capacitors are turned on and connected in parallel to the ground and the resonant cavity, the resonant cavity capacitance increases, and the resonant frequency decreases; when the control word is 0, the MOS transistors M1, M2 and M3 are all disconnected, the capacitor is disconnected from the resonant cavity, the capacitance of the resonant cavity is reduced, the resonant frequency is increased, and the switched capacitor can be used in occasions requiring large capacitance change.

Fig. 5 shows a varactor capacitance circuit, which shows different capacitances to the outside when the control word changes between 0 and 1, and can realize capacitance change in several flights (a flight is a capacitance unit).

Fig. 6 shows a MOS transistor capacitor, in which the source, the drain and the gate of two MOS transistors are connected together, and a high voltage and a low voltage are applied to the gate, so that a high capacitance and a low capacitance are induced between the source and the gate, and a smaller capacitance change is realized. By the characteristics of the three capacitor circuits, a coarse adjustment capacitor array can be formed by four groups of switch capacitors in an equal ratio distribution mode, a middle adjustment capacitor array is formed by five groups of variable capacitance diode capacitors and one group of MOS capacitors, and a fine adjustment capacitor array is formed by four groups of variable capacitance diode capacitor circuits and two groups of MOS capacitors.

In the embodiment of the present invention, the capacitive degeneration circuit realizes a smaller capacitance change by converting the source capacitance to the drain electrode according to a certain ratio, so as to achieve a higher resolution. As shown in fig. 7, which shows the principle of the capacitive degeneration circuit, in fig. 7(a), C is a coarse tuning capacitor, L is a resonant inductor, and C is a fine tuning capacitor. Rloss is the parasitic resistance of the capacitance-inductance resonant cavity, and Ced is the equivalent capacitance converted from the source capacitance to the drain resonant cavity.

The fine tuning capacitor circuit is connected to the source electrode of the MOS tube, the series-parallel connection is converted into the circuit shown in figure 7(b), the source electrode capacitance is converted into the drain electrode capacitance shown in formula (5),

wherein, g_mIs transconductance of MOS transistor, C is source electrode capacitance, w_l0Is the resonant frequency;

in radio-frequency circuits C>>g_m/(2w_l0) Then, the formula (5) is simplified to the formula (6),

wherein, g_mIs transconductance of MOS transistor, C is source electrode capacitance, w_l0To the resonant frequency, Q_fAs a conversion factor

The source electrode capacitance is converted to the drain electrode according to a certain proportion, and the conversion factor is controlled by controlling the drain electrode capacitance and the MOS tube transconductance so as to realize smaller capacitance change and achieve higher resolution.

Fig. 8 is a noise diagram of a circuit, in which Thermal noise (Thermal noise) generated by parasitic resistance of a resistor, a MOS transistor, and an inductor, and flicker noise (flicker noise) of the MOS transistor are mainly included.

In the embodiment of the present invention, the noise filter circuit is shown as a dotted line frame in fig. 9, and is used for filtering and suppressing the flicker noise in the circuit. The thermal noise is mainly guided to the ground by filtering through capacitors C3 and C4, and the flicker noise is attenuated by providing a large Impedance (High Impedance at 2W0) at the second harmonic by using a large inductor to inhibit the flow of the flicker noise in a circuit.

The embodiment of the utility model provides an above-mentioned scheme mainly has following beneficial effect:

(1) the tuning range of the oscillator is large by adopting three-stage tuning capacitors of coarse tuning, medium tuning and fine tuning.

(2) And the current multiplexing of a complementary differential structure is adopted, so that the power consumption of the circuit is low.

(3) And the capacitor inductor is adopted to filter noise, so that the phase noise is very low.

(4) The capacitive degeneration circuit is adopted, so that the resolution of the circuit is high.

The above description is only for the best embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are all covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A low power, high bandwidth, high resolution, low phase noise digitally controlled oscillator, comprising:

the device comprises a complementary differential MOS tube compensation circuit, a three-stage capacitance tuning circuit, a capacitance inductance filter circuit and a capacitance degeneration circuit, wherein a coarse tuning and a middle tuning capacitor array are connected between drain electrodes of a compensation NMOS tube and a PMOS tube in parallel, the capacitance degeneration circuit is connected between source electrodes of the two compensation NMOS tubes, and the capacitance inductance filter circuit is respectively connected between the source electrode of the NMOS tube and the ground end and between the source electrode of the PMOS tube and a power supply.

2. The digital controlled oscillator of claim 1, wherein the complementary differential MOS transistor compensation circuit comprises two NMOS transistors connected in a cross-coupling manner, sources of the two NMOS transistors are connected together, a gate of a first NMOS transistor is connected to a drain of a second NMOS transistor, and a drain of the first NMOS transistor is connected to a gate of the second NMOS transistor, so as to form a cross-coupling structure.

3. The digital controlled oscillator of claim 1, wherein the three-stage capacitor tuning circuit comprises coarse tuning, medium tuning and fine tuning capacitor arrays, the coarse tuning and medium tuning capacitor arrays are connected in parallel to drain electrodes of a compensation NMOS transistor and a PMOS transistor, the fine tuning capacitor array is connected in parallel between source electrodes of the two NMOS transistors, biasing resistors R1 and R2 are connected in series to the source electrodes of the NMOS transistors, and coarse tuning and medium tuning fine tuning control words are connected to control terminals of the coarse tuning, medium tuning and fine tuning capacitor arrays respectively.

4. A low power consumption, high bandwidth, high resolution, low phase noise digitally controlled oscillator according to claim 1, wherein the coarse tuning capacitor in the three stage capacitor tuning circuit is a switched capacitor circuit.

5. A low power consumption, high bandwidth, high resolution, low phase noise digital controlled oscillator according to claim 1, wherein the medium tuning capacitance in the three-stage capacitance tuning circuit is a varactor capacitance circuit.

6. A low power consumption, large bandwidth, high resolution, low phase noise digital controlled oscillator according to claim 1, wherein the fine tuning capacitor in the three-stage capacitor tuning circuit is a MOS transistor capacitor, and the source, drain and gate of two MOS transistors are connected together.

7. A low power consumption, high bandwidth, high resolution, low phase noise digital controlled oscillator according to claim 1, wherein four sets of switched capacitors are distributed in equal proportion to form a coarse tuning capacitor array, five sets of varactor capacitors and one set of MOS capacitors form a medium tuning capacitor array, and four sets of varactor capacitor circuits and two sets of MOS capacitors form a fine tuning capacitor array.

8. The digitally controlled oscillator of claim 1, wherein the capacitance-inductance filtering circuit comprises: the filter capacitor and the inductor are connected between the common mode point of the bias resistors R1 and R2 and the ground, the filter capacitor and the inductor are connected between the power supply and the source electrodes of the two PMOS tubes, and the filter capacitors are respectively connected between the source electrodes of the two NMOS tubes and the ground.