CN209282201U - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- CN209282201U CN209282201U CN201821957737.2U CN201821957737U CN209282201U CN 209282201 U CN209282201 U CN 209282201U CN 201821957737 U CN201821957737 U CN 201821957737U CN 209282201 U CN209282201 U CN 209282201U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000010276 construction Methods 0.000 claims abstract description 15
- 210000002615 epidermis Anatomy 0.000 claims abstract description 3
- 238000002425 crystallisation Methods 0.000 claims description 23
- 230000008025 crystallization Effects 0.000 claims description 23
- 230000003213 activating effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 57
- -1 phosphonium ion Chemical class 0.000 description 52
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- 238000002347 injection Methods 0.000 description 43
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- 230000008569 process Effects 0.000 description 30
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 25
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- 229910052732 germanium Inorganic materials 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 11
- 238000001994 activation Methods 0.000 description 10
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- 238000002513 implantation Methods 0.000 description 10
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- 239000007790 solid phase Substances 0.000 description 7
- 238000005280 amorphization Methods 0.000 description 6
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- 229910052796 boron Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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Abstract
The disclosure provides a kind of semiconductor devices, comprising: the semiconductor substrate of the first conduction type, the substrate are equipped with groove isolation construction；Active area, it is set between the groove isolation construction, including source region, drain region, the source region, the drain region include the first doped region of first conduction type and the second doped region of the second conduction type, second doped region is located at the upper epidermis of first doped region, and the drain region further includes the third doped region for being connected to second doped region lower part；Embedded type word line structure, the embedded type word line structure setting is between the source region and the drain region and runs through second doped region, wherein the third doped region is between the embedded type word line structure.The semiconductor devices that the disclosure provides can improve the activating ion concentration in LDD region domain while limiting LDD region field width and spending.
Description
Technical field
This disclosure relates to technical field of manufacturing semiconductors, in particular to a kind of semiconductor devices.
Background technique
With the hair of DRAM (Dynamic Random Access Memory, dynamic random access memory) manufacturing technology
It opens up, under identical memory chip size, becomes raising storage energy using the miniature density to increase storage unit of access device
The main trend of power.When DRAM memory cell size by 6F2 it is miniature to 4F2 when, the Distance Shortened of adjacent memory part will cause
Coupling effect between adjacent transistor and character line is stronger, in turn results in the memory device on one line of storage unit in frequency
The memory device leakage current of adjacent line is caused to increase in forthright switch operating process, this effect is known as row hammer effect (Row
Hammer Effect).In the related technology, it is proposed that in the adjacent memory device for burying word-line (Buried Word Line)
Total source/drain region increase by one of phosphonium ion by increasing by one mask exposure developing process in the implantation process of N-type trap
The step of injection, to change the doping concentration distribution situation of trap inside storage array device architecture.
The position of exhaustion region is adjusted by the way that correct phosphonium ion implant dosage and energy is arranged, it can be by exhaustion region
The regional screen effect (Shield effect) that electric field generates operates to reduce specific character on-line storage device in frequency
Hour hammer door (hammering gate) causes the chance that electronics in logical leakage current is moved to adjacent character on-line storage device.So
And more one of mask exposure developing process will will increase manufacturing cost, therefore, it is necessary to one kind can not increase changing for manufacturing cost
The device architecture of benefaction hammer effect.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The disclosure is designed to provide a kind of semiconductor devices, for overcoming the relevant technologies to be at least to a certain extent
The problem of reducing row hammer effect and increasing manufacturing cost.
According to the disclosure in a first aspect, providing a kind of semiconductor devices, comprising:
The semiconductor substrate of first conduction type, the substrate are equipped with groove isolation construction；
Active area is set between the groove isolation construction, including source region, drain region, the source region,
The drain region includes the first doped region of first conduction type and the second doped region of the second conduction type,
Second doped region is located at the upper epidermis of first doped region, and the drain region further includes being connected to described second
The third doped region of doped region lower part；
Embedded type word line structure, the embedded type word line structure setting is between the source region and the drain region
And run through second doped region, wherein the third doped region is between the embedded type word line structure.
In an exemplary embodiment of the disclosure, the forming process of second doped region includes:
The semiconductor ion of first dosage is injected to form the first non-crystallization region to first doped region；
Second conductive type ion for the first time is carried out to first non-crystallization region and injects processing procedure, and carries out quick heat and moves back
Fire process and solid phase epitaxial recrystallization technique；
Wherein, the semiconductor ion includes silicon ion or germanium ion, and the implantation dosage of the semiconductor ion is greater than
3e14cm-2。
In an exemplary embodiment of the disclosure, the forming process of the third doped region includes:
The junction of second doped region and first doped region between the embedded type word line structure is infused
Enter the semiconductor ion of third dosage to form the second non-crystallization region；
Second of second conductive type ion is carried out to second non-crystallization region and injects processing procedure, and in subsequent production position
Rapid thermal anneal process and solid phase epitaxial recrystallization technique are carried out during contact structure；
Wherein, the semiconductor ion includes silicon ion or germanium ion, and the implantation dosage of the semiconductor ion is greater than
3e14cm-2。
In an exemplary embodiment of the disclosure, the second conductive type ion of first time injection processing procedure includes phosphonium ion
The depth of injection and arsenic ion injection, the phosphonium ion injection is greater than the depth of arsenic ion injection, the note of the phosphonium ion
Enter dosage greater than 1e13cm-2, the implantation dosage of the arsenic ion is 1e14cm-2~5e14cm-2。
In an exemplary embodiment of the disclosure, second of second conductive type ion injection processing procedure includes phosphonium ion
The implantation dosage of injection, the phosphonium ion is greater than 1e13cm-2。
In an exemplary embodiment of the disclosure, the semiconductor substrate include the deep-well region of second conduction type with
And the well region of second conduction type below the groove isolation construction, the well region are located at first doped region
The lower section in domain simultaneously connects the groove isolation construction bottom and the deep-well region.
In an exemplary embodiment of the disclosure, further include be set to it is described between the adjacent embedded type word line structure
The contact zone of conductive bitline contact structures on drain region, the conductive bitline contact structures and the drain region includes described second leading
The Doped ions of electric type.
In an exemplary embodiment of the disclosure, the Doped ions are arsenic, and the dopant dose of the Doped ions is
1e15cm-2~4e15cm-2。
The LDD region domain for the semiconductor devices that the embodiment of the present disclosure provides is before formation by the decrystallized of p-well region
Processing, can effectively limit the injection depth of the phosphonium ion and arsenic ion that are subsequently implanted into, so that in the phosphonium ion of injection large dosage
After arsenic ion, LDD region domain both can keep diffusion depth in safe range, be unlikely to cause short-channel effect, and can
With more activating ions, so that LDD region domain has lower resistance and bigger conducting electric current, semiconductor devices has more
High service speed.It is formed in addition, bit line contacting window region passes through Twice Amorphization and injects phosphonium ion, common drain/supply source
The PN junction exhaustion region at pole position extends to channel direction, cooperates lower conducting resistance, can be effectively reduced row hammer effect.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
The process structure schematic diagram for the semiconductor devices that Fig. 1 disclosure provides.
Fig. 2 and Fig. 3 is the schematic illustration of the embodiment of the present disclosure.
Fig. 4 A~Fig. 4 R is the detailed manufacturing process schematic diagram of semiconductor devices in an embodiment of the present disclosure.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used
Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and
So that all aspects of this disclosure thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure
Point, thus repetition thereof will be omitted.
The process structure schematic diagram for the semiconductor structure that Fig. 1 disclosure provides.
With reference to Fig. 1, in the embodiments of the present disclosure, semiconductor structure 100 may include:
P-type silicon substrate portion 1, groove isolation construction 2, deep n-type well layer 3, N-type well region 4, p-well region 5, the second doped region 7
(lightly doped drain region/LDD region domain), third doped region 72, gate insulator oxide layer 81, gate metal layer 82, N-type are heavily doped
Miscellaneous conductive bitline contact structures 9 and dielectric layer 83.Wherein, the second doped region 7 is provided with the wordline ditch for being deep into p-well region 5
Slot 8, third doped region 72 is located between two wordline grooves 8 and the lower part of the second doped region 7 corresponding with drain region
Connection, gate insulator oxide layer 81 are covered on 8 surface of wordline groove and extend surface and the groove for being laid in the second doped region 7
Isolation structure 2 connects, and gate metal layer 82 is deposited with inside wordline groove 8.Dielectric layer 83 is deposited on gate metal layer 82.
Second doped region 7 and third doped region 72 can be pressed down by the non-crystallization region that decrystallized processing procedure is formed in advance
System is subsequently implanted into the diffusion depth of ion, in n-type doping ion implanting and after carrying out thermal annealing, recrystallization processing procedure, forms list
The higher LDD region domain of N-type ion concentration in the volume of position, to have lower conducting resistance and biggish conducting electric current, simultaneously
Short-channel effect and GIDL effect are avoided, the service speed of device can be effectively promoted, realizes supershallow connection surface production.Third
The setting of doped region 72 makes the depth in the corresponding LDD region domain in drain region greater than the depth in the corresponding LDD region domain in source region,
Row hammer effect can effectively be inhibited.
In addition, conductive bitline contact structures 9 are doped with arsenic ion, to promote conducting electric current.Preferably, the second doped region is being formed
During domain 7 and third doped region 72, the dosage of decrystallized processing procedure injection germanium ion or silicon ion is greater than 3e14cm-2,
1e13cm is greater than to the dopant dose of the phosphonium ion of non-crystallization region injection after decrystallized processing procedure-2, the doping of the arsenic ion of injection
Dosage is 1e14cm-2~5e14cm-2, the temperature of thermal annealing is 1000 DEG C or more after ion implanting.
In semiconductor structure shown in Fig. 1, the production of the second doped region 7 (N-type LDD region domain (Source/Drain))
The silicon or germanium ion for first passing through ion implantation technology injection high dose, make the monocrystalline silicon region injected form non-crystallization region
(PAI) N-type depth doping phosphonium ion (greater than the dosage of traditional handicraft) and high dose after, then to non-crystallization region injection middle dosage
Shallow doping arsenic ion is improved by solid phase epitaxial recrystallization technique (SPER) and is activated in subsequent high temperature thermal annealing production process
Ion doping concentration reduces the conducting resistance in LDD region domain.Make the manufacturing process and the second doped region of third doped region 72
The production in domain 7 is similar, only can choose when to the n-type doping ion of non-crystallization region injection middle dosage and is only injected into phosphonium ion
(greater than the dosage of traditional handicraft).
Above-mentioned injection processing procedure effectively inhibits the diffusion depth of n-type doping ion, improve in unit volume n-type doping from
The concentration of son, and then conducting electric current, service speed when improving device operation, reduce conducting resistance.It is mixed due to inhibiting
The diffusion depth of miscellaneous element effectively prevents short-channel effect and GIDL effect.Meanwhile the conduction by the way that drain region is arranged is logical
Road length can inhibit row hammer effect in the conductive channel of source region on the basis of not increasing mask processing procedure, and utilize simultaneously
Lower conducting resistance further decreases row hammer effect.
Fig. 2 and Fig. 3 is the schematic illustration of the embodiment of the present disclosure.
With reference to Fig. 2, when not making third doped region between p-well region 1 and LDD region domain 2, when wordline WLA does frequency
Property switch operation when, the electrons of generation, which are attracted by high potential rank by neighbouring wordline WLB, to be generated leakage current 3 in the past and causes
Row hammer effect, causes the interference of intercharacter.
According to PN junction theoretical basis, the vague and general sector width of PN junction is mainly determined by low concentration region, with reference to Fig. 3, two
Between adjacent word line increase third doped region 4 (depth equivalent to increase the second doped region) after, PN junction it is vague and general
Region and its built in field will extend downwardly, this will to generate the electronics of high potential rank by vague and general in the channel wordline WLA
In area built in field effect and drift about flow to altogether bit line (Common bit line) and in a very short period of time with hole-recombination,
The drain current path originally in Fig. 2 is plugged, the interference caused by row hammer effect to wordline WLB is reduced.
In addition, the embodiment of the present disclosure is in the LDD region domain of DRAM Access device device, by the region P-Well
Boron ion injection is carried out to reduce the resistance in doping phosphorus region in lightly doped drain region (Lightly Doped Drain, LDD)
Value increases conducting electric current, and Lai Tisheng is turned on/off current ratio (on/off current ratio), main possible machine
It is made as generated decrystallized depth when PAI (Pre-Amorphization Implantation, preparatory decrystallized doping) step
The interstitial atom and boron atom that the degree region (End-of-Range, EOR) is released in annealing can generate reciprocation, in turn
The phenomenon that reducing and reacted between phosphorus and interstitial atom, and more phosphorus atoms is made to generate activation.Solve the utility model technology
Technical solution used by problem is the system applied to DRAM Access Device LDD using preparatory preamorphization process technology
To make, improve phosphorus doping dosage whereby and can inhibit the diffusion of phosphorus, this method can effectively improve the activation carrier concentration in LDD region domain,
The conducting resistance in LDD region domain is reduced, the driving current and service speed when transistor works are increased and can avoid causing short channel
And the innovative technology mode of GIDL (gate-induced drain leakage, grid induced drain leakage current) effect.
In the following, being illustrated so that the first conduction type is p-type, the second conduction type is N-type as an example to the embodiment of the present disclosure.
It is understood that it is N-type, the side that the second conduction type is p-type that the embodiment of the present disclosure, which can also be applied in the first conduction type,
In case, the disclosure is not particularly limited this.
Fig. 4 A~Fig. 4 P is the detailed manufacturing process schematic diagram of semiconductor devices in an embodiment of the present disclosure.
In Fig. 4 A, (the Shallow Trench of fleet plough groove isolation structure 2 is made in P type substrate 1 using masked etch process
Isolation, STI), manufacturing process for example may include deposition, gluing, transfer, etching, insulating layer production, metal deposit etc.
Related STI manufacture craft, the disclosure are not limited.
In Fig. 4 B, phosphonium ion is injected to form deep n-type well area 3 (Deep N-Well, DNW).
In Fig. 4 C, phosphonium ion is injected into the bottom of STI by mask process, forms the N well region in connection deep N-well region
4(N-Well)。
In Fig. 4 D, boron ion is injected to form the first doped region 5 (p-well region, P-Well) on substrate P top.
With reference to Fig. 4 A~Fig. 4 D, before forming active area, can first be provided with groove isolation construction (STI,
Shallow Trench Isolation) P type substrate on carry out ion implanting sequentially to form deep N-well region, N well region, P
Well area, is wherein silica inside groove isolation construction, and outside is insulating layer.Next, can be with structure shown in Fig. 4 D
Substrate makes N-type lightly doped drain region (LDD).In some embodiments, groove isolation construction is formed to mark off active area
The step of can also be in production deep N-well region, N well region, after p-well region, the disclosure is not limited.
In Fig. 4 E, carry out the LDD-PAI technique (the first preamorphization process) of disclosure proposition, to p-well region injection silicon from
Son or germanium ion (dosage > 3e14cm-2) to form the first non-crystallization region 6.
In Fig. 4 F, phosphonium ion and arsenic ion are injected to non-crystallization region, wherein the injection depth of phosphonium ion is greater than arsenic ion
Injection depth, phosphonium ion implantation dosage be greater than 1e13cm-2, arsenic ion implantation dosage is in 1e14cm-2~5e14cm-2Between, with
Activating ion concentration is improved to reduce the conducting resistance in LDD region domain.
In Fig. 4 G, high temperature (1000 DEG C or more) rapid thermal annealing (Rapid Thermal Anneal) and SPER work are carried out
Skill makes arsenic, phosphonium ion activation diffusion to form the first doped region 7.
Ion implantation is that the atom of dopant is introduced one of solid material modification method.Briefly, ion
The process of injection be exactly in vacuum system, with through acceleration the atom to be adulterated ion exposure (injection) solid material,
To form the superficial layer (implanted layer) with special nature in selected (being injected) region.Wherein, it injects
The depth distribution of ion can be controlled by acceleration voltage, i.e., controlled by Implantation Energy.
Then more refinement ground injects the process of semiconductor ion for example to p-well region 5 as shown in Figure 4 E are as follows: firstly, logical
Ion implantation is crossed with the germanium ion of first the first dosage of energy injection or silicon ion in the surface layer of p-well region 5 and along P type substrate
1 direction extends, and forms first non-crystallization region 6 with the first depth.
In the embodiments of the present disclosure, the concentration of the silicon ion or germanium ion that inject during the first non-crystallization region 6 is formed
Greater than 3e14cm-2；The n-type doping ion of processing procedure is doped for example including phosphonium ion or arsenic ion to the first non-crystallization region 6,
Wherein the depth of phosphonium ion injection is greater than the depth of arsenic ion injection, and the implantation dosage of phosphonium ion is greater than 1e13cm-2, arsenic ion
Implantation dosage is 1e14cm-2~5e14cm-2.It should be noted that due to carrying out preparatory amorphous when silicon substrate plate temperature is room temperature
EOR defect interface (amorphized silicon and monocrystalline silicon substrate can be generated in the decrystallized silicon layer and its lower zone of silicon substrate by changing processing procedure
Interface), even if EOR defect interface still can exist to increasing drain current path and size after subsequent anneal process,
Therefore substrate temperature needs to maintain 0 DEG C hereinafter, optimum temperature range is -50 DEG C~-150 DEG C, to have in amorphization
Effect avoids the generation of leakage current.
The process that n-type doping ion is injected in Fig. 4 F for example can be with are as follows: with the second energy to the first non-crystallization region 6 first
The phosphonium ion of the second dosage is injected, the phosphonium ion injection region 61 of the second depth is formed；Next with third energy to amorphized areas
The arsenic ion of third dosage is injected in domain 6, to form the arsenic ion injection region 62 of third depth.Wherein, third energy is less than second
Energy, the second energy is less than the first energy；Less than the second depth, (the injection depth of phosphonium ion is greater than the note of arsenic ion to third depth
Enter depth), the second depth is less than or equal to the first depth (depth that the injection depth of phosphonium ion is less than non-crystallization region)；Third agent
For amount less than the second dosage, the first dosage is, for example, to be greater than 3e14cm-2, the second dosage for example can be for greater than 1e13cm-2。
Next, made by rapid thermal anneal process (temperature be greater than 1000 DEG C) arsenic ion in the first non-crystallization region 6,
Phosphonium ion activation diffusion, then by solid phase epitaxial recrystallization (Solid Phase Epitaxy Recrystallization,
SPER) technique makes each injection ion in the second doped region recrystallize (SPER) to form the second doped region 7.
In the embodiments of the present disclosure, first sharp before the second doped region 7 (Source/Drain) of semiconductor devices is formed
With ion implantation technology to the silicon ion or germanium ion of p-well region injection high dose, the monocrystalline silicon region for injecting it is decrystallized.
The gap that the amorphization depth region (End-of-Range, EOR) generated during decrystallized (PAI) is released in annealing
Ion can generate reciprocation with the boron ion of p-well region, and then reduce and react between phosphonium ion and gap ion, make more
Phosphonium ion activation.After the germanium ion or Si ion implantation of high dose, the silicon materials region (p-well region 5) for having crystal orientation originally will be made
Structure (first non-crystallization region 6) of the amorphous to change is formed, it is deep to the injection of subsequent n-type doping ion (phosphonium ion and arsenic ion)
Degree has inhibitory effect, and then in the case where reaching the same process conditions of supershallow connection surface (injection rate of n-type doping ion is identical), can increase
Add n-type doping ion in the implantation dosage of unit injection region, effectively improves the activation concentration of n-type doping ion.
By injecting middle dosage N-type doping P elements (greater than the dosage of traditional handicraft) and high dose deeply to non-crystallization region
Shallow doping arsenic element, and solid phase epitaxial recrystallization (Solid Phase is carried out in subsequent high temperature thermal annealing manufacturing process
Epitaxy Recrystallization, SPER) technique, it is higher ion activation concentration can be formed with source area in drain region
N-type LDD region, reduce transistor in N-type LDD region series resistance, and then promoted conducting electric current, promoted device service speed.
In Fig. 4 H, wordline metal gate region ditch slot definition (Word-Line Metal-Gate region define is carried out
trench)。
In Fig. 4 I, completes wordline metal gate region trench region mask lithography and formed wordline groove 8.
In the processing procedure shown in Fig. 4 H~Fig. 4 I, etching forms wordline groove.By general lithographic method, according to wordline ditch
The depth and spatial design of slot 8 require to complete etching, make wordline groove 8 across the second doped region 7 and partial etching first is mixed
Miscellaneous region (p-well region 5).
In Fig. 4 J, gate oxidation process is completed, forms gate insulator oxide layer on the surface of wordline groove 8.Pass through high temperature
Processing procedure forms gate insulator oxide layer 81 on the surface of wordline groove 8, at the same time, since high temperature causes the second doped region 7
In germanium ion and silicon materials generate oxidation reaction so that silicon materials are converted into germanium material.It can be with defined word line trenches 8
The second doped region between groove isolation construction 2 is source region, the second doped region between adjacent wordline groove 8
For drain region.The second doped region 7 can also be referred to as N-type lightly doped drain region (LDD) as a result,.Due to n-type doping from
The solid solubility of sub (such as arsenic ion and phosphonium ion) in germanium material is higher than silicon materials, further improves n-type doping
The activation concentration of ion, thus for the n-type doping ion of same injection rate, the second doped region being made of germanium material
7 is smaller compared to the series resistance in the LDD region domain being made of silicon materials, and conducting electric current is higher.
In Fig. 4 K, metal gates (TiN/W) depositing operation and dry etching process are completed.
It is required according to the depth design of gate metal layer 82, deposits the metal of corresponding amount of metal in one in wordline groove 8
Gate metal layer 82 is formed in wordline groove 8 on partially (bottom).And the top water horizontal line of gate metal layer 82 is higher than second and mixes
The horizontal line that miscellaneous region 7 connects with p-well region 5.Preferably, the metal that this step is deposited is tungsten.
In Fig. 4 L, dielectric barrier layer deposition is completed.Preferably, the material of dielectric barrier layer is silicon nitride (SiN), passes through one
As deposition method, deposited silicon nitride is in 82 surface of gate metal layer in wordline groove 8, until the upper surface of covering substrate,
To form dielectric barrier layer 83.
In Fig. 4 M, it may include contraposition that bit line contacting window (Bit-Line Contact) is formed between adjacent word line groove
The definition of line contact window position and the production for being etched completion bit line contacting window region.It first can be according to the second doped region
The position of drain region determines the position of bit line contacting window 91 on the surface of drain region in domain 7, and then determines bit line contacting window
The position of 91 corresponding dielectric barrier layers 83 performs etching downwards dielectric barrier layer 83 to the position until exposing in wordline groove
The upper surface of the second doped region 7 between 8, using as bit line contacting window 91.
In Fig. 4 N, from bit line contact area, it is decrystallized to carry out second for the junction to the first doped region 5 and the second doped region 7
Dopping process is to form the second non-crystallization region 71.
In Fig. 4 O, third time doping injection is carried out in bit line contact zone (bit line contacting window to the second non-crystallization region 71
91) the third doped region 72 of the second doped region 7 of connection is formed under.
In the step shown in Fig. 4 N, the injection ion and ion implantation dosage of the second decrystallized dopping process can be with first
Decrystallized dopping process is identical.In the step shown in Fig. 4 O, third time doping injection includes that phosphonium ion injects, phosphonium ion injection
Dosage is greater than 1e13cm-2.
In Fig. 4 P~Fig. 4 R, in forming initial conductive bitline contact structures on bit line contacting window, and complete in the process pair
The quick thermal annealing process of third doped region 72.It in some embodiments, further include that the conductive bitline contact structures are successively carried out
Arsenic ion injection and thermal activation treatment activate bit line contact zone to be formed.Wherein, arsenic ion implantation dosage is 1e15cm-2~
4e15cm-2, thermal activation treatment is rapid thermal annealing ion activation, and the treatment temperature of quick thermal annealing process is 800-1000 DEG C.
In Fig. 4 P, carry out in-situ polycrystalline siliceous deposits (in-situ Poly-Si Deposition), to form covering bit line
The polysilicon layer 92 of contact hole 91.
In Fig. 4 Q, it is etched technique and forms initial conductive bitline contact structures 93 and complete to initial conductive bitline contact structures 93
High concentration dosage N+ arsenic ion injects to reduce contact resistance.Specifically, by ion implantation technology using the 4th energy to first
Beginning conductive bitline contact structures 93 inject N-type ion, and the N-type ion of injection is preferably arsenic ion, and the arsenic ion for injecting this is located at
On the interface of initial conductive bitline contact structures 93 and the second doped region 7, to reduce the contact resistance between the two regions.
It is that N+ drain electrode and third doped region 72 carry out high-temperature thermal annealing ion to initial conductive bitline contact structures 93 in Fig. 4 R
Activating process and solid phase epitaxial recrystallization technique (i.e. second of SPER technique) form conductive bitline contact structures 9 afterwards.At this point, bit line connects
Activating ion doping concentration in touching structure 9 is improved, and has lower resistance and higher conducting electric current.Bit line contact
The depth in the LDD region domain of the corresponding drain region in 9 lower section of structure is big compared with the depth in the LDD region domain of source region, can effectively drop
Low row hammers interference of the effect to adjacent devices wordline into shape, further decreases the conducting resistance in channel, promotes conducting electric current.
In conclusion the embodiment of the present disclosure is by adjusting the ion implanting depth in amorphization and adulterates phosphonium ion
Implant energy size adjusts the LDD region domain diffusion depth of source electrode and drain electrode, and then adjusts that concentration area is lightly doped in N-type and design is logical
The length in road, has at least the following advantages:
1. maintaining same mask number decline low row to hammer effect into shape, the increase to cost of manufacture is avoided；
2. by carrying out preparatory preamorphization process before the manufacture of the lightly doped drain region region (LDD) N can be being increased
Inhibit the injection depth of subsequent n-type doping atom while the implantation dosage of type foreign atom, improves the ion activation in LDD region domain
Concentration forms the abrupt interface near the interface PN, increases vague and general sector width；
3. row hammer effect can be effectively reduced to neighbouring by Twice Amorphization technique adjustment drain transistor passage length
The interference of word lines further decreases the conducting resistance in channel, promotes conducting electric current.
In addition, above-mentioned attached drawing is only schematically illustrating for the processing according to included by the utility model exemplary embodiment,
Rather than limitation purpose.It can be readily appreciated that above-mentioned processing shown in the drawings does not indicate or limits the time sequencing of these processing.
Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein
Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications are used
Way or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in
Common sense or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are by weighing
Benefit requires to point out.
Claims (5)
1. a kind of semiconductor devices characterized by comprising
The semiconductor substrate of first conduction type, the substrate are equipped with groove isolation construction；
Active area is set between the groove isolation construction, including source region, drain region, the source region, described
Drain region includes the first doped region of the first conduction type and the second doped region of the second conduction type, and described second
Doped region is located at the upper epidermis of first doped region, and the drain region further includes being connected to second doped region
The third doped region of lower part；
Embedded type word line structure, the embedded type word line structure setting is between the source region and the drain region and passes through
Second doped region is worn, wherein the third doped region is between the embedded type word line structure.
2. semiconductor devices as described in claim 1, which is characterized in that it is decrystallized that second doped region is formed in first
In region, first non-crystallization region is formed in first doped region.
3. semiconductor devices as described in claim 1, which is characterized in that it is decrystallized that the third doped region is formed in second
Region, second non-crystallization region are formed at the junction of second doped region and first doped region.
4. semiconductor devices as described in claim 1, which is characterized in that the semiconductor substrate includes second conductive-type
The well region of the deep-well region of type and second conduction type below the groove isolation construction, the well region are located at institute
State the lower section of the first doped region and connect the groove isolation construction bottom and the deep-well region.
5. semiconductor devices as described in claim 1, which is characterized in that further include being set to the adjacent embedded type word line knot
The conductive bitline contact structures on the drain region between structure.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211122A (en) * | 2018-11-21 | 2020-05-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN113497129A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2023010606A1 (en) * | 2021-08-05 | 2023-02-09 | 长鑫存储技术有限公司 | Semiconductor storage apparatus and forming method |
| US12069850B2 (en) | 2020-10-15 | 2024-08-20 | Changxin Memory Technologies, Inc. | Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer |
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2018
- 2018-11-21 CN CN201821957737.2U patent/CN209282201U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211122A (en) * | 2018-11-21 | 2020-05-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN111211122B (en) * | 2018-11-21 | 2024-05-21 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN113497129A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113497129B (en) * | 2020-04-07 | 2023-12-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| US12069850B2 (en) | 2020-10-15 | 2024-08-20 | Changxin Memory Technologies, Inc. | Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer |
| WO2023010606A1 (en) * | 2021-08-05 | 2023-02-09 | 长鑫存储技术有限公司 | Semiconductor storage apparatus and forming method |
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