CN209150484U - A kind of VCSEL laser driving circuit under low voltage cmos technique - Google Patents
A kind of VCSEL laser driving circuit under low voltage cmos technique Download PDFInfo
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- CN209150484U CN209150484U CN201822011269.6U CN201822011269U CN209150484U CN 209150484 U CN209150484 U CN 209150484U CN 201822011269 U CN201822011269 U CN 201822011269U CN 209150484 U CN209150484 U CN 209150484U
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Abstract
A kind of VCSEL laser driving circuit under low voltage cmos technique, including the first, second NMOS tube, the first, second, third, fourth PMOS tube；The grid of first NMOS tube connects the first input voltage, and drain electrode connects second source voltage by resistance, inductance, grid and the drain electrode of the first PMOS tube are connect by first capacitor, grid and the drain electrode of third PMOS tube are connect by the second capacitor, source electrode connects current source；The grid of second NMOS tube connects the second input voltage, and drain electrode connects the drain electrode of the 4th PMOS tube and the anode of laser diode VCSEL, source electrode connect current source；The drain electrode of first PMOS tube connects the source electrode of third PMOS tube, and source electrode connects the first supply voltage, and grid connects the grid of the second PMOS tube, and the drain electrode of the second PMOS tube connects the source electrode of the 4th PMOS tube, and source electrode connects the first supply voltage；The drain electrode of third PMOS tube connects current source, and grid connects the grid of the 4th PMOS tube.The utility model realizes the combination of high power supply voltage and the design of low-voltage core metal-oxide-semiconductor, avoids the use of high-voltage MOS pipe, effective guarantee high bandwidth index.
Description
Technical field
The utility model relates to the VCSEL Laser Driven asic chip design fields in optical fiber data transmission system, specifically
The VCSEL laser driving circuit being related under a kind of low voltage cmos technique.
Background technique
The features such as large capacity that optical fiber telecommunications system has with it, has obtained hair at full speed in network and multimedia communication
The features such as exhibition, VCSEL laser is with small divergence angle, high bandwidth, threshold current are small, easy large area array Integrated manufacture, is logical in current optical fiber
It is used widely in letter system.The threshold voltage representative value of VCSEL laser is between 1.6V~2.0V, corresponding driving chip
Final output grade need sufficiently large supply voltage to provide enough voltage margins, be typically 3.3V.In low voltage cmos
Under technique (such as CMOS 65nm core voltage is 1.2V) background, design driven ASIC circuit cannot make for high bandwidth consideration
With high-voltage MOS pipe (load excessive reduction bandwidth), this contradiction is to design laser driving chip band under low voltage cmos technique
Problem is carried out.
Summary of the invention
The technical problems to be solved in the utility model is, in order to overcome the lance of high power supply voltage Yu low voltage cmos technology room
Shield provides the VCSEL laser driving circuit under a kind of low voltage cmos technique, realizes high power supply voltage and low-voltage core
The combination of metal-oxide-semiconductor design, makes driving circuit possess sufficiently large voltage margin, provides sufficiently large out-put dynamic range, simultaneously
Avoid the use of high-voltage MOS pipe, effective guarantee high bandwidth index.
Used technical solution is the utility model to solve above-mentioned technical problem:
A kind of VCSEL laser driving circuit under low voltage cmos technique, including the first NMOS tube NM1, the 2nd NMOS
Pipe NM2, the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4, first capacitor C1, second
Capacitor C2, resistance R1, inductance L and laser diode VCSEL；
The drain electrode that the grid of the first NMOS tube NM1 meets the first input voltage vin p, the first NMOS tube NM1 is on the one hand logical
Resistance R1, inductance L is crossed to be connected with second source voltage VDD2, on the other hand by first capacitor C1 respectively with the first PMOS tube
The grid of PM1 is connected with drain electrode, but also is connected respectively with the grid of third PMOS tube PM3 and drain electrode by the second capacitor C2
It connects, the source electrode of the first NMOS tube NM1 is connected with current source Imod；
The grid of the second NMOS tube NM2 connects the second input voltage vin n, the drain electrode and the 4th of the second NMOS tube NM2
The drain electrode of PMOS tube PM4 is connected, and the source electrode of the second NMOS tube NM2 is connected with current source Imod；
The drain electrode of the first PMOS tube PM1 is connected with the source electrode of third PMOS tube PM3, the source of the first PMOS tube PM1
Pole meets the first supply voltage VDD1；
The grid of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, the leakage of the second PMOS tube PM2
Pole is connected with the source electrode of the 4th PMOS tube PM4, and source electrode meets the first supply voltage VDD1；
The drain electrode of the third PMOS tube PM3 is connected with current source Ibias, the grid and the 4th of third PMOS tube PM3
The grid of PMOS tube PM4 is connected；
The drain electrode of the anode and the 4th PMOS tube PM4 of the laser diode VCSEL and the drain electrode of the second NMOS tube NM2 connect
It connects, the minus earth of laser diode VCSEL.
According to the above scheme, the first supply voltage VDD1 is 3.3V supply voltage.
Compared with prior art, the utility model has the beneficial effects that
1, cascode current source structure is constituted using PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4,
By simple and practical circuit structure, the combination of high power supply voltage and the design of low-voltage core metal-oxide-semiconductor is realized, in low voltage cmos
Technique (such as CMOS 65nm 1.2V core voltage) design, using under 3.3V supply voltage situation, remains to ensure each PMOS
Three end voltage differences of pipe are all within 1.2V, and under the conditions of avoiding using high-voltage MOS pipe, laser driving circuit is able to use
3.3V high power supply voltage power supply, make driving circuit possess the sufficiently large bias of sufficiently large voltage margin and dynamic range,
Modulation current output capability meets the safety requirements of low voltage cmos core metal-oxide-semiconductor simultaneously, effective guarantee high bandwidth
Index；
2, it is directed to cascade superimposed current source structure, the utility model proposes use capacitor C1, C2 to be connected with resistance R1,
The double capacitive feedforward circuits for being directed to current source are formed, bandwidth and optimization output have effectively been expanded；
3, inductor peaking technology is used in output stage left arm, the drain load of NMOS tube NM1 is resistance R1, inductance L, into one
Step expands output stage bandwidth.
Detailed description of the invention
Fig. 1 is the VCSEL laser driving circuit schematic diagram under the utility model low voltage cmos technique.
Specific embodiment
Technical solutions of the utility model are described in detail with reference to the accompanying drawings and examples.
As shown in Figure 1, the VCSEL laser driving circuit under a kind of low voltage cmos technique of the present embodiment, including two
NMOS tube NM1, NM2, four PMOS tube PM1, PM2, PM3, PM4, two capacitor C1, C2, resistance a R1, an inductance L and
One laser diode VCSEL, the connection type of each component are as follows:
On the one hand the drain electrode that the grid of first NMOS tube NM1 meets the first input voltage vin p, the first NMOS tube NM1 passes through electricity
Resistance R1, inductance L are connected with second source voltage VDD2, on the other hand by first capacitor C1 respectively with the first PMOS tube PM1's
Grid is connected with drain electrode, but also is connected respectively with the grid of third PMOS tube PM3 and drain electrode by the second capacitor C2, the
The source electrode of one NMOS tube NM1 is connected with current source Imod；
The grid of second NMOS tube NM2 connects the drain electrode and the 4th PMOS tube of the second input voltage vin n, the second NMOS tube NM2
The drain electrode of PM4 is connected, and the source electrode of the second NMOS tube NM2 is connected with current source Imod；
The drain electrode of first PMOS tube PM1 is connected with the source electrode of third PMOS tube PM3, and the source electrode of the first PMOS tube PM1 connects
First supply voltage VDD1；
The grid of second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, the drain electrode of the second PMOS tube PM2 with
The source electrode of 4th PMOS tube PM4 is connected, and source electrode meets the first supply voltage VDD1；
The drain electrode of third PMOS tube PM3 is connected with current source Ibias, the grid and the 4th PMOS of third PMOS tube PM3
The grid of pipe PM4 is connected；
The anode of laser diode VCSEL is connect with the drain electrode of the 4th PMOS tube PM4 and the drain electrode of the second NMOS tube NM2,
The minus earth of laser diode VCSEL.
The first supply voltage VDD1 is 3.3V supply voltage in embodiment.
Cascode current source structure is constituted using PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4,
Low voltage cmos technique (such as CMOS 65nm 1.2V core voltage) design, uses 3.3V supply voltage (VDD1 in figure) situation
Under, the three end voltage differences for remaining to ensure each PMOS tube are within 1.2V, under the conditions of avoiding using high-voltage MOS pipe, laser
Device driving circuit is able to use the power supply of 3.3V high power supply voltage, meets the safety requirements of low voltage cmos core metal-oxide-semiconductor.
Obviously, above-described embodiment is merely examples for clearly illustrating the present invention, and is not to this reality
With the restriction of novel embodiment.For those of ordinary skill in the art, drawn according to the spirit of the utility model
The obvious changes or variations of stretching still in the protection scope of the utility model among.
Claims (2)
1. the VCSEL laser driving circuit under a kind of low voltage cmos technique, it is characterised in that: including the first NMOS tube NM1,
Second NMOS tube NM2, the first PMOS tube PM1, the second PMOS tube PM2, third PMOS tube PM3, the 4th PMOS tube PM4, the first electricity
Hold C1, the second capacitor C2, resistance R1, inductance L and laser diode VCSEL；
On the one hand the drain electrode that the grid of the first NMOS tube NM1 meets the first input voltage vin p, the first NMOS tube NM1 passes through electricity
Resistance R1, inductance L are connected with second source voltage VDD2, on the other hand by first capacitor C1 respectively with the first PMOS tube PM1's
Grid is connected with drain electrode, but also is connected respectively with the grid of third PMOS tube PM3 and drain electrode by the second capacitor C2, the
The source electrode of one NMOS tube NM1 is connected with current source Imod；
The grid of the second NMOS tube NM2 connects the drain electrode and the 4th PMOS tube of the second input voltage vin n, the second NMOS tube NM2
The drain electrode of PM4 is connected, and the source electrode of the second NMOS tube NM2 is connected with current source Imod；
The drain electrode of the first PMOS tube PM1 is connected with the source electrode of third PMOS tube PM3, and the source electrode of the first PMOS tube PM1 connects
First supply voltage VDD1；
The grid of the second PMOS tube PM2 is connected with the grid of the first PMOS tube PM1, the drain electrode of the second PMOS tube PM2 with
The source electrode of 4th PMOS tube PM4 is connected, and source electrode meets the first supply voltage VDD1；
The drain electrode of the third PMOS tube PM3 is connected with current source Ibias, the grid and the 4th PMOS of third PMOS tube PM3
The grid of pipe PM4 is connected；
The anode of the laser diode VCSEL is connect with the drain electrode of the 4th PMOS tube PM4 and the drain electrode of the second NMOS tube NM2,
The minus earth of laser diode VCSEL.
2. the VCSEL laser driving circuit under low voltage cmos technique according to claim 1, it is characterised in that: institute
Stating the first supply voltage VDD1 is 3.3V supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822011269.6U CN209150484U (en) | 2018-11-30 | 2018-11-30 | A kind of VCSEL laser driving circuit under low voltage cmos technique |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822011269.6U CN209150484U (en) | 2018-11-30 | 2018-11-30 | A kind of VCSEL laser driving circuit under low voltage cmos technique |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401103A (en) * | 2019-07-26 | 2019-11-01 | 光梓信息科技（上海）有限公司 | Pulse laser driver |
| CN113765081A (en) * | 2021-09-17 | 2021-12-07 | 深圳南云微电子有限公司 | Gate-source voltage protection circuit |
| WO2023032143A1 (en) * | 2021-09-03 | 2023-03-09 | 日本電信電話株式会社 | Dml driver |
| WO2023032144A1 (en) * | 2021-09-03 | 2023-03-09 | 日本電信電話株式会社 | Dml driver |
| WO2024209616A1 (en) * | 2023-04-06 | 2024-10-10 | 日本電信電話株式会社 | Dml driver |
-
2018
- 2018-11-30 CN CN201822011269.6U patent/CN209150484U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401103A (en) * | 2019-07-26 | 2019-11-01 | 光梓信息科技（上海）有限公司 | Pulse laser driver |
| US11581693B2 (en) | 2019-07-26 | 2023-02-14 | Photonic Technologies (Shanghai) Co., Ltd. | Pulsed laser driver |
| WO2023032143A1 (en) * | 2021-09-03 | 2023-03-09 | 日本電信電話株式会社 | Dml driver |
| WO2023032144A1 (en) * | 2021-09-03 | 2023-03-09 | 日本電信電話株式会社 | Dml driver |
| CN113765081A (en) * | 2021-09-17 | 2021-12-07 | 深圳南云微电子有限公司 | Gate-source voltage protection circuit |
| WO2024209616A1 (en) * | 2023-04-06 | 2024-10-10 | 日本電信電話株式会社 | Dml driver |
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