CN209132386U - Scan chain circuitry and grid-control flip-flop circuit - Google Patents

Abstract

A kind of Scan chain circuitry and grid-control flip-flop circuit.Scan chain circuitry includes flip-flop circuit.Flip-flop circuit includes enable end and the output end for being compatible with first and second set-up mode.Under the first set-up mode, enable end is coupled to the first conductive section to receive scanning enable signal, and output end is coupled to combinational logic circuit via the second conductive section, and is coupled to third conductive section via the second conductive section.Under the second set-up mode, enable end via first and the 4th conductive section be coupled to the first input end of grid controlling circuit, third conductive section is coupled to the second input terminal of grid controlling circuit via the 5th conductive section, output end more via second and the 6th conductive section be coupled to the output end of grid controlling circuit.Grid-control flip-flop circuit provided by this case can provide compatible input/output interface, to carry out element exchange in the design phase.In this way, more chip areas and unnecessary power consumption can be saved, and obtain accurate Time-Series analysis.

Description

Scan chain circuitry and grid-control flip-flop circuit

Technical field

This case relates to a kind of Scan chain circuitry and grid-control flip-flop circuit, and in particular to having compatibility The Scan chain circuitry and grid-control flip-flop circuit of the input/output interface of a variety of set-up modes.

Background technique

In integrated circuit testing field, it is subsequent except wrong or detect wrong survey to execute that a fc-specific test FC circuit can be set Examination.However, test circuit quantity also can become together more as circuit element quantity increases.In addition, in order to avoid circuit is being tested During cause excessive immediate current, additional gating logic can be added in test circuit.Based on above-mentioned two reason, such as This, will cause chip area to obviously increase, and may introduce unnecessary extra delay.

Utility model content

To solve the above-mentioned problems, some aspects of this case are to provide a kind of Scan chain circuitry, it includes it is multiple just Anti- device circuit.The multiple flip-flop circuit is concatenated with one another, and to enter a scan pattern according to a scanning enable signal, with One combinational logic circuit is tested, at least flip-flop circuit in the multiple flip-flop circuit is compatible with one comprising one One input/output interface of the first set-up mode and one second set-up mode, and the input/output interface includes an enable end and one Output end.Enable end is to receive the scanning enable signal.Output end is coupled to the combinational logic circuit.In the first setting side Under formula, which is coupled to one first conductive section to receive the scanning enable signal, and the output end is led via one second Electric section is coupled to the combinational logic circuit, and is coupled to a third conductive section via second conductive section.This second Under set-up mode, which also includes an at least grid controlling circuit, at least a flip-flop circuit cooperates with fortune with this Make.Under second set-up mode, which is coupled to the grid-control via first conductive section and one the 4th conductive section One first input end of circuit is to transmit the scanning enable signal to the first input end, and the third conductive section is via one the 5th Conductive section is coupled to one second input terminal of the grid controlling circuit, which more leads via second conductive section with one the 6th Electric section is coupled to an output end of the grid controlling circuit.The third conductive section, the 4th conductive section, the 5th conductive section Implemented in the 6th conductive section each by a first metal layer, and first conductive section and second conductive section are every One is implemented by a second metal layer.

In some embodiments, under second set-up mode, which is not attached to the third conduction region Section.

In some embodiments, first conductive section and position of second conductive section under first set-up mode It is identical to first conductive section and position of second conductive section under second set-up mode.

In some embodiments, which corresponds to one first circuit layout, and second set-up mode is corresponding It is laid out in a second circuit, which all corresponds to one the in first circuit layout and the second circuit cloth intra-office One pattern, second conductive section all correspond to one second pattern in first circuit layout and the second circuit cloth intra-office.

In some embodiments, which includes one and door, a nor gate or a multiplexer.

In some embodiments, the multiple flip-flop circuit each is a D-type flip-flop.

Other aspects of this case are to provide a kind of grid-control flip-flop circuit, have one first set-up mode and one second Set-up mode, the grid-control flip-flop circuit include a flip-flop circuit.Flip-flop circuit to receive a scanning enable signal with One combinational logic circuit is tested.The flip-flop circuit includes an input/output interface, which is compatible with First set-up mode and second set-up mode, and the input/output interface includes an enable end and an output end.Enable end Enable signal is scanned to receive this.Output end is coupled to the combinational logic circuit.Under first set-up mode, the enable end One first conductive section is coupled to receive the scanning enable signal, and the output end is coupled to this via one second conductive section Combinational logic circuit, and a third conductive section is coupled to via second conductive section.Under second set-up mode, the grid Controlling flip-flop also includes a grid controlling circuit, which is coupled to the grid via first conductive section and one the 4th conductive section A first input end of circuit is controlled to transmit the scanning enable signal to the first input end, the third conductive section is via one the Five conductive sections are coupled to one second input terminal of the grid controlling circuit, and the output end is more via second conductive section and one the 6th Conductive section is coupled to an output end of the grid controlling circuit.The third conductive section, the 4th conductive section, the 5th conduction region Section is implemented in the 6th conductive section each by a first metal layer, and first conductive section and second conductive section Each is implemented by a second metal layer.

In conclusion grid-control flip-flop circuit provided by this case can provide compatible input/output interface, to design Stage carries out element exchange.In this way, more chip areas and unnecessary power consumption can be saved, and obtain accurate timing point Analysis.

Detailed description of the invention

For the above and other purpose, feature, advantage and embodiment of this case can be clearer and more comprehensible, the explanation of appended attached drawing It is as follows:

Fig. 1 is a kind of schematic diagram of Scan chain circuitry according to depicted in some embodiments of this case；

Fig. 2 is the schematic diagram of the grid-control flip-flop circuit according to depicted in some embodiments of this case；

Fig. 3 A is the signal according to depicted in some embodiments of this case corresponding to the circuit layout of the flip-flop circuit of Fig. 1 Figure；

Fig. 3 B is the showing corresponding to the circuit layout of the grid-control flip-flop circuit of Fig. 2 according to depicted in some embodiments of this case It is intended to；

Fig. 4 A is the solid for corresponding to the rightmost side part of circuit layout in Fig. 3 A according to depicted in some embodiments of this case Schematic diagram；

Fig. 4 B is the solid for corresponding to the rightmost side part of circuit layout in Fig. 3 B according to depicted in some embodiments of this case Schematic diagram；

Fig. 5 is a kind of schematic diagram of test macro according to depicted in some embodiments of this case；

Fig. 6 is a kind of schematic diagram of test method according to depicted in some embodiments of this case；

Fig. 7 is according to the drawn preset condition of some embodiments of this case be design rule check conceptual schematic view；With And

Fig. 8 is according to the drawn preset condition of some embodiments of this case be timing requirements conceptual schematic view.

Specific embodiment

All vocabulary used herein have its common meaning.Above-mentioned vocabulary is determined in universal common dictionary Justice should not be limited to and originally take off comprising the merely illustrative using example of any vocabulary discussed in this in the content of this specification Show the range and meaning of content.Similarly, this disclosure is also not only limited with the various embodiments shown by this specification.

Herein, using the vocabulary of first, second and third etc., be used to describe various elements, component, region, Layer and/or block be it is understood that.But these elements, component, region, layer and/or block should not be by these terms It is limited.These vocabulary are only limited to for distinguishing single element, component, region, layer and/or block.Therefore, one hereinafter First element, component, region, layer and/or block are also referred to as second element, component, region, layer and/or block, without de- Original idea from this case.Used herein " and/or " include any one of one or more associated projects and all Combination.

About " coupling " used herein or " connection ", can refer to two or multiple element mutually directly make entity or electricity Property contact, or mutually put into effect indirectly body or in electrical contact, be also referred to as two or multiple element mutual operation or movement.

In this article, term " circuit system (circuitry) " refers to is formed comprising one or more circuits (circuit) Triangular web.Term " circuit ", which refers to, to be connected by one or more transistors and/or one or more main passive devices by certain way It connects to handle the object of signal.

Referring to Fig.1, Fig. 1 is a kind of scan chain (scan chain) circuit system according to depicted in some embodiments of this case The schematic diagram of system 100.In some embodiments, Scan chain circuitry 100 may be implemented in integrated circuit (or chip), with benefit Carry out subsequent test (such as Time-Series analysis etc.).

Scan chain circuitry 100 includes the flip-flop circuit 120 and combinational logic circuit 140 of multiple concatenations.Yu Yi In a little embodiments, flip-flop circuit 120 can be D-type flip-flop, but this case is not limited thereto.Various types of flip-flop circuits 120 be all the range that this case is covered.In some embodiments, combinational logic circuit 140 can be one or more numbers to be measured The set of (or logic) circuit.

Flip-flop circuit 120 each includes first input end SI, the second input terminal D, enable end EN, the first output end SO And second output terminal Q, wherein the enable end EN of each flip-flop circuit 120 is to receive scanning enable signal SEN.First The first input end SI of a flip-flop circuit 120 is to receive scan input signal SIN, and first flip-flop circuit 120 First output end SO is coupled to the first input end SI of second flip-flop circuit 120.The rest may be inferred, the last one flip-flop electricity The first output end SO on road 120 is to export Scan out SOUT.

Furthermore the second input terminal D and second output terminal Q of each flip-flop circuit 120 are coupled to combinational logic electricity A corresponding I/O node inside road 140, (is not drawn with receiving/exporting main (primary) input/output signal respectively Show).When receiving the scanning enable signal SEN of tool particular logic value (for example, logical value 0), multiple 120 quilts of flip-flop circuit Enable and enter scan pattern.In scan pattern, the operation of multiple flip-flop circuits 120 is similar to shift registor, and root Scan out SOUT is generated according to scan input signal SIN.For equivalent, when operating in scan pattern, each flip-flop Circuit 120 is exported by signal latch received by its first input end SI and via the first output end SO.In other words, in scanning Under mode, Scan out SOUT will be determined by scan input signal SIN, and not influenced by combinational logic circuit 140.Such as This can be by detecting the signal value variation of Scan out SOUT come really in the subsequent testing operation after scan pattern Recognize whether combinational logic circuit 140 defective or failure.

It is the schematic diagram of the grid-control flip-flop circuit 200 according to depicted in some embodiments of this case referring to Fig. 2, Fig. 2.It is easy Similar component in understanding, FIG. 1 to FIG. 2 will be designated as identical label.

As it was earlier mentioned, combinational logic circuit 140 does not influence Scan out SOUT under scan pattern.Therefore, group Switching of the combinational logic circuit 140 under scan pattern will cause unnecessary power consumption, and its switching may introduce excessive wink Between electric current and cause the pressure drop on route.In some embodiments, flip-flop circuit 120 in Fig. 1 each can more arrange in pairs or groups one Grid-control (gated) circuit 124.In some embodiments, grid controlling circuit 124 can be with 120 Collaboration of flip-flop circuit in Fig. 1 For a grid-control flip-flop circuit 200, switched with avoiding combinational logic circuit 140 to generate in scanning-mode it.In this way, can reduce State unnecessary power consumption and pressure drop.In different embodiments, grid controlling circuit 124 can by with the logics such as door, nor gate or multiplexer Circuit is implemented, but this case is not limited thereto.Various types of grid controlling circuits 124 are all the range that this case is covered.To be easy to Understand, following paragraphs content illustrates for door.

In this example, grid controlling circuit 124 includes first input end A1, the second input terminal A2 and output end Z.First input End A1 is coupled to the enable end EN of flip-flop circuit 120, scans enable signal SEN to receive.Second input terminal A2 is connected to positive and negative The second output terminal Q of device circuit 120, and output end Z is coupled to the internal node of combinational logic circuit 140.In other words, grid-control electricity Road 124 is coupled between combinational logic circuit 140 and flip-flop circuit 120.For equivalent, grid-control flip-flop circuit 200 it is defeated Outlet Z replaces the second output terminal Q of flip-flop circuit 120 to be connected to combinational logic circuit 140.As it was earlier mentioned, when entering When scan pattern, scanning enable signal SEN has particular logic value (for example, logical value 0).In under this condition, grid controlling circuit 124 will be maintained at fixed current potential (for example, current potential of counterlogic value 0) by the signal that output end Z is exported, not change Become the switching of combinational logic circuit 140.It is generated in this way, can avoid operation of the combinational logic circuit 140 under scan pattern Unnecessary power consumption.

It is according to depicted in some embodiments of this case corresponding to Fig. 1's referring to Fig. 3 A~Fig. 3 B and Fig. 4 A~Fig. 4 B, Fig. 3 A The schematic diagram of the circuit layout 300A of flip-flop circuit 120, Fig. 3 B are according to depicted in some embodiments of this case corresponding to Fig. 2's The schematic diagram of the circuit layout 300B of grid-control flip-flop circuit 200, Fig. 4 A are to be corresponded to according to depicted in some embodiments of this case The stereoscopic schematic diagram of the rightmost side part of circuit layout 300A in Fig. 3 A, and Fig. 4 B is right according to depicted in some embodiments of this case Should in Fig. 3 B the rightmost side part of circuit layout 300B stereoscopic schematic diagram.For it can be readily appreciated that above-mentioned each attached drawing and Fig. 1~figure Similar component in 2 will be designated as identical label.

In some embodiments, first set-up mode of the circuit layout 300A corresponding to the flip-flop circuit 120 of Fig. 1, and Second set-up mode of the circuit layout 300B corresponding to the grid-control flip-flop circuit 200 of Fig. 2.Fig. 3 A~Fig. 3 B and Fig. 4 A~Fig. 4 B For example to illustrate related set-up mode.It should be appreciated that be to be clearly understood that related set-up mode, Fig. 3 A~Fig. 3 B and Fig. 4 A~ The position of main input/output terminal is listed in Fig. 4 B, and does not list all internal connecting layers, semiconductor layer or internal brilliant in detail The relevant entire infrastructure of body pipe etc. details.Under the spirit and scope for not departing from this case, Fig. 3 A~Fig. 3 B and Fig. 4 A~Fig. 4 B Shown in set-up mode can be adjusted according to process requirement and/or design code, replace with change.

In some embodiments, grid-control flip-flop circuit 200 is arranged with flip-flop circuit 120 with defeated with compatible input Outgoing interface (such as: the first output end SO, enable end EN and output end Z (or second output terminal Q) etc.).For example, when being applied to When flip-flop circuit 120, as shown in Figure 3A, circuit layout 300A includes pattern 310-1, pattern 320-1A~320-1D, pattern 330-1, pattern 340-1, pattern 350-1 and pattern 360-1.Pattern 310-1 corresponds to the multiple crystalline substances for implementing flip-flop circuit 120 The grid of body pipe, and can be implemented by polysilicon (poly-silicon) layer PO.Pattern 320-1A~320-1D corresponds to flip-flop The multiple input terminals or output end of circuit 120, and can be implemented by second metal layer M2.For example, pattern 320-1A corresponds to enable EN, pattern 320-1B is held to correspond to the first output end SO, pattern 320-1C corresponds to second output terminal Q, and pattern 320-1D is used In extension pattern 320-1C.Pattern 330-1 is used to define the correspondence active area of aforesaid plurality of transistor, can be expanded by oxide (Oxide diffusion, OD) layer OD is dissipated to implement.

Pattern 340-1 can be implemented by the first metal layer M1, be used for the internal connecting layer as flip-flop circuit 120.It should Understand, in some embodiments, the above-mentioned each pattern implemented by the first metal layer M1 or second metal layer M2 is specific to tie Structure can be considered a conductive section.For example, saved together referring to the inside for corresponding to flip-flop circuit 120 Fig. 4 A, pattern 340-1 Point (not being painted) setting, to connect out second output terminal Q.

Furthermore pattern 350-1 can be implemented by contacting (contact), be used to be electrically connected metal layer and polysilicon layer or Active area.For example, the both ends setting of pattern 340-1 above-mentioned is respectively corresponded referring to Fig. 4 A, multiple pattern 350-1 together, with Couple the internal node of the first metal layer M1 corresponding to pattern 340-1 to flip-flop circuit 120.

Pattern 360-1 can be implemented by through-hole (VIA), be used to be electrically connected metal layer.For example, together referring to Fig. 4 A, figure The both ends of case 320-1C are respectively arranged with a pattern 360-1.In this way, the corresponding second metal layer M2 of pattern 320-1C can be via The corresponding through-hole of pattern 360-1 is mutually coupled with the first metal layer M1 corresponding to lower section pattern 340, using as second output terminal Q。

As shown in Figure 3B, when being applied to grid-control flip-flop circuit 200, compared to circuit layout 300A, circuit layout 300B also include multiple pattern 310-2, pattern 330-2, pattern 340-2A~340-2E, pattern 350-2 and pattern 360-2A~ 360-2B。

Pattern 310-2 corresponds to the grid of multiple transistors in grid controlling circuit 124, and can be implemented by polysilicon layer PO.Figure Case 330-2 is used to define the correspondence active area of aforesaid plurality of transistor, can be implemented by oxide diffusion layer OD.Pattern 340- 2A~340-2E corresponds to the multiple input terminals or output end and its interconnector layer of grid controlling circuit 124, and can be by the first gold medal Belong to layer M1 to implement.For example, pattern 340-2A corresponds to first input end A1, pattern 340-2B corresponds to the second input terminal A2, figure Case 340-2C corresponds to output end Z, and pattern 340-2D corresponds to internal connecting layer to realize the interconnector of grid controlling circuit 124, and Pattern 340-2E is for extending pattern 340-2C.

Pattern 350-2 can be implemented by contacting (contact), be used to be electrically connected the first metal layer M1 to grid (i.e. pair Should be in the position of polysilicon layer PO) or source/drain (position for corresponding to oxide diffusion layer OD).For example, multiple patterns 350-2 respectively corresponds the endpoint setting of pattern 340-2A~340-2D above-mentioned, right to couple pattern 340-2A~340-2D institute The first metal layer M1 answered to grid controlling circuit 124 internal node (grid or source/drain).

Pattern 360-2A and 360-2B can be implemented by VIA, be used to be electrically connected metal layer.For example, together referring to Fig. 4 B, Compared to Fig. 4 A, the corresponding through-hole of pattern 360-1 is removed, therefore second metal layer M2 corresponding to pattern 320-1C is not attached to The first metal layer M1 corresponding to lower section pattern 340.Pattern 360-2A is set between pattern 340-2E and pattern 320-1D, and Pattern 360-2B is set between pattern 340-2A and pattern 320-1A.In this way, the corresponding the first metal layer M1 of pattern 340-2E It can be coupled via second metal layer M2 corresponding to the corresponding through-hole of pattern 360-2A and pattern 320-1D.Pass through this setting side Formula, the output end Q of the compatible flip-flop circuit 120 of output end corresponding to pattern 320-1C or grid-control flip-flop circuit 200 Output end Z.In addition, the first metal layer M1 corresponding to pattern 340-2A can be via the corresponding through-hole of pattern 360-2B and pattern The coupling of second metal layer M2 corresponding to 320-1A.For equivalent, as shown in previous Fig. 2, first input end A1 be may be coupled to just The enable end EN of anti-device circuit 120.

According to the set-up mode of above-mentioned Fig. 4 A~Fig. 4 B, it is possible to find multiple pattern 320-1A corresponding to second metal layer M2 The position of input terminal defined in~320-1D or output end circuit layout 300A and second corresponding to the first set-up mode It is all identical, therefore compatible in flip-flop circuit 120 and grid-control flip-flop electricity in circuit layout 300B corresponding to set-up mode Road 200.In this way, in some embodiments, when executing test method (method 600 as be described hereinafter), flip-flop circuit 120 with Grid-control flip-flop circuit 200 can be directly substituted for one another.

It is a kind of signal of test macro 500 according to depicted in some embodiments of this case referring to Fig. 5 and Fig. 6, Fig. 5 Figure, and Fig. 6 is a kind of schematic diagram of test method 600 according to depicted in some embodiments of this case.For it can be readily appreciated that test Method 600 illustrates the operation referring to test macro 500 together.

Test macro 500 includes processor 510, memory body 520 and multiple input/output (Input/Output, I/O) Interface 530.Processor 510 is coupled to memory body 520 and multiple I/O interfaces 530.In each embodiment, processor 510 is Central processing unit (CPU), special application integrated circuit (Application-specific integrated circuit, ASIC), multiprocessor, distributed processing system or suitable processing unit.For implement processor 510 various circuits or Unit is all the range that this case is covered.

Memory body 520 stores one or more procedure codes, to Computer Aided Design integrated circuit.For example, memory Body 520 stores a procedure code, and for this procedure code to form coded by multiple instruction collection, plurality of instruction set is used to check multiple collection At multiple layout patterns in circuit, or integrated circuit is tested.In some embodiments, the executable storage of processor 510 It is stored in the procedure code of memory body 520, and the operation of test method 600 can be automatically performed.

In some embodiments, memory body 520 is that storage medium can be read in non-transient computer, has (that is, storage) Multiple codings to the multiple instruction collection tested chip.For example, memory body 520 is stored to execute test Multiple executable instructions of method 600.In some embodiments, computer-readable storage medium be electrical property, magnetism, optics, Infrared ray and/or semiconductor system (or device).For example, computer-readable storage medium includes semiconductor or solid-state Memory body, tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disc with/ Or optical disc.In one or more embodiments using optical disc, computer-readable storage medium includes read-only note Recall CD (CD-ROM), repeatable record writing optical disk (CD-R/W) and/or digital image and sound optical disk (DVD).

Multiple I/O interfaces 530 receive multiple inputs or order from various control devices, and wherein control device can be set by circuit Meter person or Test Engineer's manipulation.Accordingly, test macro 500 can be steered by the input or order of multiple I/O interfaces 530.In In some embodiments, multiple I/O interfaces 530 include a screen, and setting is to show the state of procedure code execution and/or show electricity Road layout.In some embodiments, multiple I/O interfaces 530 include graphic user interface (GUI).In other embodiments, Multiple I/O interfaces 530 include keyboard, numeric keypad, mouse, trace ball, Touch Screen, cursor direction keys or its above-mentioned group It closes, to link up information and multiple orders to processor 510.

Illustrate the relevant operation of test method 600 below.In operation S610, the netlist of the internal circuit of instruction chip is received (netlist) file.

For example, wherein data D1 can as shown in figure 5, I/O interface 530 can receive data D1 and be stored in memory body 520 For the net meter file for describing inner wafer circuit.For example, net meter file can be used to describe the Scan chain circuitry of Fig. 1 100 and chip in other circuits.In some embodiments, circuit designers can be by describing scan chain electricity in net meter file Road system 100, flip-flop circuit 120 and grid-control flip-flop circuit 200 are designed.In some embodiments, netlist text The content of part meets the grammer of a predefined type, this grammer can be recorded with the descriptor format that can be tested the identification of test system 500.One In a little embodiments, net meter file is gate leve (gate-level) net meter file.In some embodiments, the predetermined class of net meter file Type can be hardware description language (Verilog) or VHSIC hardware description language (veryhigh-speed hardware description language,VHDL).The type of above-mentioned grammer is used for example, and this case is not limited thereto.

In operation S620, according to net meter file execution put with coiling (place and route) program, to generate a cloth Office data D2.

For example, memory body 520 stores the software of a design tool or cad tools, processor 510 can This software is executed, to execute automatic putting according to data D1 and around sequence of threads.In this way, processor 510 can be according to corresponding to data Circuit indicated by the net meter file of D1, and automatically put corresponding circuit element and between line, it is corresponding to generate Topology data D2.

In operation S630, flip-flop circuit 120 is replaced with by grid-control flip-flop circuit 200 according to topology data D2.

In some embodiments, processor 510 can decide whether incite somebody to action according to topology data D2 and an at least preset condition Flip-flop circuit 120 replaces with grid-control flip-flop circuit 200.

Referring to Fig. 7, it is design rule check (design that Fig. 7, which is drawn preset condition by some embodiments according to this case, Rule check, DRC) conceptual schematic view.By taking Fig. 7 as an example, preset condition above-mentioned is that need to meet the requirement of DRC.DRC is to use In ensuring that circuit layout can meet parameter provided by manufacturer, to promote the yield and stability of chip.In practical application, The cloth intra-office of chip has multiple circuit elements, and circuit element need each other it is spaced apart, to meet wanting for DRC It asks.For example, as shown in fig. 7, pattern 700 is used to define the element of low critical voltage, the wherein circuit of pattern 700 and Fig. 3 A It is laid out the distance between 300A and is greater than a pre-determined distance PD.In under this condition, processor 510 can determine that the requirement for meeting DRC.It connects , if the circuit layout 300A of Fig. 3 B, which is replaced with circuit layout 300B, (it is positive and negative also to replace with grid-control for flip-flop circuit 120 Device circuit 200), the distance between pattern 700 and circuit layout 300B will be less than pre-determined distance PD.Accordingly, processor 510 determines The requirement of DRC is not met, therefore determines circuit layout 300A not to be replaced with circuit layout 300B.Conversely, if pattern 700 and circuit It is laid out the distance between 300B and is greater than or equal to pre-determined distance PD, processor 510 determines the requirement for meeting DRC, therefore determining will be electric Road layout 300A replaces with circuit layout 300B.

It is above-mentioned only to illustrate for defining the element of low critical voltage, but this case is not limited thereto.In different embodiments In, processor 510 can be confirmed whether the requirement of DRC according to circuit layout to all elements, to complete operation S630.

Alternatively, referring to Fig. 8, Fig. 8 is according to the drawn preset condition of some embodiments of this case be timing requirements concept Schematic diagram.By taking Fig. 8 as an example, preset condition above-mentioned is that need to meet timing requirements.In some embodiments, processor 510 can be first Circuit layout 300A is replaced with into circuit layout 300B, and execute static timing analysis (Static Timing Analysis, The test programs such as STA), to confirm whether replaced circuit layout 300B meets timing requirements.For example, as shown in figure 8, replacing It is changed to after circuit layout 300B (after replacing with grid-control flip-flop circuit 200), STA program can be performed to analyze in processor 510 Well-to-do (slack) of maximum delay time Tdelay and Scan chain circuitry 100 caused by grid-control flip-flop circuit 200 Time Tslack.In some embodiments, the data that STA program acquisition Scan chain circuitry 100 can be performed in processor 510 are supported Up to time Tarrival and data preparation time Trequired, and the difference by calculating above-mentioned two time obtain it is well-to-do Time Tslack.If well-to-do time Tslack is greater than or equal to this delay time Tdelay, processor 510 be can determine that when meeting Sequence requirement, and determine that replacement circuit layout 300A is circuit layout 300B.Conversely, if when the well-to-do time is greater than or equal to this delay Between Tdelay, then processor 510, which can determine that, meets timing requirements, and determine replacement circuit layout 300A be circuit layout 300B.

New circuit layout is generated, and execute follow-up test process in operation S640 with continued reference to Fig. 6.

For example, one or more flip-flop circuits 120 are processor 510 after grid-control flip-flop circuit 200 in replacement chip New circuit layout be can produce as data D3 and to store to memory body 520.Then, processor 510 can be held according to data D3 The design of row subsequent placement and/or testing process, such as comprising insertion decoupling capacitance, Time-Series analysis, sweep test etc., with true Whether correct recognize chip running.

In it is some in the related technology, when carrying out wafer sort, part or all of flip-flop in net meter file electricity Road can directly be replaced by the flip-flop circuit with grid-control function, then arrange automatically and the programs such as wiring.In this way, The area of chip entirety will obviously increase.

Compared to above-mentioned technology, by the way that the flip-flop circuit 120 with compatible input/output interface and grid-control is arranged Some embodiments of flip-flop circuit 200, this case can be after the programs such as automatic arrangement and wiring (i.e. operation S620), further according to pre- If condition (may be, for example, DRC, Time-Series analysis etc. requirement) is to determine whether replace with grid-control flip-flop circuit 200.Whereby, may be used Grid-control flip-flop circuit 200 is replaced according to the remaining area after wiring, therefore not will increase additional areas.In this way, chip Area can remain original compared with small area, and unnecessary function caused by reducing combinational logic circuit 140 simultaneously under scan pattern Consumption.Simultaneously as some embodiments of this case are to decide whether to replace flip-flop circuit after the programs such as automatic arrangement and wiring 120, the actual wire extra delay introduced with additional circuit part (for example, grid controlling circuit 124) can be considered together. In this way, accurate critical path can be obtained in simulation of the rear layout (post-layout) in the stage.

In conclusion test macro, method provided by this case can be defeated by compatible input with grid-control flip-flop circuit Outgoing interface carries out element exchange in the design phase.In this way, more chip areas and unnecessary power consumption can be saved, and obtain calibrated True Time-Series analysis.

Although this case is disclosed above with embodiment, so itself and non-limiting this case is any to be familiar with this those skilled in the art, is not taking off From in the spirit and scope of this case, when can be used for a variety of modifications and variations, therefore the right that the protection scope of this case is appended when view Subject to the range that claim is defined.

Claims (10)

1. a kind of Scan chain circuitry, characterized by comprising:

Multiple flip-flop circuits, the multiple flip-flop circuit is concatenated with one another, and to enter one according to a scanning enable signal Scan pattern, at least flip-flop circuit packet to test a combinational logic circuit, in the multiple flip-flop circuit The input/output interface for being compatible with one first set-up mode and one second set-up mode containing one, and the input/output interface packet Contain:

One enable end, to receive the scanning enable signal；And

One output end is coupled to the combinational logic circuit,

Wherein under first set-up mode, which is coupled to one first conductive section to receive the scanning enable signal, And the output end is coupled to the combinational logic circuit via one second conductive section, and is coupled to one via second conductive section Third conductive section,

Wherein under second set-up mode, which also includes an at least grid controlling circuit, with this at least one Flip-flop circuit Collaboration, under second set-up mode, the enable end is conductive via first conductive section and one the 4th Section is coupled to a first input end of the grid controlling circuit to transmit the scanning enable signal to the first input end, which leads Electric section is coupled to one second input terminal of the grid controlling circuit via one the 5th conductive section, which more second leads via this Electric section and one the 6th conductive section are coupled to an output end of the grid controlling circuit,

Wherein in the third conductive section, the 4th conductive section, the 5th conductive section and the 6th conductive section each Implemented by a first metal layer, and first conductive section and second conductive section each are implemented by a second metal layer.

2. Scan chain circuitry according to claim 1, which is characterized in that under second set-up mode, this second Conductive section is not attached to the third conductive section.

3. Scan chain circuitry according to claim 1, which is characterized in that first conductive section and second conduction Position of the section under first set-up mode is identical to first conductive section and second conductive section in second setting Position under mode.

4. Scan chain circuitry according to any one of claims 1 to 3, which is characterized in that first set-up mode pair The first circuit layout of Ying Yuyi, second set-up mode corresponding to a second circuit be laid out, first conductive section this first Circuit layout and the second circuit cloth intra-office all correspond to one first pattern, second conductive section first circuit layout with The second circuit cloth intra-office all corresponds to one second pattern.

5. Scan chain circuitry according to claim 1, which is characterized in that the grid controlling circuit include one with door, one or NOT gate or a multiplexer.

6. Scan chain circuitry according to claim 1, which is characterized in that the multiple flip-flop circuit each is One D-type flip-flop.

7. a kind of grid-control flip-flop circuit, which is characterized in that the grid-control flip-flop circuit has one first set-up mode and one the Two set-up modes, and the grid-control flip-flop circuit includes:

One flip-flop circuit, to receive a scanning enable signal to test a combinational logic circuit, the flip-flop is electric Road includes an input/output interface, which is compatible with first set-up mode and second set-up mode, and should Input/output interface includes:

One enable end scans enable signal to receive this；And

One output end is coupled to the combinational logic circuit,

Wherein under first set-up mode, which is coupled to one first conductive section to receive the scanning enable signal, And the output end is coupled to the combinational logic circuit via one second conductive section, and is coupled to one via second conductive section Third conductive section,

Wherein under second set-up mode, which also includes a grid controlling circuit, which first leads via this Electric section and one the 4th conductive section are coupled to a first input end of the grid controlling circuit to transmit the scanning enable signal and extremely should First input end, the third conductive section are coupled to one second input terminal of the grid controlling circuit via one the 5th conductive section, should Output end is more coupled to an output end of the grid controlling circuit via second conductive section and one the 6th conductive section,

Wherein in the third conductive section, the 4th conductive section, the 5th conductive section and the 6th conductive section each Implemented by a first metal layer, and first conductive section and second conductive section each are implemented by a second metal layer.

8. grid-control flip-flop circuit according to claim 7, which is characterized in that under second set-up mode, this second Conductive section is not attached to the third conductive section.

9. grid-control flip-flop circuit according to claim 7, which is characterized in that first conductive section and second conduction Position of the section under first set-up mode is identical to first conductive section and second conductive section in second setting Position under mode.

10. grid-control flip-flop circuit according to any one of claims 7 to 9, which is characterized in that first set-up mode pair The first circuit layout of Ying Yuyi, second set-up mode corresponding to a second circuit be laid out, first conductive section this first Circuit layout and the second circuit cloth intra-office all correspond to one first pattern, second conductive section first circuit layout with The second circuit cloth intra-office all corresponds to one second pattern.