CN209120150U

CN209120150U - D type flip flop control circuit and d type flip flop

Info

Publication number: CN209120150U
Application number: CN201821720175.XU
Authority: CN
Inventors: 范习安
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-10-22
Filing date: 2018-10-22
Publication date: 2019-07-16
Anticipated expiration: 2028-10-22

Abstract

The utility model discloses a kind of d type flip flop control circuit and d type flip flops, are related to technical field of integrated circuits.The d type flip flop control circuit includes that first control signal generates unit, second control signal generates unit and switch element；The control terminal of output end and switch element that first control signal generates unit connects；The first end of output end and switch element that second control signal generates unit connects；The second end of switch element is connect with latch cicuit.The d type flip flop control circuit of the disclosure not only may be implemented d type flip flop and reset d type flip flop may be implemented again to set 1, and be not necessarily to carry out circuit structure more change.

Description

D type flip flop control circuit and d type flip flop

Technical field

This disclosure relates to technical field of integrated circuits, in particular to a kind of d type flip flop control circuit and d type flip flop.

Background technique

Trigger affects the properties of system as component part important in digital display circuit, as area, power consumption, Speed etc..D type flip flop is one of most common trigger, is played an important role in integrated circuit design.

For the set and reset of d type flip flop, currently, generalling use the mode of PMOS tube pull-up and/or NMOS tube drop-down. Specifically, the control effect for being only able to achieve d type flip flop is to set 1 in the scene of PMOS tube pull-up；In the scene of NMOS tube drop-down In, it is able to achieve the control effect of d type flip flop only to reset.The control effect for setting 1 is reset but also has if making circuit not only and having, It needs to carry out upper pulling process using PMOS tube simultaneously and carries out pulling operation using NMOS tube.However, in this case, using Two metal-oxide-semiconductors, increase chip area.

It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.

Utility model content

The disclosure is designed to provide a kind of d type flip flop control circuit and d type flip flop, and then at least to a certain extent It can not preferably be realized caused by overcoming the limitation and defect due to the relevant technologies while there is the D touching for resetting and setting 1 function Send out device.

According to one aspect of the disclosure, a kind of d type flip flop control circuit is provided, d type flip flop control circuit includes first Control signal generation unit, second control signal generates unit and switch element；The output end of first control signal generation unit It is connect with the control terminal of switch element；The first end of output end and switch element that second control signal generates unit connects；It opens The second end for closing element is connect with latch cicuit.

In a kind of exemplary embodiment of the disclosure, switch element includes NMOS tube.

In a kind of exemplary embodiment of the disclosure, when first control signal generates unit output high level, if Second control signal is high level, and NMOS tube is opened, then d type flip flop sets 1；If second control signal is low level, D triggering Device is reset.

According to one aspect of the disclosure, a kind of d type flip flop, including above-mentioned d type flip flop control circuit are provided.

In a kind of exemplary embodiment of the disclosure, latch cicuit includes the first latch units and the second latch units； Wherein, the second end of switch element is connected between the first latch units and the second latch units.

In the technical solution provided by some embodiments of the present disclosure, believe one end of switch element as the second control Number input terminal, on the one hand, in the case where first control signal is enabled, can determine that D is triggered according to second control signal The control effect of device；On the other hand, second control signal can be preset, to achieve the purpose that default control effect；Another aspect, Compared to the scheme that the relevant technologies use two metal-oxide-semiconductors, the scheme of the disclosure can reduce chip area；In another aspect, this public affairs The controling circuit structure opened is simple, can use the control circuit and carries out complicated Logic Circuit Design, to meet different need It asks.

It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not The disclosure can be limited.

Detailed description of the invention

The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure Some embodiments for those of ordinary skill in the art without creative efforts, can also basis These attached drawings obtain other attached drawings.In the accompanying drawings:

Fig. 1 diagrammatically illustrates the structure chart of the d type flip flop of the relevant technologies；

Fig. 2 shows a kind of schematic diagrames of reseting module in the related technology；

Fig. 3 shows a kind of schematic diagram of set module in the related technology；

Fig. 4 shows the schematic diagram of control module according to the exemplary embodiment of the disclosure；

Fig. 5 diagrammatically illustrates the structure chart of d type flip flop according to the exemplary embodiment of the disclosure.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can Omitted with technical solution of the disclosure it is one or more in the specific detail, or can be using other groups Member, device etc..In other cases, known solution is not shown in detail or describes to avoid a presumptuous guest usurps the role of the host and makes the disclosure Various aspects thicken.

In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure Note indicates same or similar part, thus will omit repetition thereof.It should be understood that art described in the disclosure Language " first ", " second ", " third " are merely to the purpose distinguished, should not become the limitation of the disclosure.

D type flip flop can be set by clock edge (rising edge or failing edge) latch data (0 or 1) in integrated circuit It is had a wide range of applications in meter.Table 1 shows the pin (PIN) and corresponding function that current d type flip flop may include.

Table 1

With reference to Fig. 1, d type flip flop can be made of two-stage latch cicuit and reset/set module 11.Two-stage latch cicuit is such as First latch units 12 and the second latch units 13 shown in Fig. 1, latch cicuit can latch this data input of input Signal and the data input for saving last time are used for circuit output result.Reset/set module 11 can divide according to control effect The case where for clearing, set postposition 1 after reset and simultaneous with reset and set.

With reference to Fig. 2, the reset/set module 11 reset after reset may include connecing NMOS tube, when RESET is enabled When, the source electrode of NMOS tube connects VSS low side, and in this case, d type flip flop is reset.

With reference to Fig. 3, the reset/set module 11 of set postposition 1 may include that PMOS tube is connect on one, when SET is enabled, The source electrode of PMOS connects VDD power end, and in this case, d type flip flop sets 1.

Furthermore it is possible to by realizing d type flip flop simultaneous with resetting and set 1 at present connecing NMOS tube and above meeting PMOS Function.However, this mode has used two metal-oxide-semiconductors, chip area is increased.

In consideration of it, the d type flip flop control circuit may include first present disclose provides a kind of d type flip flop control circuit Control signal generation unit, second control signal generates unit and switch element.The features such as strong in view of NMOS tube driving capability, In the illustrative embodiments of the disclosure, switch element described in the disclosure can be realized using NMOS tube.However, should Understand, those skilled in the art can also substitute NMOS using other devices of such as PMOS tube according to the design of the disclosure Pipe realizes switch element, this all should belong to the protection scope of the disclosure.

It is illustrated below in conjunction with d type flip flop control circuit of the Fig. 4 to the disclosure.

With reference to Fig. 4, the output end that first control signal generates unit 42 can be connect with the control terminal of switch element 41；The The output end of two control signal generation units 43 can be connect with the first end of switch element 41.In addition, the second of switch element End can be connect with the latch cicuit for including in d type flip flop.

First control signal generates unit 42 and second control signal generates unit 43 and can respond other trigger signals point Not Chan Sheng first control signal and second control signal, to control switch element 41 or even d type flip flop.Specifically, producing The process of raw first control signal and second control signal is similar with generation RESET signal and SET signal in the related technology, this public affairs Open that there is no special restriction on this.

In addition, first control signal generates unit 42 and second control signal generates unit 43 and can be deployed in same control In chip, their output end can be respectively two output pins of the control chip, that is to say, that be based on different application field The logic rules of scape, which can export two control signals, with the working condition for controlling d type flip flop.

It will be readily appreciated by those skilled in the art that first control signal generates according to the real work scene of d type flip flop Unit 42 and second control signal generate the first control signal that unit 43 generates respectively and second control signal may equal not phases Together.

According to some embodiments of the present disclosure, first control signal generation unit 42 can be to be generated in the related technology The unit of RESET signal, that is to say, that in some examples of the disclosure, first control signal be can be in the related technology RESET signal.In this case, only change switch element one end input, can be realized d type flip flop and meanwhile have clearing with Set 1 function.

Still referring to FIG. 4, when first control signal generates the generation of unit 42 and the first control signal exported is high level, Switch element 41 is opened, in this case, if second control signal generates the second control letter that unit 43 is generated and exported It number is high level, then the high level signal can control d type flip flop via switch element 41 and set 1, to realize as in the related technology Set effect；If second control signal is low level, which can control D triggering via switch element 41 Device is reset, to realize such as clearing effect in the related technology.

D type flip flop control circuit according to an exemplary embodiment of the present disclosure, using one end of switch element as second Control the input terminal of signal, on the one hand, in the case where first control signal is enabled, can determine according to second control signal The control effect of d type flip flop；On the other hand, second control signal can be preset, to achieve the purpose that default control effect；It is another Aspect, compared to the scheme that the relevant technologies use two metal-oxide-semiconductors, the scheme of the disclosure can reduce chip area；In another aspect, The controling circuit structure of the disclosure is simple, can use the control circuit and carries out complicated Logic Circuit Design, to meet difference Demand.

Further, a kind of d type flip flop is additionally provided in this example embodiment.

With reference to Fig. 5, the d type flip flop of the disclosure may include for realizing the control circuit with set is resetted.Specifically, such as Upper described, which may include switch element 41, first control signal generates unit 42 and second control signal generates Unit 43.Wherein, which can be NMOS tube.Specific description illustrates phase with d type flip flop control circuit above Together, details are not described herein.

In addition, d type flip flop can also include the first latch units 12 and the second latch units 13, the disclosure is to latch units Type do not do specifically limited, those skilled in the art are easy to directly determine out the structure of disclosure latch units.

When first control signal generates the generation of unit 42 and the first control signal exported is high level, switch element 41 It opens, in this case, if second control signal generates, unit 43 is generated and the second control signal exported is high level, Then the high level signal can control d type flip flop via switch element 41 and set 1, to realize such as set effect in the related technology； If second control signal is low level, which can control d type flip flop via switch element 41 and reset, with reality Now such as clearing effect in the related technology.

D type flip flop according to an exemplary embodiment of the present disclosure, using one end of switch element as second control signal Input terminal, on the one hand, in the case where first control signal is enabled, d type flip flop can be determined according to second control signal Control effect；On the other hand, second control signal can be preset, to achieve the purpose that default control effect；In another aspect, this Disclosed controling circuit structure is simple, can use the control circuit and carries out complicated Logic Circuit Design, different to meet Demand.

Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes Or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in often Knowledge or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by right It is required that pointing out.

It should be understood that the present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and And various modifications and changes may be made without departing from the scope thereof.The scope of the present disclosure is only limited by the attached claims.

Claims

1. a kind of d type flip flop control circuit, which is characterized in that the d type flip flop control circuit includes that first control signal generates Unit, second control signal generate unit and switch element；

The output end that the first control signal generates unit is connect with the control terminal of the switch element；

The output end that the second control signal generates unit is connect with the first end of the switch element.

2. d type flip flop control circuit according to claim 1, which is characterized in that the switch element includes NMOS tube.

3. d type flip flop control circuit according to claim 2, which is characterized in that when the first control signal generates list When member output high level, if second control signal is high level, the NMOS tube is opened, then d type flip flop sets 1；If second Control signal is low level, then d type flip flop is reset.

4. a kind of d type flip flop, which is characterized in that including d type flip flop control circuit described in claim 1.

5. d type flip flop according to claim 4, which is characterized in that further include latch cicuit, the latch cicuit includes the One latch units and the second latch units；

Wherein, the second end of the switch element is connected between first latch units and second latch units.

6. d type flip flop according to claim 4 or 5, which is characterized in that the switch element includes NMOS tube.

7. d type flip flop according to claim 6, which is characterized in that when the first control signal generates unit output height When level, if second control signal is high level, the NMOS tube is opened, then d type flip flop sets 1；If second control signal For low level, then d type flip flop is reset.