CN209043334U - A kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal - Google Patents
A kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal Download PDFInfo
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- CN209043334U CN209043334U CN201822130160.4U CN201822130160U CN209043334U CN 209043334 U CN209043334 U CN 209043334U CN 201822130160 U CN201822130160 U CN 201822130160U CN 209043334 U CN209043334 U CN 209043334U
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Abstract
The utility model discloses a kind of high speed synchronous sample processing systems of multiple groups analog-digital blended signal, including analog voltage signal data-interface, analog current signal data-interface, pulse data signal interface, digital signal input system, signal modulation module, analog signal filter processor, operational amplifier, A/D analog-digital converter, buffer memory, Ethernet transceiver module, digital signal output modules, PDA, four analog voltage signals acquire sensor, four analog current signal acquisition sensors and four pulse simulation signal acquisition sensors, buffer memory respectively with Ethernet transceiver module, the connection of data-signal output module.The collection of simulant signal of three types had both may be implemented in the utility model, 12 analog signal processings, conversion may be implemented again and obtain more comprehensively data in conjunction with the external digital signal transmitted, provide very comprehensive data supporting for subsequent product defect analysis.
Description
Technical field
The utility model relates to high-speed data acquisition field more particularly to a kind of high-speed synchronous of multiple groups analog-digital blended signal
Acquisition processing system.
Background technique
With manufacturing continuous development, surface curve degree, the radian of industrial products require higher and higher, the shape of product
Diversity and product batch, standardization level mutually restrict, while requiring product quality also higher and higher.Industrial products
After the processing and manufacturings such as molding, forging and stamping, casting, blow molding, the generation of surface defects of products is often inevitable, than
The defects of there are micro-bubble, scratch, spot, hole, impurity, breakage, stain, unqualified curved surface radians such as product surface, no
The beauty and comfort level of product are only influenced, and performance can be used for and bring adverse effect, so manufacturer is to product
Surface defects detection pay much attention to, need between product export to product carry out surface defects detection, to find in time,
To effective control for product quality, certain problems present in production technology can also be analyzed according to testing result, to prevent
Or reduce the generation of faulty goods.
The defects detection of product mostly uses greatly multiple sensors to sample product surface, then transmits sampled signal
Defect processing is carried out into computer, the sampled point on product is more, and it is more accurate for the defect analysis of product, generally directed to
The defects detection of medium-sized product detects acquisition frequently with 16 sensors and scans product surface, for the defect of small sized product
Detection generally also detects acquisition using 12 sensors and scans product surface, and conventional needle often adopts the defects detection of product
With single voltage sensor or single current sensor, do not occur using voltage sensor, current sensor and arteries and veins
It rushes sensor combinations mode and carries out product defects and detected.Acquisition is detected using 10 or more sensors and scans product
Surface can guarantee the defects detection more demanding to product surface quality in this way, since sensor needs in product defects detection
The signal to be sampled is more, this just needs a set of realization of High Speed sensor analog signals output, signal processing, analog-to-digital conversion etc.
Acquisition processing system, traditional approach are adopting using 12 sets of aggregate signal acquisitions, signal output, signal processing, analog-to-digital conversions etc.
Collect processing system, every set acquisition processing system is separately connected different sensors and acquires product surface different zones or difference
Surface data signal, then every set acquisition processing system at digital signal and is input to computer by processing, analog-to-digital conversion
In.It will result in more huge and scattered system in this way to lay, increase the use difficulty of product defects detection, deployment cost
Also larger, the route in system is easy to cause the defects of breaking, winding in use.Traditional acquisition processing system can only
Analog signal is received, the digital signal under different communications protocol can not be received, this is unfavorable for acquisition processing system and obtains more comprehensively
Data, to product defects analyze it is unfavorable.
Utility model content
Place in view of the shortcomings of the prior art, the purpose of this utility model is to provide a kind of mixing of multiple groups modulus to believe
Number high speed synchronous sample processing system, realize the collection of simulant signal of three types, analog signal processing, analog-to-digital conversion etc.
Reason obtains 12 digital signals, and N number of digital signal interface receives the digital signal under different communications protocol respectively, and passes through association
View conversion CPU is converted into digital signal under consolidated network agreement, and treated that 12 digital signals carry out is comprehensive together with modulus
Synchronous transfer carries out subsequent defective analysis processing into PDA after the digital signal filter processing of conjunction.
The purpose of this utility model is achieved through the following technical solutions:
A kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal, including analog voltage signal data-interface,
Analog current signal data-interface, pulse data signal interface, digital signal input system, signal modulation module, analog signal
Filter processor, operational amplifier, A/D analog-digital converter, buffer memory, Ethernet transceiver module, digital signal export mould
Block, PDA (15), four analog voltage signal acquisition sensors, four analog current signal acquisition sensors and four pulse modes
Quasi- signal acquisition sensor, the digital signal input system includes protocol conversion CPU, memory modules B, the protocol conversion
CPU is used for the data for decoding the data under different communications protocol, being converted under network communication protocol, the network communication protocol
Including ICP/IP protocol, NETBEUI agreement and IPX/SPX agreement, the digital signal input system further includes that digital signal is defeated
Outgoing interface and N number of digital signal interface, all digital signal interfaces are connect with protocol conversion CPU, memory modules B respectively, described
Memory modules B is connect with digital signal output interface；The analog voltage signal data-interface passes through signal transmission flat cable A and letter
The connection of number modulation module, the analog current signal data-interface are connect by signal transmission flat cable B with signal modulation module, institute
Pulse data signal interface is stated to connect by signal transmission flat cable C with signal modulation module；The analog voltage signal data connect
Mouth has at least four signal data interface A, has signal data transmission circuit inside the analog voltage signal data-interface
A, the signal data transmission circuit A include that at least four signal datas transmit sub-circuit A；The analog current signal data connect
Mouth has at least four signal data interface B, has signal data transmission circuit inside the analog current signal data-interface
B, the signal data transmission circuit B include that at least four signal datas transmit sub-circuit B；The pulse data signal interface
With at least four signal data interface C, the pulse data signal interface internal has signal data transmission circuit C, described
Signal data transmission circuit C includes that at least four signal datas transmit sub-circuit C；Have at least inside the signal modulation module
12 signal modulation circuits, the signal modulation module are connect with analog signal filter processor, the analog signal filtering
There are at least 12 analog signal filter circuits, the analog signal filter processor and operational amplifier connect inside processor
It connects, there is at least 12 operational amplification circuits, the operational amplifier and A/D analog-digital converter inside the operational amplifier
Connection, the A/D analog-digital converter inside have at least 12 analog-to-digital conversion modules, and signal data interface A, signal data pass
Defeated sub-circuit A, signal modulation circuit, analog signal filter circuit, operational amplification circuit, analog-to-digital conversion module successively correspond
Connection, signal data interface B, signal data transmit sub-circuit B, signal modulation circuit, analog signal filter circuit, operation amplifier
Circuit, analog-to-digital conversion module successively connect one to one, and signal data interface C, signal data transmit sub-circuit C, signal modulation
Circuit, analog signal filter circuit, operational amplification circuit, analog-to-digital conversion module successively connect one to one；The A/D modulus turns
Parallel operation is connect with buffer memory, and the digital signal output interface is connect with buffer memory, buffer memory respectively with
Too net transceiver module, digital signal output modules connection, the Ethernet transceiver module pass through wireless network mode and PDA network
Connection, the digital signal output modules are connect with PDA.
In order to which the utility model, communication used in the data before the protocol conversion CPU decoding, conversion is better achieved
Agreement include the following: S7-400 high speed communication agreement, S7-300 high speed communication agreement, S7-300/400 variable access agreement,
S7-1200/1500 variable access agreement, SIEMENS PLC real time ethernet protocol, Siemens's motion controller real-time ethernet association
View, Siemens TDC controller real time ethernet protocol, S7-300/400MPI/DP variable access agreement, S7-300/400 ether
Net iso variable access agreement, S7-200smart variable access agreement, reflective memory fidonetFido, GE company SNPX variable access
Agreement, GE company EGD communications protocol, GE company SRTP communications protocol, times good fortune real time ethernet protocol, times good fortune EtherCAT are real
When Ethernet protocol, times good fortune ADS variable access agreement, general WindowsUdp communications protocol, kernel KernalUDP communication association
View, general WindowsTcp server-side communications protocol, general WindowsTcp user client communication agreement, the OPC based on automation
Communications protocol, the OPC communications protocol based on Com component, the block access of ModbusTCP memory, ModbusTCP variable access agreement,
Modbus variable access agreement, standard serial port agreement RS232, AB real time ethernet protocol Ethernet/IP, ABPLC variable are deposited
Take agreement Ethernet/IPbackplate, real data files communications protocol Realtimedatafile, logical signal definition
Agreement Logicalsignals；The protocol conversion CPU leads to for decoding the data under above-mentioned communications protocol, being converted into network
It interrogates the data under agreement and is transmitted to memory modules B.
Preferably, there are four signal data interface A, signal data transmission electricity for the analog voltage signal data-interface tool
Road A includes that four signal datas transmit sub-circuit A；The analog current signal data-interface has there are four signal data interface B,
Signal data transmission circuit B includes that four signal datas transmit sub-circuit B；There are four signals for the pulse data signal interface tool
Data-interface C, signal data transmission circuit C include that four signal datas transmit sub-circuit C；Tool inside the signal modulation module
There are 12 signal modulation circuits, there is 12 analog signal filter circuits, institute inside the analog signal filter processor
Stating has 12 operational amplification circuits inside operational amplifier, inside the A/D analog-digital converter there are 12 moduluses to turn
Block is changed the mold, the analog-to-digital conversion module is for converting analog signals into digital signal, the analog voltage signal data-interface
Four signal data interface A and four signal datas transmission sub-circuit A connect one to one, analog voltage signal data-interface
Four signal datas transmission sub-circuit A connect one to one with four signal modulation circuits inside signal modulation module, institute
The four signal data interface B and four signal data transmission sub-circuit B for stating analog current signal data-interface are corresponded and are connected
It connects, four signals inside the four signal datas transmission sub-circuit B and signal modulation module of analog current signal data-interface
Modulation circuit connects one to one, and four signal data interface C of the pulse data signal interface and four signal datas pass
Defeated sub-circuit C connects one to one, the four signal datas transmission sub-circuit C and signal modulation module of pulse data signal interface
Four internal signal modulation circuits connect one to one, 12 signal modulation circuits, 12 analog signal filter circuits,
12 operational amplification circuits, 12 analog-to-digital conversion modules successively connect one to one；The signal transmission flat cable A has four
A signal transmission line, for the signal transmission flat cable B tool there are four signal transmission line, the signal transmission flat cable C has four
A signal transmission line.
Preferably, the utility model further includes digital signal filter processor, the digital signal filter processor
The connection of the output end of input terminal and buffer memory, the output end of the digital signal filter processor are received and dispatched with Ethernet respectively
The input terminal connection of the input terminal, digital signal output modules of module.
Preferably, having memory modules inside the Ethernet transceiver module.
The utility model compared with the prior art, have the following advantages that and the utility model has the advantages that
(1) the utility model acquires four voltage analog signals, four voltage analog signals and four by sensor respectively
A pulse simulation signal, 12 analog signals are synchronous respectively to realize signal acquisition, analog signal processing, analog-to-digital conversion, number
The data sampling process such as signal processing, data transmission, not only can be improved the system integration of product defects detection, have reduced
Layout difficulty, the system influence more compact that not will receive use process after laying, and share buffer memory and number
Signal filter processor, the concentration that synchronization digital signal may be implemented, quick, synchronous transfer are facilitated into computer
Subsequent computer subsequent data analysis processing.
(2) the utility model realizes that collection of simulant signal, analog signal processing, the analog-to-digital conversion etc. of three types are handled
To 12 digital signals, N number of digital signal interface receives the digital signal under different communications protocol respectively, and is turned by agreement
It changes CPU and is converted into digital signal under consolidated network agreement, and treated that 12 digital signals carry out is comprehensive together with modulus
Synchronous transfer carries out subsequent defective analysis processing into PDA after digital signal filter processing, it can thus be seen that the utility model
Not only the collection of simulant signal of three types may be implemented, but also 12 analog signal processings, conversion may be implemented and combine external
The digital signal transmitted carries out comprehensive product defects analysis, can provide for subsequent product defect analysis very comprehensively
Data supporting.
(3) the utility model for existing product mass defect detection realistic problem be simulated signal acquisition face,
The processes innovations such as signal processing, data transmission improve, so that data are acquired, laid, data transmission is more simplified, facilitate system cloth
If improving the speed and efficiency of data acquisition.
(4) the utility model has Ethernet transceiver module, and memory modules are equipped in Ethernet transceiver module, can
It is transmitted in computer in such a way that other digital signals for facilitating ten two digital signals and receiving carry out wireless network.
Detailed description of the invention
Fig. 1 is the structural block diagram of the utility model.
Wherein, title corresponding to the appended drawing reference in attached drawing are as follows:
1- analog voltage signal data-interface, 2- analog current signal data-interface, 3- pulse data signal interface,
4- data-signal output interface, 5- protocol conversion CPU, 6- memory modules B, 7- signal modulation module, the filter of 8- analog signal
Wave processor, 9- operational amplifier, 10-A/D analog-digital converter, 11- buffer memory, the processing of 12- digital signal filter
Device, 13- Ethernet transceiver module, 131- memory modules A, 14- digital signal output modules, 15-PDA.
Specific embodiment
The utility model is described in further detail below with reference to embodiment:
Embodiment
As shown in Figure 1, a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal, including analog voltage signal
Data-interface 1, analog current signal data-interface 2, pulse data signal interface 3, digital signal input system, signal modulation mould
Block 7, analog signal filter processor 8, operational amplifier 9, A/D analog-digital converter 10, buffer memory 11, digital signal filter
Processor 12, Ethernet transceiver module 13, digital signal output modules 14, PDA15, four analog voltage signal acquisition sensings
Device, four analog current signal acquisition sensors and four pulse simulation signal acquisition sensors, digital signal input system packet
Protocol conversion CPU5, memory modules B6 are included, protocol conversion CPU5 is used for data decoding, the conversion networking under different communications protocol
Data under network communications protocol, network communication protocol include ICP/IP protocol, NETBEUI agreement and IPX/SPX agreement.Such as Fig. 1
Shown, four analog voltage signal acquisition sensors are respectively the first acquisition sensors A, the second acquisition sensors A, third acquisition
Sensors A, the 4th acquisition sensors A, four analog current signal acquisition sensors are respectively the first acquisition sensor B, second
Sensor B, third acquisition sensor B, the 4th acquisition sensor B are acquired, four pulse simulation signal acquisition sensors are respectively
First acquisition sensor C, the second acquisition sensor C, third acquisition sensor C, the 4th acquisition sensor C.
Digital signal input system further includes digital signal output interface 4 and N number of digital signal interface, as shown in Fig. 1, N
A digital signal interface is respectively first interface, second interface ... N interface.All digital signal interfaces turn with agreement respectively
CPU5, memory modules B6 connection are changed, memory modules B6 is connect with digital signal output interface 4.Analog voltage signal data-interface 1
It is connect by signal transmission flat cable A with signal modulation module 7, analog current signal data-interface 2 passes through signal transmission flat cable B
It is connect with signal modulation module 7, pulse data signal interface 3 is connect by signal transmission flat cable C with signal modulation module 7.Mould
The quasi- tool of voltage signal data interface 1 has signal number inside analog voltage signal data-interface 1 there are four signal data interface A
It include that four signal datas transmit sub-circuit A according to transmission circuit A, signal data transmission circuit A, signal data transmits sub-circuit A
For mature circuit, the utility model analog voltage signal data-interface 1 is integrated in signal data transmission circuit A, and there are four signals
Data transmission circuit A.There are four signal data interface B, analog current signal data connect the tool of analog current signal data-interface 2
It includes that four signal datas transmit sub-circuit B that 2 inside of mouth, which has signal data transmission circuit B, signal data transmission circuit B, is believed
It is mature circuit that number, which transmits sub-circuit B, and the utility model analog current signal data-interface 2 is in signal data transmission circuit
Signal data transmits sub-circuit B there are four integrating in B.There are four signal data interface C, pulses for the tool of pulse data signal interface 3
Having signal data transmission circuit C, signal data transmission circuit C inside signal data interface 3 includes four signal data transmission
Sub-circuit C, it is mature circuit that signal data, which transmits sub-circuit C, and the utility model pulse data signal interface 3 is passed in signal data
Signal data transmits sub-circuit C there are four integrating in transmission of electricity road C.There are 12 signal modulation electricity inside signal modulation module 7
Road, signal modulation circuit are the analog signal modulation circuit of existing maturation, and the utility model signal modulation module 7 has been internally integrated
12 signal modulation circuits.Signal modulation module 7 is connect with analog signal filter processor 8, analog signal filter processor 8
Inside has 12 analog signal filter circuits, and analog signal filter circuit is the analog signal filter circuit of existing maturation,
The utility model analog signal filter processor 8 has been internally integrated 12 analog signal filter circuits.At analog signal filtering
Reason device 8 is connect with operational amplifier 9, has 12 operational amplification circuits inside operational amplifier 9, operational amplification circuit is existing
There is mature operational amplification circuit, the utility model operational amplifier 9 has been internally integrated 12 operational amplification circuits.Operation is put
Big device 9 is connect with A/D analog-digital converter 10, has 12 analog-to-digital conversion modules inside A/D analog-digital converter 10, and modulus turns
Changing the mold block is mature analog-to-digital conversion component, and analog-to-digital conversion module is for converting analog signals into digital signal.
As shown in Figure 1, four signal data interface A of analog voltage signal data-interface 1 and four signal datas transmit
Sub-circuit A connects one to one, the four signal datas transmission sub-circuit A and signal modulation of analog voltage signal data-interface 1
Four signal modulation circuits inside module 7 connect one to one, and four signal datas of analog current signal data-interface 2 connect
Mouth B and four signal datas transmission sub-circuit B connect one to one, four signal datas of analog current signal data-interface 2
Transmission sub-circuit B connects one to one with four signal modulation circuits inside signal modulation module 7, pulse data signal interface
3 four signal data interface C connect one to one with four signal data transmission sub-circuit C, pulse data signal interface 3
Four signal datas transmission sub-circuit C connect one to one with four signal modulation circuits inside signal modulation module 7, ten
Two signal modulation circuits, 12 analog signal filter circuits, 12 operational amplification circuits, 12 analog-to-digital conversion modules
Successively connect one to one.There are four signal transmission lines for signal transmission flat cable A tool, and there are four signals for signal transmission flat cable B tool
Transmission line, there are four signal transmission lines for signal transmission flat cable C tool.A/D analog-digital converter 10 is connect with buffer memory 11,
Digital signal output interface 4 is connect with buffer memory 11, the input terminal and buffer memory of digital signal filter processor 12
11 output end connection, the output end of digital signal filter processor 12 respectively with the input terminal of Ethernet transceiver module 13, number
The input terminal of word signal output module 14 connects, and Ethernet transceiver module 13 is connected by wireless network mode and PDA15 network
It connects, digital signal output modules 14 and PDA15 (or computer, PDA are palm PC) connect.In Ethernet transceiver module 13
Portion has memory modules 131, and when Ethernet transceiver module 13 carries out wireless network transmissions, memory modules 131 may be implemented to count
It is acted on according to caching.
As shown in Figure 1, protocol conversion CPU5 is decoded, communications protocol used in the data before conversion includes the following: S7-
400 high speed communication agreements, S7-300 high speed communication agreement, S7-300/400 variable access agreement, S7-1200/1500 variable are deposited
Take agreement, SIEMENS PLC real time ethernet protocol, Siemens's motion controller real time ethernet protocol, Siemens's TDC controller
Real time ethernet protocol, S7-300/400MPI/DP variable access agreement, S7-300/400 Ethernet iso variable access agreement,
S7-200smart variable access agreement, reflective memory fidonetFido, GE company SNPX variable access agreement, GE company EGD communication association
View, GE company SRTP communications protocol, times good fortune real time ethernet protocol, times good fortune EtherCAT real time ethernet protocol, times good fortune ADS
Variable access agreement, general WindowsUdp communications protocol, kernel KernalUDP communications protocol, general WindowsTcp service
End communication agreement, general WindowsTcp user client communication agreement, the OPC communications protocol based on automation, based on Com component
OPC communications protocol, the block access of ModbusTCP memory, ModbusTCP variable access agreement, Modbus variable access agreement, standard
Serial port protocol RS232, AB real time ethernet protocol Ethernet/IP, ABPLC variable access agreement Ethernet/
IPbackplate, real data files communications protocol Realtimedatafile, logical signal define agreement
Logicalsignals.N number of digital signal interface of the utility model is respectively adopted corresponding for above-mentioned communications protocol
Special purpose interface and exclusive data bus, protocol conversion CPU5 storage inside has to be carried out for the data under above-mentioned communications protocol respectively
The data conversion database or data conversion module of decoding, conversion, protocol conversion CPU5 can be by the number under above-mentioned communications protocol
According to the data for decoding, being converted under network communication protocol and it is transmitted to memory modules B6.
Four analog voltage signal acquisition sensors sample the different detection zones or difference test point of product surface respectively
The voltage analog signal of feedback, four analog current signals acquisition sensors sample respectively product surface different detection zones or
The current analog signal of different test point feedbacks, four pulse simulation signal acquisition sensors sample the difference of product surface respectively
The pulse simulation signal of detection zone or different test point feedbacks can acquire four analog voltage signals in actual use
Sensor forms one group of acquisition sensor group A, four analog voltage signal acquisition sensors can be formed one group of acquisition sensing
Four pulse simulation signal acquisition sensors can be formed one group of acquisition sensor group C by device group B, will acquisition sensor group A,
Acquisition sensor group B and acquisition sensor group C are respectively arranged on moving arm, are moved by moving arm and realize product table
The successively scan operation in face.Four analog voltage signal acquisition sensors respectively transmit sample four voltage analog signals
Into analog voltage signal data-interface 1, four signal datas transmission sub-circuit A of analog voltage signal data-interface 1 is one by one
It is corresponding to receive four voltage analog signals, and four voltage analog signal one-to-one correspondence are transmitted in signal modulation module 7
Signal modulation is wherein carried out in four signal modulation circuits, modulated four voltage analog signals one-to-one correspondence is transmitted to simulation
Four analog signal filter circuits of signal filter processor 8 carry out analog signal filtering processing, four electricity after filtering processing
Pressure analog signal corresponds the operational amplification circuit progress analog signal operation amplifier processing for being transmitted to operational amplifier 9, fortune
Four voltage analog signals after calculating enhanced processing correspond four analog-to-digital conversion moulds being transmitted in A/D analog-digital converter 10
Analog-to-digital conversion is carried out in block respectively, four voltage analog signals are converted into four number letters by four analog-to-digital conversion modules respectively
Number and the corresponding buffer memory 11 that is transmitted to carry out real-time, continuous buffer memory respectively.Four analog current signal acquisitions
Sample four current analog signals are transmitted in analog current signal data-interface 2 by sensor respectively, analog current letter
Four signal datas transmission sub-circuit B of number interface 2, which is corresponded, receives four current analog signals, and by four electricity
Flow field simulation signal corresponds in the four additional signal modulation circuit being transmitted in signal modulation module 7 and carries out signal modulation,
Modulated four current analog signals correspond four analog signal filtered electricals for being transmitted to analog signal filter processor 8
Road carries out analog signal filtering processing, and four current analog signals one-to-one correspondence after filtering processing is transmitted to operational amplifier 9
Operational amplification circuit carry out the processing of analog signal operation amplifier, operation amplifier treated four current analog signals one are a pair of
Analog-to-digital conversion, four current analog letters are carried out in four analog-to-digital conversion modules that should be transmitted in A/D analog-digital converter 10 respectively
Number it is converted into four digital signals respectively by four analog-to-digital conversion modules and corresponding be transmitted to buffer memory 11 and distinguished
In real time, continuous buffer memory.Four pulse simulation signal acquisition sensors respectively believe sample four pulse simulations
It number is transmitted in pulse data signal interface 3, four signal datas transmission sub-circuit C mono- of pulse data signal interface 3 is a pair of
It should receive four pulse simulation signals, and four pulse simulation signals one-to-one correspondence are transmitted to another in signal modulation module 7
Signal modulation is carried out in outer four signal modulation circuits, modulated four pulse simulation signals one-to-one correspondence is transmitted to simulation letter
Four analog signal filter circuits of number filter processor 8 carry out analog signal filtering processing, four pulses after filtering processing
Analog signal corresponds the operational amplification circuit progress analog signal operation amplifier processing for being transmitted to operational amplifier 9, operation
Four pulse simulation signals after enhanced processing correspond four analog-to-digital conversion moulds being transmitted in A/D analog-digital converter 10
Analog-to-digital conversion is carried out in block respectively, four pulse simulation signals are converted into four number letters by four analog-to-digital conversion modules respectively
Number and the corresponding buffer memory 11 that is transmitted to carry out real-time, continuous buffer memory respectively.
In this way, just real-time, continuous buffer memory has 12 digital signals, digital signal filter to buffer memory 11
Processor 8 carries out digital signal filter processing to 12 digital signals respectively and passes through filtered 12 digital signals
Digital signal output modules 10 are transmitted to PDA11 (or computer, PDA are palm PC) or filtered 12 numbers
Signal is transmitted in Ethernet transceiver module 9, and the memory modules 91 in Ethernet transceiver module 9 are used for 12 digital signals
Cached, Ethernet transceiver module 9 by 12 digital signals by wireless network mode be transmitted to PDA11 (or calculate
Machine, PDA are palm PC).Meanwhile receiving the digital signal number under different communications protocol respectively by N number of digital signal interface
According to, then protocol conversion CPU5 effect under by under different communications protocol digital signal data decoding, be converted to network communication
Digital signal data after conversion is simultaneously stored in memory modules B6 by digital signal data under agreement, and memory modules B6 will
Digital signal data after conversion is transmitted in buffer memory 11 by data-signal output interface 4, and buffer memory 11 is just
In real time, it is continuously cached with the digital signal data in addition to 12 digital signals that analog-to-digital conversion is come, PDA11 can
It is handled with the product defects analysis for carrying out next step according to obtained all digital signal datas.Certainly, the utility model
PDA11 can individually receive the digital signal data of product defects, then PDA11 based on the received digital signal data into
The product defects analysis of row next step is handled.
The analog voltage signal data-interface 1 of the utility model is separately connected four analog voltage signal acquisition sensors,
Analog current signal data-interface 2 is separately connected four analog current signal acquisition sensors, and pulse data signal interface 3 is distinguished
Four pulse simulation signal acquisition sensors are connected, determine that the sensor by surface defects of products detection is divided into four in this way
Analog voltage signal acquires sensor, four analog current signals acquire sensor, four pulse simulation signal acquisition sensors.
It is correspondingly connected with four analog voltage signal acquisition sensor groups and by same analog voltage signal data-interface 1, mould
Four signal data interface A are provided on quasi- voltage signal data interface 1 to realize four analog voltage signal acquisition sensors
It is correspondingly connected with；Meanwhile by four analog current signal acquisition sensor groups and passing through same analog current signal data-interface 2
It is correspondingly connected with, four signal data interface B is provided on analog current signal data-interface 2 to realize four analog current signals
Acquisition sensor is correspondingly connected with.It is connect four pulse simulation signal acquisition sensor groups and by same pulse data signal
Mouthfuls 3 are correspondingly connected with, and four signal data interface C are provided on pulse data signal interface 3 to realize four pulse simulation signals
Acquisition sensor is correspondingly connected with.Four voltage analog signals, four current analog signals and four pulse simulation signals just divide
Group carries out analog signal transmission and subsequent processing.Voltage analog signal modulation circuit, four there are four being integrated in signal modulation module 7
A current analog signal modulation circuit and four pulse simulation signal modulation circuits, 12 signal modulation circuits, 12 moulds
Quasi- signal filter circuit, 12 operational amplification circuits successively respectively to four voltage analog signals, four current analog signals,
Four pulse simulation signals carry out analog signal processing, then four voltage analog signals, four current analog signals, four arteries and veins
It rushes analog signal and synchronizes analog-to-digital conversion respectively in 12 analog-to-digital conversion modules respectively in A/D analog-digital converter 10,
It thus synchronizes to obtain 12 digital signals, buffer memory is in buffer memory 11 again for 12 digital signals, using straight
It connects two data transfer modes of mode and network mode and is transmitted to PDA15 (or computer, PDA are palm PC), so far complete
12 analog signals just realize the data samplings such as synchronous acquisition, synchronous analog signal processing, synchronous ADC, synchronous transfer
Process, PDA15 obtain the product defects analysis processing that 12 digital signals carry out next step again.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (5)
1. a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal, including digital signal input system, the number
Word signal input system includes protocol conversion CPU (5), memory modules B (6), and the protocol conversion CPU (5) is used for difference is logical
Data decoding under news agreement, the data that are converted under network communication protocol, the network communication protocol include ICP/IP protocol,
NETBEUI agreement and IPX/SPX agreement, it is characterised in that: including analog voltage signal data-interface (1), analog current signal
Data-interface (2), pulse data signal interface (3), signal modulation module (7), analog signal filter processor (8), operation are put
Big device (9), A/D analog-digital converter (10), buffer memory (11), Ethernet transceiver module (13), digital signal output modules
(14), PDA (15), four analog voltage signal acquisition sensors, four analog current signal acquisition sensors and four pulses
Collection of simulant signal sensor, the digital signal input system further include digital signal output interface (4) and N number of digital signal
Interface, all digital signal interfaces are connect with protocol conversion CPU (5), memory modules B (6) respectively, the memory modules B (6) with
Digital signal output interface (4) connection；The analog voltage signal data-interface (1) passes through signal transmission flat cable A and signal tune
Molding block (7) connection, the analog current signal data-interface (2) are connected by signal transmission flat cable B and signal modulation module (7)
It connects, the pulse data signal interface (3) is connect by signal transmission flat cable C with signal modulation module (7)；The analog voltage
Signal data interface (1) has at least four signal data interface A, has inside the analog voltage signal data-interface (1)
Signal data transmission circuit A, the signal data transmission circuit A include that at least four signal datas transmit sub-circuit A；The mould
Quasi- current signal data-interface (2) have at least four signal data interface B, and the analog current signal data-interface (2) is interior
It includes that at least four signal datas transmit sub-circuit B that portion, which has signal data transmission circuit B, the signal data transmission circuit B,；
The pulse data signal interface (3) has at least four signal data interface C, and the pulse data signal interface (3) is internal
With signal data transmission circuit C, the signal data transmission circuit C includes that at least four signal datas transmit sub-circuit C；Institute
Stating has at least 12 signal modulation circuits, the signal modulation module (7) and analog signal inside signal modulation module (7)
Filter processor (8) connection, the analog signal filter processor (8) is internal to have at least 12 analog signal filtered electricals
Road, the analog signal filter processor (8) connect with operational amplifier (9), have at least inside the operational amplifier (9)
12 operational amplification circuits, the operational amplifier (9) connect with A/D analog-digital converter (10), the A/D analog-digital converter
(10) internal to have at least 12 analog-to-digital conversion modules, signal data interface A, signal data transmit sub-circuit A, signal modulation
Circuit, analog signal filter circuit, operational amplification circuit, analog-to-digital conversion module successively connect one to one, signal data interface
B, signal data transmits sub-circuit B, signal modulation circuit, analog signal filter circuit, operational amplification circuit, analog-to-digital conversion module
Successively connect one to one, signal data interface C, signal data transmission sub-circuit C, signal modulation circuit, analog signal filtering
Circuit, operational amplification circuit, analog-to-digital conversion module successively connect one to one；The A/D analog-digital converter (10) is deposited with caching
Reservoir (11) connection, the digital signal output interface (4) connect with buffer memory (11), buffer memory (11) respectively with
Ethernet transceiver module (13), digital signal output modules (14) connection, the Ethernet transceiver module (13) pass through wireless network
Network mode and PDA (15) are connected to the network, and the digital signal output modules (14) connect with PDA (15).
2. a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal described in accordance with the claim 1, feature exist
In: communications protocol used in the data before protocol conversion CPU (5) decoding, conversion includes the following: S7-400 high speed communication
Agreement, S7-300 high speed communication agreement, S7-300/400 variable access agreement, S7-1200/1500 variable access agreement, west gate
Sub- PLC real time ethernet protocol, Siemens's motion controller real time ethernet protocol, Siemens TDC controller real-time ethernet
Agreement, S7-300/400MPI/DP variable access agreement, S7-300/400 Ethernet iso variable access agreement, S7-200smart
Variable access agreement, reflective memory fidonetFido, GE company SNPX variable access agreement, GE company EGD communications protocol, GE company
SRTP communications protocol, times good fortune real time ethernet protocol, times good fortune EtherCAT real time ethernet protocol, times good fortune ADS variable access association
View, general WindowsUdp communications protocol, kernel KernalUDP communications protocol, general WindowsTcp server-side communications protocol,
General WindowsTcp user client communication agreement, the OPC communications protocol based on automation, the OPC based on Com component communicate association
View, the block access of ModbusTCP memory, ModbusTCP variable access agreement, Modbus variable access agreement, standard serial port agreement
RS232, AB real time ethernet protocol Ethernet/IP, ABPLC variable access agreement Ethernet/IPbackplate, in real time
Data file communications protocol Realtimedatafile, logical signal define agreement Logicalsignals；The protocol conversion
CPU (5) be used for by under above-mentioned communications protocol data decoding, the data that are converted under network communication protocol and be transmitted to memory mould
Block B (6).
3. a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal according to claim 1 or 2, feature
Be: analog voltage signal data-interface (1) tool includes four there are four signal data interface A, signal data transmission circuit A
A signal data transmits sub-circuit A；There are four signal data interface B, signal numbers for analog current signal data-interface (2) tool
It include that four signal datas transmit sub-circuit B according to transmission circuit B；There are four signal numbers for pulse data signal interface (3) tool
It include that four signal datas transmit sub-circuit C according to interface C, signal data transmission circuit C；The signal modulation module (7) is internal
With 12 signal modulation circuits, there are 12 analog signal filtered electricals inside the analog signal filter processor (8)
Road, the operational amplifier (9) is internal to have 12 operational amplification circuits, has inside the A/D analog-digital converter (10)
12 analog-to-digital conversion modules, the analog-to-digital conversion module is for converting analog signals into digital signal, the analog voltage
Four signal data interface A of signal data interface (1) connect one to one with four signal data transmission sub-circuit A, simulate
Four signal datas transmission sub-circuit A of voltage signal data interface (1) and four signal tune of signal modulation module (7) inside
Circuit processed connects one to one, the four signal data interface B and four signal numbers of the analog current signal data-interface (2)
Connect one to one according to transmission sub-circuit B, four signal datas of analog current signal data-interface (2) transmission sub-circuit B with
Four internal signal modulation circuits of signal modulation module (7) connect one to one, and the four of the pulse data signal interface (3)
A signal data interface C connects one to one with four signal data transmission sub-circuit C, and the four of pulse data signal interface (3)
Four signal modulation circuits a signal data transmission sub-circuit C internal with signal modulation module (7) connect one to one, and 12
A signal modulation circuit, 12 analog signal filter circuits, 12 operational amplification circuits, 12 analog-to-digital conversion modules according to
It is secondary to connect one to one；For the signal transmission flat cable A tool there are four signal transmission line, the signal transmission flat cable B has four
A signal transmission line, there are four signal transmission lines for the signal transmission flat cable C tool.
4. a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal described in accordance with the claim 3, feature exist
In: it further include digital signal filter processor (12), the input terminal and buffer memory of the digital signal filter processor (12)
The output end of device (11) connects, the output end of the digital signal filter processor (12) respectively with Ethernet transceiver module (13)
Input terminal, digital signal output modules (14) input terminal connection.
5. a kind of high speed synchronous sample processing system of multiple groups analog-digital blended signal, feature exist according to claim 4
In: there are memory modules (131) inside the Ethernet transceiver module (13).
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880233A (en) * | 2019-12-06 | 2020-03-13 | 大连理工大学 | Time-synchronized hybrid analog and digital sensor data acquisition system and method |
| CN111157783A (en) * | 2019-12-28 | 2020-05-15 | 杭州拓深科技有限公司 | Control system for common acquisition of differential signal and waveform data |
| CN112462927A (en) * | 2020-12-10 | 2021-03-09 | 曙光信息产业股份有限公司 | Voltage regulation method and device, server and computer readable storage medium |
| CN114061825A (en) * | 2020-07-29 | 2022-02-18 | 英飞凌科技股份有限公司 | Multiple sensor measurement with analog output |
| CN114600050A (en) * | 2020-09-30 | 2022-06-07 | 焦旭 | Multi-signal parallel acquisition circuit, electronic device and body characteristic signal acquisition instrument |
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2018
- 2018-12-19 CN CN201822130160.4U patent/CN209043334U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880233A (en) * | 2019-12-06 | 2020-03-13 | 大连理工大学 | Time-synchronized hybrid analog and digital sensor data acquisition system and method |
| CN111157783A (en) * | 2019-12-28 | 2020-05-15 | 杭州拓深科技有限公司 | Control system for common acquisition of differential signal and waveform data |
| CN114061825A (en) * | 2020-07-29 | 2022-02-18 | 英飞凌科技股份有限公司 | Multiple sensor measurement with analog output |
| CN114600050A (en) * | 2020-09-30 | 2022-06-07 | 焦旭 | Multi-signal parallel acquisition circuit, electronic device and body characteristic signal acquisition instrument |
| CN112462927A (en) * | 2020-12-10 | 2021-03-09 | 曙光信息产业股份有限公司 | Voltage regulation method and device, server and computer readable storage medium |
| CN112462927B (en) * | 2020-12-10 | 2022-08-30 | 曙光信息产业股份有限公司 | Voltage regulation method and device, server and computer readable storage medium |
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