CN112462927B - Voltage regulation method and device, server and computer readable storage medium - Google Patents

Voltage regulation method and device, server and computer readable storage medium Download PDF

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Publication number
CN112462927B
CN112462927B CN202011434816.7A CN202011434816A CN112462927B CN 112462927 B CN112462927 B CN 112462927B CN 202011434816 A CN202011434816 A CN 202011434816A CN 112462927 B CN112462927 B CN 112462927B
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cpu
communication protocol
control chip
stage
communication
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CN112462927A (en
Inventor
白文记
邓建廷
孙寰宇
李海杰
曹泽中
宿韧
路云飞
范敬柱
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Zhongke Sugon Information Industry Chengdu Co ltd
Dawning Information Industry Co Ltd
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Zhongke Sugon Information Industry Chengdu Co ltd
Dawning Information Industry Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application relates to a voltage regulation method and device, a server and a computer readable storage medium, comprising: and determining a target communication protocol of the CPU currently communicating with the power control chip from a preset communication protocol set according to the current running state of the CPU. Specifically, a first communication protocol determined for the power-on phase and the power-off phase from the plurality of communication protocols is different from a second communication protocol determined for the normal operation phase from the plurality of communication protocols. Different communication protocols are configured in different states of the CPU to transmit the voltage regulation signal, so that the problem that the voltage regulation signal output by the CPU to the power supply control chip is inaccurate frequently caused by the fact that an open source communication protocol is adopted in the traditional method at the starting-up stage or the shutdown stage of the CPU is solved. And then, controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol. Finally, the control power supply control chip accurately adjusts the input voltage of the CPU according to the voltage adjusting signal.

Description

Voltage regulation method and device, server and computer readable storage medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to a voltage adjustment method and apparatus, a server, and a computer-readable storage medium.
Background
With the continuous development of cloud computing technology, the performance of the CPU is also continuously improved. While the performance of the CPU is continuously improved, the power consumption of the CPU is also increasing. In order to reduce the power consumption of the CPU, a scheme is proposed to dynamically adjust the voltage of the CPU. When the CPU is in a high load, the power control chip is controlled to configure high voltage for the CPU so as to meet the normal operation of the CPU; and when the CPU is in a low load, the power supply control chip is controlled to configure a low voltage for the CPU so as to reduce the power consumption of the CPU while meeting the normal operation of the CPU.
However, for some CPUs using an open source communication protocol to communicate with a power control chip, in a power-on stage or a power-off stage of the CPU, a condition that a voltage regulation signal output by the CPU to the power control chip is not accurate often occurs, so that the power control chip cannot perform accurate dynamic voltage regulation on the CPU.
Disclosure of Invention
The embodiment of the application provides a voltage regulation method, a voltage regulation device, a server and a computer readable storage medium, which can be used for accurately and dynamically regulating the voltage of a CPU.
A voltage regulation method, comprising:
acquiring the current running state of the CPU; the running state comprises any one of a starting stage, a shutdown stage and a normal running stage of the CPU;
determining a target communication protocol of the CPU which is currently communicated with a power control chip from a preset communication protocol set according to the current running state of the CPU; wherein the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase;
sending a control instruction to the CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power control chip by adopting the target communication protocol so as to control the power control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
In the embodiment of the application, the BIOS chip determines a target communication protocol for the CPU to communicate with the power control chip currently from a preset communication protocol set according to the current running state of the CPU. Specifically, a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase. Different communication protocols are configured in different states of the CPU to transmit the voltage regulation signal, so that the problem that the voltage regulation signal output to the power supply control chip by the CPU is inaccurate frequently caused by the adoption of an open source communication protocol in the traditional CPU starting stage or the traditional CPU shutdown stage is solved. And then, controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol. And finally, the control power supply control chip adjusts the input voltage of the CPU according to the voltage adjusting signal.
In one embodiment, the obtaining the current running state of the CPU includes:
and if a CPU starting instruction is monitored, acquiring the current running state of the CPU as being in the starting stage.
In the embodiment of the present application, the BIOS chip monitors the current operating state of the CPU in real time, and specifically, if the BIOS chip monitors that a CPU boot instruction is triggered, it indicates that the current operating state of the CPU is in a boot stage. Therefore, the BIOS chip acquires that the current running state of the CPU is in a boot stage. The BIOS chip judges whether the current running state of the CPU enters a starting-up stage by monitoring whether a CPU starting-up instruction is triggered, and the BIOS chip can conveniently, quickly and accurately judge the current running state of the CPU.
In one embodiment, the acquiring the current running state of the CPU further includes:
judging whether the CPU is powered on in the starting-up stage;
and if so, the CPU enters the normal operation stage from the starting stage and acquires the current operation state of the CPU as being in the normal operation stage.
In the embodiment of the application, when the CPU is in a starting-up stage, the BIOS chip determines the current running state of the CPU by judging whether the CPU is powered on or not. Specifically, if the CPU is powered on in the startup phase, the current operating state of the CPU is acquired and the CPU enters the normal operating phase from the startup phase. The judgment mode is convenient and quick, and the BIOS chip can accurately judge the current running state of the CPU through the judgment mode.
In one embodiment, the acquiring the current running state of the CPU further includes:
and if a CPU shutdown instruction is monitored in the normal operation stage, acquiring the current operation state of the CPU, and entering the shutdown stage from the normal operation stage.
In the embodiment of the application, in the normal operation stage, the BIOS chip determines whether the current operation state of the CPU enters the shutdown stage from the normal operation stage by judging whether a CPU shutdown instruction is monitored. The judgment mode is convenient and quick, and the BIOS chip can accurately judge the current running state of the CPU through the judgment mode.
In one embodiment, the first communication protocol is an I2C communication protocol, and the second preset communication protocol is an open source communication protocol.
In the embodiment of the application, the BIOS chip acquires the current running state of the CPU, and determines the current target communication protocol for the CPU to communicate with the power control chip from a preset communication protocol set according to the current running state of the CPU. And when the CPU is in a starting-up stage or a shutdown stage, the BIOS chip controls the CPU to communicate with the power supply control chip by adopting an I2C communication protocol. And when the CPU is in a normal operation stage, the BIOS chip controls the CPU to communicate with the power supply control chip by adopting an open source communication protocol. Therefore, the compatibility problem of the open source communication protocol is solved, and the data transmission speed is improved.
In one embodiment, the second preset communication protocol is a PVID communication protocol; the determining, from a preset communication protocol set, a target communication protocol for the current communication between the CPU and the power control chip according to the current operating state of the CPU includes:
if the current running state of the CPU is in the starting-up stage, determining that the target communication protocol is an I2C communication protocol from a preset communication protocol set;
if the current running state of the CPU enters the normal running stage from the starting stage, determining that the target communication protocol is a PVID communication protocol;
and if the current running state of the CPU enters the shutdown stage from the normal running stage, determining that the target communication protocol is the I2C communication protocol.
In the embodiment of the application, if the current running state of the CPU is in the boot stage, it is determined from the preset communication protocol set that the target communication protocol is the I2C communication protocol. And if the current running state of the CPU enters a normal running stage from a starting stage, determining that the target communication protocol is the PVID communication protocol. And if the current running state of the CPU enters a shutdown stage from a normal running stage, determining that the target communication protocol is the I2C communication protocol. In the startup stage or the shutdown stage of the CPU, an I2C communication protocol with a wide application range is adopted to meet the requirement of accurately transmitting information. And when the CPU is not in the startup stage and the shutdown stage, the PVID communication protocol is adopted to carry out high-speed and accurate information transmission. The problem that the electrical signal of the PIN corresponding to the PVID communication protocol on the CPU is ambiguous in the starting-up stage or the shutdown stage of the CPU is solved.
In one embodiment, if the current running state of the CPU is in the boot stage, the sending a control instruction to the CPU includes:
sending the equipment address of the power control chip and the I2C address of the power control chip to the CPU;
the method comprises the steps of sending a control instruction to a CPU to control the CPU to establish I2C communication between the CPU and a power supply control chip according to an equipment address of the power supply control chip and an I2C address of the power supply control chip, and controlling the CPU to output a voltage regulation signal to the power supply control chip through the I2C communication.
In the embodiment of the application, after determining that the target communication protocol is the I2C communication protocol, the BIOS chip sends the device address of the power control chip and the I2C address of the power control chip to the CPU. The CPU can establish I2C communication between the CPU and the power control chip based on the device address of the power control chip and the I2C address of the power control chip. At this time, the CPU can output a voltage adjustment signal to the power control chip through I2C communication. The I2C communication protocol with wider application range is adopted in the CPU startup stage or the CPU shutdown stage to meet the requirement of accurately transmitting information.
In one embodiment, if the current operation state of the CPU enters the normal operation stage from the boot stage, the sending a control instruction to the CPU includes:
modifying the numerical value of the register of the power control chip into a first value, wherein the first value is used for starting a PVID interface of the power control chip;
the control instruction is sent to the CPU to control the CPU to switch the I2C communication between the CPU and the power supply control chip into PVID communication based on a PVID interface, and control the CPU to output a voltage adjusting signal to the power supply control chip through the PVID communication.
In the embodiment of the application, after the BIOS chip determines that the target communication protocol is the PVID communication protocol, the BIOS chip modifies the value of the register of the power control chip to be the first value, and turns on the PVID interface of the power control chip. The CPU switches I2C communication between the CPU and the power supply control chip to PVID communication based on the PVID interface, and outputs a voltage adjustment signal to the power supply control chip through the PVID communication. The method can realize high-speed and accurate information transmission by adopting the PVID communication protocol when the CPU is not in the startup stage and the shutdown stage.
In one embodiment, if the current operating state of the CPU enters the shutdown phase from the normal operating phase, the sending a control instruction to the CPU includes:
changing the value of the register of the power control chip from a first value to a second value, wherein the second value is used for closing a PVID interface of the power control chip;
and sending a control instruction to the CPU to control the CPU to switch the PVID communication between the CPU and the power supply control chip into I2C communication, and control the CPU to output a voltage regulation signal to the power supply control chip through the I2C communication.
In the embodiment of the application, after determining that the target communication protocol is the I2C communication protocol, the BIOS chip modifies the value of the register of the power control chip from the first value to the second value, and closes the PVID interface of the power control chip. At this time, the CPU can output a voltage adjustment signal to the power control chip through the originally established I2C communication. The I2C communication protocol with wider application range is adopted in the CPU startup stage or the CPU shutdown stage to meet the requirement of accurately transmitting information.
A voltage regulation method, comprising:
receiving a control instruction determined by the BIOS chip according to the running state of the CPU; the running state comprises any one stage of a starting stage, a shutdown stage and a normal running stage of the CPU;
outputting a voltage regulation signal to a power supply control chip by adopting a target communication protocol according to the control instruction; the target communication protocol is determined by the BIOS from a preset communication protocol set based on the running state of the CPU; the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase;
and controlling the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
In the embodiment of the application, the CPU receives a control instruction determined by the BIOS chip according to the running state of the CPU, and outputs a voltage regulation signal to the power control chip by adopting a target communication protocol according to the control instruction. So that the power supply control chip can adjust the input voltage of the CPU according to the voltage adjusting signal after receiving the voltage adjusting signal. The CPU outputs a voltage regulation signal to the power control chip by adopting a first communication protocol in a starting-up stage and a shutdown stage. And the CPU outputs a voltage regulation signal to the power supply control chip by adopting a second communication protocol in the normal operation stage. The first communication protocol and the second communication protocol are two different communication protocols. Therefore, different communication protocols are adopted for communication in different states of the CPU, and the problem that a voltage adjusting signal output to a power supply control chip by the CPU is inaccurate frequently in the starting-up stage or the shutdown stage of the CPU by adopting an open source communication protocol in the prior art is solved. Finally, accurate dynamic voltage regulation of the CPU can be realized.
A voltage regulation device, comprising:
the running state acquisition module is used for acquiring the current running state of the CPU; the running state comprises any one of a starting stage, a shutdown stage and a normal running stage of the CPU;
the target communication protocol determining module is used for determining a target communication protocol of the CPU which is currently communicated with the power control chip from a preset communication protocol set according to the current running state of the CPU; wherein the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase;
the control instruction sending module is used for sending a control instruction to the CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting the target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
A server comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, causes the processor to carry out the steps of the above method.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method as above.
The voltage adjusting method, the voltage adjusting device, the server and the computer readable storage medium acquire the current running state of the CPU; the running state comprises any one stage of a starting-up stage, a shutdown stage and a normal running stage of the CPU. Determining a target communication protocol of the CPU currently communicating with the power control chip from a preset communication protocol set according to the current running state of the CPU; the communication protocol set comprises a plurality of communication protocols, and a first communication protocol determined for a startup phase and a shutdown phase from the plurality of communication protocols is different from a second communication protocol determined for a normal operation phase from the plurality of communication protocols. Sending a control instruction to a CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
And determining a target communication protocol of the CPU currently communicating with the power control chip from a preset communication protocol set according to the current running state of the CPU. Specifically, a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase. Different communication protocols are configured in different states of the CPU to transmit the voltage regulation signal, so that the problem that the voltage regulation signal output to the power supply control chip by the CPU is inaccurate frequently caused by the adoption of an open source communication protocol in the traditional CPU starting stage or the traditional CPU shutdown stage is solved. And then, controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol. Finally, the control power supply control chip accurately adjusts the input voltage of the CPU according to the voltage adjusting signal.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of an exemplary embodiment of a voltage regulation method;
FIG. 2 is a flow diagram of a voltage regulation method in one embodiment;
FIG. 3 is a flowchart of the method of FIG. 2 for obtaining the current running state of the CPU;
FIG. 4 is a flowchart of the method for determining a target communication protocol for the CPU to currently communicate with the power control chip from a preset communication protocol set in FIG. 2;
FIG. 5 is a flow diagram of a method of sending control instructions to the CPU of FIG. 2 in one embodiment;
FIG. 6 is a flow chart of a method of sending control commands to the CPU of FIG. 2 in another embodiment;
FIG. 7A is a diagram illustrating an interface on a power control chip in accordance with one embodiment;
FIG. 7B is a diagram illustrating the establishment of two types of communication links between the CPU and the power control chip, according to one embodiment;
FIG. 8 is a flow chart of a voltage regulation method in another embodiment;
FIG. 9 is a block diagram of a voltage regulation device in one embodiment;
fig. 10 is a schematic diagram of an internal configuration of a server in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.
As shown in fig. 1, fig. 1 is a diagram of an application scenario of a voltage regulation method in an embodiment. The application environment includes a server 100, and the server 100 includes a BIOS chip 120, a CPU140, and a power control chip 160. The BIOS chip 120 obtains the current running state of the CPU; the running state comprises any one stage of a starting stage, a shutdown stage and a normal running stage of the CPU; according to the current running state of the CPU, determining a target communication protocol of the CPU for communicating with the power control chip from a preset communication protocol set; the communication protocol set comprises a plurality of communication protocols, and a first communication protocol determined for a startup phase and a shutdown phase in the plurality of communication protocols is different from a second communication protocol determined for a normal operation phase in the plurality of communication protocols; sending a control instruction to a CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal. Of course, the voltage adjusting method may be applied to any terminal device such as a mobile phone, a tablet computer, a PDA (Personal Digital Assistant), a wearable device, and a smart home.
Fig. 2 is a flowchart of a voltage regulation method in an embodiment, and as shown in fig. 2, a voltage regulation method is provided and applied to a server or a terminal device. The method includes the following steps 220 through 240.
Step 220, acquiring the current running state of the CPU; the running state comprises any one of the current starting stage, the current shutdown stage and the normal running stage of the CPU.
The server 100 includes a BIOS chip, a CPU140, and a power control chip 160. The BIOS chip monitors the current running state of the CPU and obtains the current running state of the CPU. The running state comprises any one of the current starting stage, the current shutdown stage and the normal running stage of the CPU.
For some CPUs using an open source communication protocol to communicate with a power control chip, during the power-on stage or the power-off stage of the CPU, the electrical signal of the PIN corresponding to the open source communication protocol on the CPU is unclear. That is, in each power-on or power-off stage, the electrical signal of the PIN corresponding to the power-on communication protocol on the CPU is sometimes at a high level and sometimes at a low level. Obviously, the undefined electrical signal of the PIN may cause the inaccurate voltage regulation signal output by the CPU to the power control chip, so that the power control chip may not perform accurate dynamic voltage regulation on the CPU. Therefore, the current stage of the CPU is monitored by the BIOS chip 120, so as to configure a corresponding communication protocol according to the current stage of the CPU, and solve the problem that the voltage adjustment signal output to the power control chip is inaccurate at the power-on stage or the power-off stage of the CPU. So that the CPU can accurately output the voltage adjusting signal to the power control chip.
And 240, determining a target communication protocol for the CPU to communicate with the power control chip currently from a preset communication protocol set according to the current running state of the CPU.
The communication protocol set comprises a plurality of communication protocols, and a first communication protocol determined for a startup phase and a shutdown phase from the plurality of communication protocols is different from a second communication protocol determined for a normal operation phase from the plurality of communication protocols. These multiple communication protocols may be open source communication protocols, or may include communication protocols developed by themselves, which is not limited in this application.
The BIOS chip pre-stores the corresponding relation table of the CPU current operation state and the communication protocol in the communication protocol set. Therefore, the BIOS chip can determine the current target communication protocol for the CPU to communicate with the power control chip according to the current running state of the CPU and the corresponding relation table. The voltage regulating signal is configured by the CPU according to the load condition of the CPU. Specifically, when the load condition of the CPU is a high load, the CPU configures the voltage adjustment signal to increase the input voltage according to the load condition of its own CPU. When the load condition of the CPU is low load, the CPU configures the voltage regulating signal to reduce the input voltage according to the load condition of the CPU. The input voltage of the CPU is dynamically adjusted, so that the CPU enters an energy-saving mode under the condition of low load, and the power consumption of the CPU is reduced. Of course, the CPU may also configure the voltage adjustment signal to specifically adjust to a specific voltage value according to a load condition of the CPU itself, so as to implement finer voltage adjustment, which is not limited in this application.
In step 260, the CPU sends control instructions.
After determining the target communication protocol, the BIOS chip sends control instructions to the CPU. After receiving the control instruction, the CPU may output a voltage adjustment signal to the power control chip by using the target communication protocol, so as to control the power control chip to adjust the input voltage of the CPU according to the voltage adjustment signal.
In the embodiment of the application, the BIOS chip determines a target communication protocol for the CPU to communicate with the power control chip currently from a preset communication protocol set according to the current running state of the CPU. Specifically, a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase. Different communication protocols are configured in different states of the CPU to transmit the voltage regulation signal, so that the problem that the voltage regulation signal output by the CPU to the power supply control chip is inaccurate frequently caused by the fact that an open source communication protocol is adopted in the traditional method at the starting-up stage or the shutdown stage of the CPU is solved. And then, controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol. Finally, the control power supply control chip is controlled to regulate the input voltage of the CPU according to the voltage regulation signal.
In one embodiment, obtaining the current running state of the CPU includes:
and if the CPU starting command is monitored, acquiring the current running state of the CPU as being in a starting stage.
The CPU power-on instruction may refer to a CPU power-on instruction triggered by an operation of a power-on/power-off button of the server or the terminal device. The starting-up stage refers to a stage that after the server or the terminal equipment receives a CPU starting-up instruction, the CPU starts to be powered on.
In the embodiment of the present application, the BIOS chip monitors the current operating state of the CPU in real time, and specifically, if the BIOS chip monitors that a CPU boot instruction is triggered, it indicates that the current operating state of the CPU is in a boot stage. Therefore, the BIOS chip acquires that the current operating state of the CPU is in the boot stage. The BIOS chip judges whether the current running state of the CPU enters a starting-up stage by monitoring whether a CPU starting-up instruction is triggered, and the current running state of the CPU can be conveniently, quickly and accurately judged.
In the above embodiment, acquiring the current operating state of the CPU further includes:
judging whether the CPU is powered on or not in the starting-up stage;
and if so, the CPU enters the normal operation stage from the starting stage and acquires the current operation state of the CPU as the normal operation stage.
The normal operation stage is a stage in which the CPU is powered on and can operate normally, relative to the power-on stage and the power-off stage.
Specifically, if the BIOS chip monitors a CPU boot instruction, it acquires that the current operating state of the CPU is in a boot stage. Then, judging whether the CPU is powered on in a starting-up stage; if yes, the current running state of the CPU is obtained and enters a normal running stage from a starting stage. If not, the current running state of the CPU is obtained and kept at the starting stage.
In the starting-up stage, it may be determined whether the CPU is powered on, where after all power supplies and devices of the CPU are powered on, the CPU sends a power-on completion signal to the BIOS chip. After the BIOS chip receives the signal of power-on completion, the CPU can be judged to be powered on. If the BIOS chip does not receive the signal of power-on completion, the CPU is defaulted to be not powered on.
In the embodiment of the application, when the CPU is in a starting-up stage, the BIOS chip determines the current running state of the CPU by judging whether the CPU is powered on or not. Specifically, if the CPU is powered on in the startup phase, the current operating state of the CPU is acquired and the CPU enters the normal operating phase from the startup phase. The judgment mode is convenient and quick, and the BIOS chip can accurately judge the current running state of the CPU through the judgment mode.
In the above embodiment, acquiring the current operating state of the CPU further includes:
and if the CPU shutdown instruction is monitored in the normal operation stage, acquiring the current operation state of the CPU, and entering the shutdown stage from the normal operation stage.
The CPU power-off instruction may refer to a CPU power-off instruction triggered by an operation of a power-on/off button of the server or the terminal device. The shutdown phase refers to a phase that the CPU starts powering off after the server or the terminal device receives a CPU shutdown instruction.
Specifically, as shown in fig. 3, acquiring the current running state of the CPU includes:
step 310, judging whether a CPU starting instruction is monitored; if yes, go to step 320;
step 320, acquiring the current running state of the CPU as a starting-up stage;
step 330, judging whether the CPU is powered on in the starting-up stage; if yes, go to step 340; if not, go to step 320;
step 340, acquiring the current running state of the CPU, and entering a normal running stage from a starting stage;
step 350, judging whether a CPU shutdown instruction is monitored or not in a normal operation stage; if yes, go to step 360; if not, go to step 340;
and step 360, acquiring the current running state of the CPU, and entering a shutdown stage from a normal running stage.
In the embodiment of the application, in the normal operation stage, the BIOS chip determines whether the current operation state of the CPU enters the shutdown stage from the normal operation stage by judging whether a CPU shutdown instruction is monitored. The judgment mode is convenient and quick, and the BIOS chip can accurately judge the current running state of the CPU through the judgment mode.
In one embodiment, the first communication protocol is the I2C communication protocol and the second predetermined communication protocol is an open source communication protocol.
Wherein the first communication protocol is an I2C communication protocol. The I2C communication protocol is also called as I2C bus transmission protocol, I2C (Inter-integrated Circuit) bus supports short-distance communication between devices, I2C bus can be used as an interface between a processor CPU and some peripheral devices, and I2C bus only needs two signal lines to complete information exchange. Therefore, the application range of the I2C bus is very wide, and the bus can be adapted to various types of CPUs, but the transmission speed of the I2C bus is slow.
The second preset communication protocol is an open source communication protocol. The types of open source communication protocols are very rich, and different open source communication protocols can be adopted for different types of CPUs to carry out communication in general. The open source communication protocol includes but is not limited to PVID, TCP/IP, NETBEUI and IPX/SPX protocols, etc., and has a high transmission speed, but each protocol has a specific application environment suitable for the protocol. For example, some CPUs may communicate using the PVID communication protocol, but there is an incompatibility problem in the course of communicating using the PVID communication protocol, because the application environments are not completely consistent. For example, in the CPU power-on stage or the CPU power-off stage, an incompatibility problem may occur in which an electrical signal of a PIN corresponding to the PVID communication protocol on the CPU is ambiguous, which may cause the information transmitted by the CPU to other peripheral devices to be frequently erroneous and the information may not be accurately transmitted.
Although the transmission speed of the open source communication protocol is high, each protocol has a specific application environment suitable for the protocol. When the application environment cannot be adapted, an incompatibility problem occurs. In order to solve the problem of incompatibility generated when a PVID communication protocol is used for communication of a CPU, an I2C communication protocol with a wide application range is adopted in a starting-up stage or a shutdown stage of the CPU so as to meet the basic requirement of accurately transmitting information. And when the CPU is not in the startup stage and the shutdown stage, the PVID communication protocol is adopted to carry out high-speed and accurate information transmission. Therefore, by combining the I2C communication protocol and the PVID communication protocol, the problem of incompatibility generated when the CPU uses the PVID communication protocol can be solved.
In the embodiment of the application, the BIOS chip acquires the current running state of the CPU, and determines the current target communication protocol for the CPU to communicate with the power control chip from a preset communication protocol set according to the current running state of the CPU. And when the CPU is in a starting-up stage or a shutdown stage, the BIOS chip controls the CPU to communicate with the power supply control chip by adopting an I2C communication protocol. And when the CPU is in a normal operation stage, the BIOS chip controls the CPU to communicate with the power supply control chip by adopting an open source communication protocol. Therefore, the compatibility problem of the open source communication protocol is solved, and the data transmission speed is improved.
In one embodiment, as shown in fig. 4, step 240, the second preset communication protocol is a PVID communication protocol; according to the current running state of the CPU, determining a target communication protocol of the CPU for communicating with the power control chip from a preset communication protocol set, wherein the target communication protocol comprises the following steps:
in step 242, if the current operating state of the CPU is in the boot stage, it is determined that the target communication protocol is the I2C communication protocol from the preset communication protocol set.
And if the BIOS chip monitors a CPU starting instruction, acquiring the current running state of the CPU as being in a starting stage. The target communication protocol is determined to be the I2C communication protocol from the preset communication protocol set according to the current running state of the CPU. Namely, when the CPU is in a startup phase, the BIOS chip controls the CPU to output a voltage adjustment signal to the power control chip by using the I2C communication protocol, so as to control the power control chip to adjust the input voltage of the CPU according to the voltage adjustment signal. For example, in general, when the CPU is in a boot stage, the CPU is under a low load, and at this time, the voltage adjustment signal may be configured to decrease the input voltage according to the load condition of the CPU. After the CPU inputs the signal for lowering the input voltage to the power control chip through I2C communication, the power control chip may lower the input voltage of the CPU according to the signal for lowering the input voltage, thereby reducing the power consumption of the CPU.
In step 244, if the current operating state of the CPU enters the normal operating stage from the boot stage, it is determined that the target communication protocol is the PVID communication protocol.
The PVID communication protocol is Port-based VLAN ID, which indicates VLAN ID based on Port in network communication, and one Port may belong to multiple VLANs, but only one PVID may exist.
Judging whether the CPU is powered on or not by the BIOS chip in the starting-up stage; if yes, the current running state of the CPU is obtained and enters a normal running stage from a starting stage. At this time, the BIOS chip determines that the target communication protocol is the PVID communication protocol from a preset communication protocol set according to the current operating state of the CPU. Namely, when the CPU is in a normal operation stage, the BIOS chip controls the CPU to output a voltage regulation signal to the power control chip by adopting a PVID communication protocol so as to control the power control chip to regulate the input voltage of the CPU according to the voltage regulation signal. For example, when the CPU is in a normal operation stage, it is determined whether the load condition of the CPU is a high load, and if so, the voltage adjustment signal may be configured to increase the input voltage according to the load condition of the CPU. After the CPU inputs the signal for increasing the input voltage to the power supply control chip through PVID communication, the power supply control chip can increase the input voltage of the CPU according to the signal for increasing the input voltage, so that the normal operation of the CPU is met.
If the load condition of the CPU is judged to be low load, the voltage adjusting signal can be configured to be the reduced input voltage according to the load condition of the CPU. After the CPU inputs the signal for lowering the input voltage to the power control chip through the PVID communication, the power control chip can lower the input voltage of the CPU according to the signal for lowering the input voltage, thereby reducing the power consumption of the CPU.
Step 246, if the current running state of the CPU enters the shutdown phase from the normal running phase, it is determined that the target communication protocol is the I2C communication protocol.
And if the CPU shutdown instruction is monitored in the normal operation stage, acquiring the current operation state of the CPU, and entering the shutdown stage from the normal operation stage. The target communication protocol is determined to be the I2C communication protocol from the preset communication protocol set according to the current running state of the CPU. Namely, when the CPU is in a shutdown stage, the BIOS chip controls the CPU to output a voltage adjustment signal to the power supply control chip by using the I2C communication protocol, so as to control the power supply control chip to adjust the input voltage of the CPU according to the voltage adjustment signal. The specific voltage adjustment process is similar to the voltage adjustment process described above, and is not described herein again.
In the embodiment of the application, if the current running state of the CPU is in the boot stage, it is determined from the preset communication protocol set that the target communication protocol is the I2C communication protocol. And if the current running state of the CPU enters a normal running stage from a starting stage, determining that the target communication protocol is the PVID communication protocol. And if the current running state of the CPU enters a shutdown stage from a normal running stage, determining that the target communication protocol is the I2C communication protocol. In the startup stage or the shutdown stage of the CPU, an I2C communication protocol with a wide application range is adopted to meet the requirement of accurately transmitting information. And when the CPU is not in the startup stage and the shutdown stage, the PVID communication protocol is adopted to carry out high-speed and accurate information transmission. The problem that the electrical signal of the PIN corresponding to the PVID communication protocol on the CPU is ambiguous in the starting-up stage or the shutdown stage of the CPU is solved.
In one embodiment, as shown in fig. 5, if the current running state of the CPU is in the boot stage, sending a control instruction to the CPU includes:
step 262, sending the device address of the power control chip and the I2C address of the power control chip to the CPU.
If the current running state of the CPU is in a starting-up stage, the BIOS chip determines that a target communication protocol is an I2C communication protocol from a preset communication protocol set and sends a control instruction to the CPU. The BIOS chip acquires the device address of the power control chip and the I2C address of the power control chip in advance, and then sends the device address of the power control chip and the I2C address of the power control chip to the CPU.
And step 264, sending a control instruction to the CPU to control the CPU to establish I2C communication between the CPU and the power supply control chip according to the equipment address of the power supply control chip and the I2C address of the power supply control chip, and to control the CPU to output a voltage regulation signal to the power supply control chip through I2C communication.
Specifically, after receiving the device address of the power control chip and the I2C address of the power control chip, the CPU can establish I2C communication between the CPU and the power control chip. At this time, the CPU can output a voltage adjustment signal to the power control chip through I2C communication.
In the embodiment of the application, after determining that the target communication protocol is the I2C communication protocol, the BIOS chip sends the device address of the power control chip and the I2C address of the power control chip to the CPU. The CPU can establish I2C communication between the CPU and the power control chip based on the device address of the power control chip and the I2C address of the power control chip. At this time, the CPU can output a voltage adjustment signal to the power control chip through I2C communication. The I2C communication protocol with wider application range is adopted in the CPU startup stage or the CPU shutdown stage to meet the requirement of accurately transmitting information.
In one embodiment, as shown in fig. 6, if the current operating state of the CPU enters the normal operating stage from the boot stage, the sending a control instruction to the CPU includes:
step 620, modifying the value of the register of the power control chip to be a first value, wherein the first value is used for starting a PVID interface of the power control chip;
and step 640, sending a control instruction to the CPU to control the CPU to switch the I2C communication between the CPU and the power supply control chip to PVID communication based on the PVID interface, and to control the CPU to output a voltage regulation signal to the power supply control chip through the PVID communication.
Specifically, if the current running state of the CPU enters the normal running stage from the boot stage, the BIOS chip determines that the target communication protocol is the PVID communication protocol from the preset communication protocol set, and sends a control instruction to the CPU. The power control chip is preset with a register, and the value of the register is used for controlling the opening or closing of the PVID interface of the power control chip.
At this time, the BIOS chip modifies the value of the register of the power control chip to a first value, and the first value is used for starting the PVID interface of the power control chip and starting the PVID interface of the power control chip. Then, the CPU switches the I2C communication between the CPU and the power supply control chip to PVID communication based on the PVID interface, and outputs a voltage adjustment signal to the power supply control chip through the PVID communication.
Fig. 7A is a schematic diagram of an interface on a power control chip. The power control chip 720 has a PVID interface 722 and an I2C interface 724. The power control chip 720 may connect with the PVID interface on the CPU through the PVID interface 722 to establish PVID communication. The power control chip can also be connected with an I2C interface on the CPU through an I2C interface 724 to establish I2C communication.
Fig. 7B is a schematic diagram illustrating two communication connections established between the CPU and the power control chip. Wherein, an I2C communication connection and a PVID communication connection are established between the CPU 740 and the power control chip 720.
In the embodiment of the application, after the BIOS chip determines that the target communication protocol is the PVID communication protocol, the BIOS chip modifies the value of the register of the power control chip to be the first value, and turns on the PVID interface of the power control chip. The CPU switches the I2C communication between the CPU and the power supply control chip to PVID communication based on the PVID interface, and outputs a voltage adjustment signal to the power supply control chip through the PVID communication. The method can realize high-speed and accurate information transmission by adopting the PVID communication protocol when the CPU is not in the startup stage and the shutdown stage.
In one embodiment, as shown in fig. 6, if the current operation state of the CPU enters the shutdown phase from the normal operation phase, sending a control instruction to the CPU includes:
step 660, modifying the value of the register of the power control chip from a first value to a second value, wherein the second value is used for closing the PVID interface of the power control chip;
and step 680, sending a control instruction to the CPU to control the CPU to switch the PVID communication between the CPU and the power supply control chip to I2C communication, and to output a voltage adjusting signal to the power supply control chip through I2C communication.
In the embodiment of the application, after determining that the target communication protocol is the I2C communication protocol, the BIOS chip modifies the value of the register of the power control chip from the first value to the second value, and closes the PVID interface of the power control chip. At this time, the CPU can output a voltage adjustment signal to the power control chip through the I2C communication established as it is. The I2C communication protocol with wider application range is adopted in the CPU startup stage or the CPU shutdown stage to meet the requirement of accurately transmitting information.
In one embodiment, a voltage regulation method is provided and applied to a server or a terminal device. The application environment of the voltage regulation method includes a server 100, and the server 100 includes a BIOS chip 120, a CPU140, and a power control chip 160. As shown in fig. 8, includes:
step 820, receiving a control instruction determined by the BIOS chip according to the running state of the CPU; the running state comprises any one stage of the CPU currently in a starting stage, a shutdown stage and a normal running stage.
The CPU receives a control instruction sent by the BIOS chip, wherein the control instruction is a control instruction generated by determining a target communication protocol of the CPU for communicating with the power control chip from a preset communication protocol set according to the current running state of the CPU by the BIOS chip.
Step 840, outputting a voltage regulation signal to the power control chip by adopting a target communication protocol according to the control instruction; the target communication protocol is determined by the BIOS from a preset communication protocol set based on the running state of the CPU; the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined for the power-on phase and the power-off phase from the plurality of communication protocols is different from a second communication protocol determined for the normal operation phase from the plurality of communication protocols.
And after receiving the control instruction sent by the BIOS chip, the CPU outputs a voltage regulation signal to the power control chip by adopting a target communication protocol according to the control instruction. And a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase. Namely, the CPU adopts a first communication protocol to output a voltage regulating signal to the power control chip in a starting-up stage and a shutdown stage. And the CPU outputs a voltage regulation signal to the power supply control chip by adopting a second communication protocol in the normal operation stage. The first communication protocol and the second communication protocol are two different communication protocols.
And step 860, controlling the power control chip to adjust the input voltage of the CPU according to the voltage adjusting signal.
After the CPU sends the voltage adjusting signal to the power supply control chip, the power supply control chip receives the voltage adjusting signal and can adjust the input voltage of the CPU according to the voltage adjusting signal.
In the embodiment of the application, the CPU receives a control instruction determined by the BIOS chip according to the running state of the CPU, and outputs a voltage regulation signal to the power control chip by adopting a target communication protocol according to the control instruction. So that the power supply control chip can adjust the input voltage of the CPU according to the voltage adjusting signal after receiving the voltage adjusting signal. The CPU outputs a voltage regulation signal to the power control chip by adopting a first communication protocol in a starting-up stage and a shutdown stage. And the CPU outputs a voltage regulation signal to the power supply control chip by adopting a second communication protocol in the normal operation stage. The first communication protocol and the second communication protocol are two different communication protocols. Therefore, different communication protocols are adopted for communication in different states of the CPU, and the problem that a voltage adjusting signal output to a power supply control chip by the CPU is inaccurate frequently in the starting-up stage or the shutdown stage of the CPU by adopting an open source communication protocol in the prior art is solved. Finally, accurate dynamic voltage regulation of the CPU can be realized.
In one embodiment, as shown in fig. 9, there is provided a voltage regulating device 900 comprising:
an operation state obtaining module 920, configured to obtain a current operation state of the CPU; the running state comprises any one stage of a starting stage, a shutdown stage and a normal running stage of the CPU;
a target communication protocol determining module 940, configured to determine, according to the current operating state of the CPU, a target communication protocol for the CPU to currently communicate with the power control chip from a preset communication protocol set; the communication protocol set comprises a plurality of communication protocols, and a first communication protocol determined for a startup phase and a shutdown phase in the plurality of communication protocols is different from a second communication protocol determined for a normal operation phase in the plurality of communication protocols;
a control instruction sending module 960, configured to send a control instruction to the CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting a target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
In an embodiment, the running state obtaining module 920 is further configured to obtain, if a CPU boot instruction is monitored, that the current running state of the CPU is in a boot stage.
In an embodiment, the running state obtaining module 920 is further configured to determine whether the CPU is powered on in the boot stage;
if yes, the CPU enters a normal operation stage from the starting stage, and the current operation state of the CPU is acquired as being in the normal operation stage.
In an embodiment, the running state obtaining module 920 is further configured to obtain, if a CPU shutdown instruction is monitored in the normal running stage, that the current running state of the CPU enters the shutdown stage from the normal running stage.
In one embodiment, the first communication protocol is the I2C communication protocol and the second predetermined communication protocol is an open source communication protocol.
In one embodiment, the second preset communication protocol is a PVID communication protocol; a target communication protocol determining module 940, configured to determine that the target communication protocol is the I2C communication protocol from a preset communication protocol set if the current operation state of the CPU is in the boot stage; if the current running state of the CPU enters a normal running stage from a starting stage, determining that a target communication protocol is a PVID communication protocol; and if the current running state of the CPU enters a shutdown stage from a normal running stage, determining that the target communication protocol is the I2C communication protocol.
In one embodiment, if the current operating state of the CPU is in the boot stage, the control instruction sending module 960 is further configured to send the device address of the power control chip and the I2C address of the power control chip to the CPU; and sending a control command to the CPU to control the CPU to establish I2C communication between the CPU and the power supply control chip according to the equipment address of the power supply control chip and the I2C address of the power supply control chip, and control the CPU to output a voltage regulation signal to the power supply control chip through I2C communication.
In one embodiment, if the current operating state of the CPU enters the normal operating stage from the boot stage, the control instruction sending module 960 is further configured to modify the value of the register of the power control chip to a first value, where the first value is used to turn on the PVID interface of the power control chip; the control instruction is sent to the CPU to control the CPU to switch the I2C communication between the CPU and the power supply control chip into PVID communication based on a PVID interface, and control the CPU to output a voltage adjusting signal to the power supply control chip through the PVID communication.
In an embodiment, if the current operation state of the CPU enters the shutdown phase from the normal operation phase, the control instruction sending module 960 is further configured to modify the value of the register of the power control chip from the first value to a second value, where the second value is used to close the PVID interface of the power control chip; the control instruction is sent to the CPU to control the CPU to switch the PVID communication between the CPU and the power supply control chip into I2C communication, and to control the CPU to output a voltage adjusting signal to the power supply control chip through I2C communication.
In one embodiment, there is provided a voltage regulating device, further comprising:
the control instruction receiving module is used for receiving a control instruction determined by the BIOS chip according to the running state of the CPU; the running state comprises any one stage of a starting stage, a shutdown stage and a normal running stage of the CPU;
the voltage regulation signal sending module is used for outputting a voltage regulation signal to the power supply control chip by adopting a target communication protocol according to the control instruction; the target communication protocol is determined by the BIOS from a preset communication protocol set based on the running state of the CPU; the communication protocol set comprises a plurality of communication protocols, and a first communication protocol determined for a startup phase and a shutdown phase from the plurality of communication protocols is different from a second communication protocol determined for a normal operation phase from the plurality of communication protocols;
and the control module is used for controlling the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
The division of the modules in the voltage regulating device is merely for illustration, and in other embodiments, the voltage regulating device may be divided into different modules as needed to complete all or part of the functions of the voltage regulating device.
Fig. 10 is a schematic diagram of an internal configuration of a server in one embodiment. As shown in fig. 10, the server includes a processor and a memory connected by a system bus. Wherein, the processor is used for providing calculation and control capability and supporting the operation of the whole server. The memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The computer program can be executed by a processor for implementing a voltage regulation method provided in the following embodiments. The internal memory provides a cached execution environment for the operating system computer programs in the non-volatile storage medium. The server may be a mobile phone, a tablet computer, or a personal digital assistant or a wearable device, etc.
The implementation of each module in the voltage regulation apparatus provided in the embodiment of the present application may be in the form of a computer program. The computer program may be run on a terminal or a server. The program modules formed by the computer program may be stored on the memory of the terminal or the server. Which when executed by a processor, performs the steps of the method described in the embodiments of the present application.
The embodiment of the application also provides a computer readable storage medium. One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the steps of the voltage regulation method.
A computer program product containing instructions which, when run on a computer, cause the computer to perform a voltage regulation method.
Any reference to memory, storage, databases, or other media used by embodiments of the application may include non-volatile and/or volatile memory. Suitable non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Rambus (Rambus) direct RAM (RDRAM), direct bused dynamic RAM (DRDRAM), and bused dynamic RAM (RDRAM).
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method of voltage regulation, comprising:
acquiring the current running state of the CPU; the running state comprises any one of a starting stage, a shutdown stage and a normal running stage of the CPU;
determining a target communication protocol of the CPU which is currently communicated with a power control chip from a preset communication protocol set according to the current running state of the CPU; wherein the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase;
sending a control instruction to the CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting the target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
2. The method of claim 1, wherein the obtaining the current running state of the CPU further comprises:
judging whether the CPU is powered on in the starting-up stage;
and if so, the CPU enters the normal operation stage from the starting stage and acquires the current operation state of the CPU as the normal operation stage.
3. The method according to claim 1 or 2, wherein the first communication protocol is an I2C communication protocol, and the second predetermined communication protocol is an open source communication protocol.
4. The method according to claim 3, wherein the second predetermined communication protocol is a PVID communication protocol; the determining, from a preset communication protocol set, a target communication protocol for the current communication between the CPU and the power control chip according to the current operating state of the CPU includes:
if the current running state of the CPU is in the starting-up stage, determining that the target communication protocol is an I2C communication protocol from a preset communication protocol set;
if the current running state of the CPU enters the normal running stage from the starting stage, determining that the target communication protocol is a PVID communication protocol;
and if the current running state of the CPU enters the shutdown stage from the normal running stage, determining that the target communication protocol is the I2C communication protocol.
5. The method according to claim 4, wherein if the current running state of the CPU is in the boot stage, the sending the control instruction to the CPU comprises:
sending the equipment address of the power control chip and the I2C address of the power control chip to the CPU;
the method comprises the steps of sending a control instruction to a CPU to control the CPU to establish I2C communication between the CPU and a power supply control chip according to an equipment address of the power supply control chip and an I2C address of the power supply control chip, and controlling the CPU to output a voltage regulation signal to the power supply control chip through the I2C communication.
6. The method of claim 4, wherein if the current operating state of the CPU enters the normal operating phase from the boot phase, the sending the control instruction to the CPU comprises:
modifying the numerical value of a register of the power control chip into a first value, wherein the first value is used for starting a PVID interface of the power control chip;
the control instruction is sent to the CPU to control the CPU to switch the I2C communication between the CPU and the power supply control chip into PVID communication based on a PVID interface, and control the CPU to output a voltage adjusting signal to the power supply control chip through the PVID communication.
7. The method according to claim 4, wherein if the current operating state of the CPU enters the shutdown phase from the normal operation phase, the sending a control instruction to the CPU comprises:
modifying the value of the register of the power supply control chip from a first value to a second value, wherein the second value is used for closing a PVID interface of the power supply control chip;
and sending a control instruction to the CPU to control the CPU to switch the PVID communication between the CPU and the power supply control chip into I2C communication, and control the CPU to output a voltage regulation signal to the power supply control chip through the I2C communication.
8. A voltage regulation device, comprising:
the running state acquisition module is used for acquiring the current running state of the CPU; the running state comprises any one of a starting stage, a shutdown stage and a normal running stage of the CPU;
the target communication protocol determining module is used for determining a target communication protocol of the CPU which is currently communicated with the power control chip from a preset communication protocol set according to the current running state of the CPU; wherein the set of communication protocols includes a plurality of communication protocols, and a first communication protocol determined from the plurality of communication protocols for the power-on phase and the power-off phase is different from a second communication protocol determined from the plurality of communication protocols for the normal operation phase;
the control instruction sending module is used for sending a control instruction to the CPU; the control instruction is used for controlling the CPU to output a voltage regulation signal to the power supply control chip by adopting the target communication protocol so as to control the power supply control chip to regulate the input voltage of the CPU according to the voltage regulation signal.
9. A server comprising a memory and a processor, the memory having stored thereon a computer program, wherein the computer program, when executed by the processor, causes the processor to perform the steps of the voltage regulation method according to any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the voltage regulation method according to any one of claims 1 to 7.
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