CN209015256U - A kind of 1553B processing system based on FPGA - Google Patents
A kind of 1553B processing system based on FPGA Download PDFInfo
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- CN209015256U CN209015256U CN201822157679.1U CN201822157679U CN209015256U CN 209015256 U CN209015256 U CN 209015256U CN 201822157679 U CN201822157679 U CN 201822157679U CN 209015256 U CN209015256 U CN 209015256U
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Abstract
The 1553B processing system based on FPGA that the utility model discloses a kind of, including the preparation chip of FPGA, the FPGA are the NOR FLASH of 64M byte, for storing FPGA loading procedure；It further include the 20MHz crystal oscillator under the global clock for being mounted to FPGA；Further include CAT811 reset chip, generates electrification reset for FPGA.The utility model is by FPGA powerful operation, control ability, logical resource abundant, in conjunction with 1553B bussing technique, while providing 1553B bus communication function, by the control of FPGA, provides the interface of easy control and access 1553B bus system.
Description
Technical field
The utility model belongs to the technical field of 1553B communication, and in particular to a kind of 1553B processing system based on FPGA
System.
Background technique
1553B bus standard be have the U.S. develop signal multiplex system a kind of standard, by the exploitation of many years,
It improves and verifies, have become a kind of international standard.Currently, 1553B bus standard is widely used to airplane synthetic avionics system
System, armored vehicle Integrated Electronic System, the fields such as the Aeronautics and Astronautics such as marine integrated electronic system, ship, weapons, electronics.
It is applied to the 1553B bus system in Aeronautics and Astronautics field at present, processor+protocol processing chip is widely used
Mode, application cost is high, and it is understood that the protocol contents of large amount of complex when use.With flying for Aeronautics and Astronautics electronic technology
Speed development, no matter military domain or civil field for the design of easy 1553B bus system and research and development demand more
Urgently.
Utility model content
The 1553B processing system based on FPGA that the purpose of this utility model is to provide a kind of, passes through the powerful fortune of FPGA
Calculation, control ability, logical resource abundant while providing 1553B bus communication function, lead in conjunction with 1553B bussing technique
The control for crossing FPGA provides the interface of easy control and access 1553B bus system.
What the utility model was mainly achieved through the following technical solutions: a kind of 1553B processing system based on FPGA, packet
FPGA is included, the FPGA's prepares the NOR FLASH that chip is 64M byte, for storing FPGA loading procedure；It further include carry
20MHz crystal oscillator under to the global clock of FPGA；Further include CAT811 reset chip, generates electrification reset for FPGA.
The utility model leads to for storing the loading procedure of FPGA in use, by the setting of NOR FLASH
Crystal oscillator carry is crossed under the global clock of FPGA, the operation clock as 1553B bus system, by the setting of reset chip,
Guarantee to start to work after putting in 1553B bus system from initialization, the accuracy of the processing to data is avoided to impact；It is described
Reset chip includes homing light module, mode control module, an interface connection mode of the homing light module
Control module, the mode control module connect homing light module, another interface difference of the homing light module
Connect 1553B processing module, FIFO processing module, RAM processing module；After 1553B bus system powers on, asynchronous reset signal is defeated
Enter in homing light module, reset signal 1 and reset signal are converted for asynchronous reset input by homing light module
2, reset signal 2 inputs 1553B processing module, FIFO processing module, RAM processing module respectively, so that 1553B processing module,
FIFO processing module, RAM processing module are resetted, and reset signal 1 is input in mode control module, and by reset signal 1
It is converted into 2 resetting pulse of reset signal, and 2 resetting pulse of reset signal is re-entered in homing light module, is FPGA
Electrification reset is generated, guarantees to start to work after 1553B bus system powers on from initialization.
The utility model has powerful processing and control function, faster to 1553B by the setting of FPGA processor
The processing of agreement.
In order to preferably realize the utility model, further, the Sparten3 Series FPGA chip based on Xilinx is mentioned
The storage of processing and data for 1553B bus protocol；And the HI-1567 chip based on 1553B switching technology provides 1553B electricity
The interchange channel of gentle Transistor-Transistor Logic level.Contain enough logical resources and RAM resource, logic money in the utility model fpga chip
Source is used for the processing of 1553B bus protocol, and RAM resource is used for the storage of 1553B bus protocol.
In order to preferably realize the utility model, further, the FPGA further includes fifo interface, for it is external
Data exchange channel；The processing system is exchanged by fifo interface with 1553B bus data.
The utility model is separately connected 1553B processing system by fifo interface and the mutual of external data interchange channel connects
Mouthful, the data exchange with 1553B bus, while the setting of fifo interface can be completed by access fifo interface, by 1553B complexity
Protocol package be converted into simple serial data stream, so that rear end is more easily handled 1553B information.
The utility model enables complex protocol packet in 1553B bus system by the setting of FIFO processing module
Faster by back-end processing, speed up processing improves the efficiency of information transmitting.
In order to preferably realize the utility model, further, the FPGA further includes BRAM, to store 1553B bus
Data.The utility model configures the hair of interface for memory module for storing 1553B bus data by the setting of BRAM
Send message.
In order to preferably realize the utility model, further, the fifo interface operating rate is 320Mbps.This reality
320Mbps is reached with the working efficiency of novel fifo interface, it is ensured that has the sufficient time for back-end processing 1553B information.
In order to preferably realize the utility model, further, the FPGA includes 2bit scheme control port, for controlling
1553B bus system processed switches BC, RT, BM mode；It further include 2 5bit remote terminal address control ports.
The utility model is provided with 1553B process kernel, has A/B double- redundancy, and has BC, RT, BM function, leads to
It crosses 2bit pattern configurations port and configures BC mode for 1553B bus system, be written into fifo interface by BC transmission frame format
One group of BC data, can be realized the transmission of BC data, and after BC message is sent completely, 1553B bus system will be connect by FIFO
Complete 1553B bus message, the status information including command word, status word, data word and this message is written in mouth to the back-end.
BC pattern configurations process: selection BC mode carries out reset configuration, resets judgement, and when reset is determined as no, return is re-started
It resets configuration to be initially configured when reset is judged to being, and successively carries out configuration control register, configuration operation note, configuration
Interrupt mask register, configuration interrupt enable register, configuration control block pointer, configuration data block pointer, enabled BC, BC configuration
It completes.
RT mode is configured by 1553B bus system by 2bit pattern configurations port, port is configured by terminal address
The address RT of configuration module sends RT by external BC and receives message, and 1553B bus system first can be to external BC transmission state
Then complete 1553B bus message will be written to the back-end by fifo interface in word, including command word, status word, data word and
The status information of this message；RT mode is configured by 1553B bus system by 2bit pattern configurations port, by terminal
Location configures the address RT of port configuration module, is written by fifo interface into the subaddressing of RT and sends message, passes through external BC
It sends RT and sends message, then 1553B bus system can will be connect first to external BC transmission state word and data word by FIFO
Complete 1553B bus message, the status information including command word, status word, data word and this message is written in mouth to the back-end.
BT pattern configurations process: selection BT mode carries out reset configuration, resets judgement, and when reset is determined as no, return is re-started
Reset configuration, reset is when being judged to being, be successively initially configured by step sequence, configuration control register, configuration operation note,
Configure interrupt mask register, configuration interrupt enable register, configuration control block pointer, configuration status word, enabled RT, configuration
RAM reception area configures Sub(n as n=0) control word, configuration Sub(n) data A, B Buffer, configuration Sub(n) broadcast number
According to Buffer；Then whether detection N is equal to 31, if detect as n+1, imports configuration Sub(n again) control word matched
Set, if detection is qualified, continues configuration and receive Sub(n) control word, as n=0, configuration Sub(n) control word, configuration Sub(n)
Data A, B Buffer, configuration Sub(n) broadcast data Buffer, whether detection N is equal to 31, if detecting as n+1, again
Configure Sub(n) control word is that RT configuration is completed if being detected as.
BM mode is configured by 1553B bus system by 2bit pattern configurations port, is sent out by external BC to external RT
RT is sent to receive message, complete 1553B bus message, including life will be written to the back-end in 1553B bus system by fifo interface
Enable the status information of word, status word, data word and this message.BM pattern configurations process: selection BM mode reset and matches
Set, reset judgement, when reset is determined as no, return re-starts reset configuration, and reset is when being judged to being, by step sequence successively into
Row is initially configured, configuration control register, configuration operation note, configuration interrupt mask register, configures and interrupt enabled deposit
Device, configuration control block pointer, configuration data block pointer, item number is monitored in configuration, filter 1 is monitored in configuration, filter is monitored in configuration
2, BM, BM configuration is enabled to complete.
The utility model passes through the setting of pattern configurations interface, so that 1553B bus system can flexibly be controlled by rear end,
Can it is easy, quickly realize multi-functional 1553B bus system switching；By the setting of pattern configurations port, for controlling
1553B bus system switches over, and the setting of port is configured by remote terminal address, when 1553B bus system is in RT mould
When formula, the terminal address of internal 2 RT is controlled.
The utility model has the beneficial effects that
(1) the preparation chip of the FPGA is the NOR FLASH of 64M byte, for storing FPGA loading procedure；Further include
The 20MHz crystal oscillator being mounted under the global clock of FPGA；Further include CAT811 reset chip, generates electrification reset for FPGA.This
Utility model has powerful processing and control function, faster to the place of 1553B agreement by the setting of FPGA processor
Reason.
(2) the Sparten3 Series FPGA chip based on Xilinx provides the processing of 1553B bus protocol and depositing for data
Storage；And the HI-1567 chip based on 1553B switching technology provides the interchange channel of 1553B level and Transistor-Transistor Logic level.This is practical new
Contain enough logical resources and RAM resource in type fpga chip, logical resource is used for the processing of 1553B bus protocol, RAM money
Source is used for the storage of 1553B bus protocol.
(3) FPGA further includes fifo interface, for the data exchange channel with outside；The processing system passes through
Fifo interface is exchanged with 1553B bus data.The utility model passes through the setting of FIFO processing module, so that the total linear system of 1553B
Complex protocol packet in system can be faster by back-end processing, and speed up processing improves the efficiency of information transmitting.
(4) the fifo interface operating rate is 320Mbps.The working efficiency of the fifo interface of the utility model reaches
320Mbps, it is ensured that have the sufficient time for back-end processing 1553B information.
(5) FPGA includes 2bit scheme control port, for controlling 1553B bus system switching BC, RT, BM mould
Formula；It further include 2 5bit remote terminal address control ports.The utility model passes through the setting of pattern configurations interface, so that
1553B bus system can flexibly be controlled by rear end, can it is easy, quickly realize multi-functional 1553B bus system switching；It is logical
The setting for crossing pattern configurations port is switched over for controlling 1553B bus system, configures port by remote terminal address
Setting controls the terminal address of internal 2 RT when 1553B bus system is in RT mode.
Detailed description of the invention
Fig. 1 is the design frame chart of the utility model；
Fig. 2 is the reset unit design frame chart of the utility model；
Fig. 3 is BC pattern configurations flow chart；
Fig. 4 is RT pattern configurations flow chart；
Fig. 5 is BM pattern configurations flow chart；
Fig. 6 is 1553B protocol processes operation schematic diagram.
Specific embodiment
Embodiment 1:
A kind of 1553B processing system based on FPGA, as shown in Figure 1 and Figure 2, including the preparation chip of FPGA, the FPGA
For the NOR FLASH of 64M byte, for storing FPGA loading procedure；It further include the 20MHz under the global clock for being mounted to FPGA
Crystal oscillator；Further include CAT811 reset chip, generates electrification reset for FPGA.
The utility model leads to for storing the loading procedure of FPGA in use, by the setting of NOR FLASH
Crystal oscillator carry is crossed under the global clock of FPGA, the operation clock as 1553B bus system, by the setting of reset chip,
Guarantee to start to work after putting in 1553B bus system from initialization, the accuracy of the processing to data is avoided to impact；It is described
Reset chip includes homing light module, mode control module, an interface connection mode of the homing light module
Control module, the mode control module connect homing light module, another interface difference of the homing light module
Connect 1553B processing module, FIFO processing module, RAM processing module；After 1553B bus system powers on, asynchronous reset signal is defeated
Enter in homing light module, reset signal 1 and reset signal are converted for asynchronous reset input by homing light module
2, reset signal 2 inputs 1553B processing module, FIFO processing module, RAM processing module respectively, so that 1553B processing module,
FIFO processing module, RAM processing module are resetted, and reset signal 1 is input in mode control module, and by reset signal 1
It is converted into 2 resetting pulse of reset signal, and 2 resetting pulse of reset signal is re-entered in homing light module, is FPGA
Electrification reset is generated, guarantees to start to work after 1553B bus system powers on from initialization.
The utility model has powerful processing and control function, faster to 1553B by the setting of FPGA processor
The processing of agreement.
Embodiment 2:
The present embodiment advanced optimizes on the basis of embodiment 1, the Sparten3 Series FPGA chip based on Xilinx
The processing of 1553B bus protocol and the storage of data are provided；And the HI-1567 chip based on 1553B switching technology provides 1553B
The interchange channel of level and Transistor-Transistor Logic level.Contain enough logical resources and RAM resource, logic in the utility model fpga chip
Resource is used for the processing of 1553B bus protocol, and RAM resource is used for the storage of 1553B bus protocol.
The other parts of the present embodiment are same as Example 1, and so it will not be repeated.
Embodiment 3:
The present embodiment advanced optimizes on the basis of embodiment 2, as shown in fig. 6, the FPGA further includes fifo interface,
For the data exchange channel with outside；The processing system is exchanged by fifo interface with 1553B bus data.
The utility model is separately connected 1553B processing system by fifo interface and the mutual of external data interchange channel connects
Mouthful, the data exchange with 1553B bus, while the setting of fifo interface can be completed by access fifo interface, by 1553B complexity
Protocol package be converted into simple serial data stream, so that rear end is more easily handled 1553B information.
The utility model enables complex protocol packet in 1553B bus system by the setting of FIFO processing module
Faster by back-end processing, speed up processing improves the efficiency of information transmitting.
The other parts of the present embodiment are identical as above-described embodiment 2, and so it will not be repeated.
Embodiment 4:
The present embodiment advanced optimizes on the basis of embodiment 3, and the FPGA further includes BRAM, total to store 1553B
Line number evidence；The fifo interface operating rate is 320Mbps.
The utility model configures interface for memory module for storing 1553B bus data by the setting of BRAM
Send message；The working efficiency of fifo interface reaches 320Mbps, it is ensured that has the sufficient time for back-end processing 1553B information.
The other parts of the present embodiment are identical as above-described embodiment 3, and so it will not be repeated.
Embodiment 5:
The present embodiment advanced optimizes on the basis of embodiment 1, and as shown in Figure 3-Figure 5, the FPGA includes 2bit mould
Formula control port, for controlling 1553B bus system switching BC, RT, BM mode；It further include 2 5bit remote terminal address controls
Port processed.
The utility model is provided with 1553B process kernel, has A/B double- redundancy, and has BC, RT, BM function, leads to
It crosses 2bit pattern configurations port and configures BC mode for 1553B bus system, be written into fifo interface by BC transmission frame format
One group of BC data, can be realized the transmission of BC data, and after BC message is sent completely, 1553B bus system will be connect by FIFO
Complete 1553B bus message, the status information including command word, status word, data word and this message is written in mouth to the back-end；
RT mode is configured by 1553B bus system by 2bit pattern configurations port, port is configured by terminal address
The address RT of configuration module sends RT by external BC and receives message, and 1553B bus system first can be to external BC transmission state
Then complete 1553B bus message will be written to the back-end by fifo interface in word, including command word, status word, data word and
The status information of this message；RT mode is configured by 1553B bus system by 2bit pattern configurations port, by terminal
Location configures the address RT of port configuration module, is written by fifo interface into the subaddressing of RT and sends message, passes through external BC
It sends RT and sends message, then 1553B bus system can will be connect first to external BC transmission state word and data word by FIFO
Complete 1553B bus message, the status information including command word, status word, data word and this message is written in mouth to the back-end；
BM mode is configured by 1553B bus system by 2bit pattern configurations port, is sent out by external BC to external RT
RT is sent to receive message, complete 1553B bus message, including life will be written to the back-end in 1553B bus system by fifo interface
Enable the status information of word, status word, data word and this message.
The utility model passes through the setting of pattern configurations interface, so that 1553B bus system can flexibly be controlled by rear end,
Can it is easy, quickly realize multi-functional 1553B bus system switching；By the setting of pattern configurations port, for controlling
1553B bus system switches over, and the setting of port is configured by remote terminal address, when 1553B bus system is in RT mould
When formula, the terminal address of internal 2 RT is controlled.
The other parts of the present embodiment are same as Example 1, and so it will not be repeated.
The above is only the preferred embodiment of the utility model, not does limit in any form to the utility model
System, any simple modification made by the above technical examples according to the technical essence of the present invention, equivalent variations, each falls within
Within the protection scope of the utility model.
Claims (6)
1. a kind of 1553B processing system based on FPGA, which is characterized in that including FPGA, the preparation chip of the FPGA is 64M
The NOR FLASH of byte, for storing FPGA loading procedure；It further include the 20MHz crystal oscillator under the global clock for being mounted to FPGA；
Further include CAT811 reset chip, generates electrification reset for FPGA.
2. a kind of 1553B processing system based on FPGA according to claim 1, which is characterized in that based on Xilinx's
Sparten3 Series FPGA chip provides the processing of 1553B bus protocol and the storage of data；And based on 1553B switching technology
The interchange channel of HI-1567 chip offer 1553B level and Transistor-Transistor Logic level.
3. a kind of 1553B processing system based on FPGA according to claim 1, which is characterized in that the FPGA is also wrapped
Fifo interface is included, for the data exchange channel with outside；The processing system is handed over by fifo interface and 1553B bus data
It changes.
4. a kind of 1553B processing system based on FPGA according to claim 3, which is characterized in that the FPGA is also wrapped
BRAM is included, to store 1553B bus data.
5. a kind of 1553B processing system based on FPGA according to claim 4, which is characterized in that the fifo interface
Operating rate is 320Mbps.
6. a kind of 1553B processing system based on FPGA according to claim 1-5, which is characterized in that described
FPGA includes 2bit scheme control port, for controlling 1553B bus system switching BC, RT, BM mode；It further include 2 5bit
Remote terminal address control port.
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| CN201822157679.1U CN209015256U (en) | 2018-12-21 | 2018-12-21 | A kind of 1553B processing system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116224877A (en) * | 2023-03-14 | 2023-06-06 | 中国科学院空间应用工程与技术中心 | Remote terminal for bus adaptation, bus adaptation system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116224877A (en) * | 2023-03-14 | 2023-06-06 | 中国科学院空间应用工程与技术中心 | Remote terminal for bus adaptation, bus adaptation system and method |
| CN116224877B (en) * | 2023-03-14 | 2023-11-07 | 中国科学院空间应用工程与技术中心 | Remote terminal for bus adaptation, bus adaptation system and method |
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Address after: 610000 No.6, Wuke East 3rd road, Wuhou e-commerce industry functional zone management committee, Wuhou District, Chengdu City, Sichuan Province Patentee after: Chengdu nengtong Technology Co.,Ltd. Address before: 610000 402, building 13, No.17, Wuxing 2nd Road, Wuhou District, Chengdu, Sichuan Province Patentee before: CHENGDU LAND TOP TECHNOLOGY CO.,LTD. |
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