CN208939000U - A kind of pole array n through-hole interdigital electrode packed LED chip - Google Patents
A kind of pole array n through-hole interdigital electrode packed LED chip Download PDFInfo
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- CN208939000U CN208939000U CN201822024668.6U CN201822024668U CN208939000U CN 208939000 U CN208939000 U CN 208939000U CN 201822024668 U CN201822024668 U CN 201822024668U CN 208939000 U CN208939000 U CN 208939000U
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Abstract
The utility model discloses a kind of pole array n through-hole interdigital electrode packed LED chips, belong to technical field of semiconductor luminescence, it from bottom to top successively include substrate, n-type semiconductor layer, luminescent layer and p-type semiconductor layer, current extending is equipped in p-type semiconductor layer, it is equipped with dielectric isolation layer on current extending, the pole the n through-hole of rectangular array distribution is equipped on dielectric isolation layer；On dielectric isolation layer side by side be equipped with the pole multiple row p through-hole perhaps the pole the p through slot pole the p through-hole perhaps the pole p through slot extend to from top to bottom current extending in left-right direction one column the pole p through-hole or the pole p through slot with one arrange the pole n through-hole be alternately arranged and form interdigital structure；It realizes the extremely conductive the continuity of a series of blocks of the pole p conductive column or p to be electrically connected and form p-electrode, n-electrode and p-electrode are in interdigitated electrode structure form；To reduce the loss of LED efficient lighting area, improve LED luminance under the premise of not influencing current expansion performance.
Description
Technical field
The utility model belongs to technical field of semiconductor luminescence, in particular to a kind of interdigital electricity of the pole array n through-hole
Pole packed LED chip.
Background technique
Light emitting diode (light emitting diodes, LEDs) is a kind of based on made of electroluminescent principle half
Conductor luminescent device.Semiconductor lighting based on great power LED is acknowledged as illuminating in history after incandescent lamp, fluorescent lamp
Third time revolution, started to be widely used in general lighting, entertainment lighting, agriculture illumination, Sports lighting, commercial lighting,
The fields such as lighting for medical use have many advantages, such as that electro-optical efficiency height, energy-saving and environmental protection, service life are long, small in size.Under same brightness,
LED electricity consumption is only the 1/10 of incandescent lamp, and service life was up to 100,000 hours.
Forward LED simple process, advantage of lower cost, are most widely used.Since Sapphire Substrate is non-conductive, horizontal junction
In structure LED chip manufacturing proces, etching table top is generally required, to expose n-GaN, and deposits n electricity on exposed n-GaN
Pole.Since etching area can lose the efficient lighting area of LED, i.e. the etching area of table top is bigger, then LED efficient lighting area
With regard to smaller, therefore the loss for etching area and reducing efficient lighting area how is effectively reduced when making n-electrode, to raising
LED luminance is of crucial importance.
Utility model content
The purpose of this utility model is to provide a kind of pole array n through-hole interdigital electrode packed LED chip, n-electrodes
Interdigitated electrode structure form is used between p-electrode, and n-electrode uses the pole array n through-hole structure form；It is above-mentioned to reach
Purpose is adopted the technical scheme that:
A kind of pole array n through-hole interdigital electrode packed LED chip successively includes substrate, n-type semiconductor from bottom to top
Layer, luminescent layer and p-type semiconductor layer are equipped with the current extending being electrically connected with p-type semiconductor layer in p-type semiconductor layer,
The dielectric isolation layer with current extending insulation connection is equipped on current extending, being equipped on dielectric isolation layer is in rectangle battle array
The pole the n through-hole of column distribution, the pole n through-hole extend to n-type semiconductor layer from top to bottom, and insulation is equipped on the through-hole wall of the pole n
Dividing wall；Be equipped with side by side on dielectric isolation layer the pole multiple row p through-hole perhaps the pole the p through slot pole the p through-hole or the pole p through slot from
Current extending is extended under above, the column pole a p through-hole or the pole p through slot are alternately arranged with the column pole a n through-hole in left-right direction
And form interdigital structure；The pole n conductive column is equipped in the through-hole of the pole n, after same column n pole conductive column is electrically connected, the pole each column n conductive column
It is electrically connected again at one end and forms n-electrode, be equipped with the pole p conductive column in the pole p through-hole or the pole p through slot or the pole p is led
Electric block, the pole same column p conductive column after perhaps the pole p conducting block is electrically connected each column p pole conductive column or the pole p conducting block in the other end
It is electrically connected again and forms p-electrode.
Preferably, the dielectric isolation layer is integrally formed with wall is dielectrically separated from.
Preferably, the current extending material is transparent conductive material.
Preferably, the dielectric isolation layer material is silica or silicon nitride.
It is continuous to have the beneficial effect that the packed LED chip of the utility model does not need to etch possessed by the utility model
Table top, need to only etch rectangular array distribution and the mutually disjunct pole n through-hole, recycle dielectric isolation layer continuous
Metal layer realizes the pole n conductive column continuity and is electrically connected and forms n-electrode, realizes the pole p conductive column or the pole p conducting block company
Continuous property is electrically connected and forms p-electrode, and n-electrode and p-electrode are in interdigitated electrode structure form；To not influence current expansion
Under the premise of energy, the loss of LED efficient lighting area is reduced, LED luminance is improved.
The packed LED chip production method of the utility model, in the distribution of production rectangular array, mutually disjunct n is extremely logical
Corresponding mask plate need to be only used when hole, producing efficiency is high, at low cost；It is golden using being deposited on dielectric isolation layer simultaneously
The mode for belonging to layer forms the pole n conductive column, the pole p conductive column or the pole p conducting block, ensure that the stabilization that each electrode is electrically connected
Property, then the n-electrode and p-electrode in interdigitated electrode structure form are formed using metal lift-off material, production quality height, efficiency
It is high.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of LED chip in step A；
Fig. 2 is the structural schematic diagram of LED chip in step B；
Fig. 3 is the structural schematic diagram of LED chip in step C；
Fig. 4 is the structural schematic diagram of LED chip in step D, E；
Fig. 5 is the structural schematic diagram of the utility model LED chip；
Fig. 6 is the top view of Fig. 5.
Specific embodiment
The utility model is further described with reference to the accompanying drawing.
As shown in Figures 4 to 6, the pole a kind of array n through-hole interdigital electrode packed LED chip successively includes from bottom to top
Substrate 1, n-type semiconductor layer 2, luminescent layer 3 and p-type semiconductor layer 4 are equipped with and 4 electricity of p-type semiconductor layer in p-type semiconductor layer 4
Property connection current extending 6, on current extending 6 be equipped with current extending 6 insulation connection dielectric isolation layer 7,
Dielectric isolation layer 7 is equipped with the pole the n through-hole 10 of rectangular array distribution, and the pole n through-hole 10 extends to N-shaped from top to bottom and partly leads
Body layer 2 is equipped on 10 inner wall of the pole n through-hole and is dielectrically separated from wall 11；On dielectric isolation layer 7 side by side be equipped with multiple row p pole through-hole or
The pole person p through slot 8, the pole p through-hole or the pole p through slot 8 extend to current extending 6 from top to bottom, in left-right direction the column pole p
Through-hole or the pole p through slot 8 and the column pole a n through-hole 5 are alternately arranged and form interdigital structure；It is extremely conductive that n is equipped in the pole n through-hole 5
Column 12, after the pole same column n conductive column 12 is electrically connected, the pole each column n conductive column 12 is electrically connected again at one end and forms n electricity
Pole, equipped with the pole p conductive column, perhaps 11 same column p pole conductive column of the pole p conducting block or the pole p are led in the pole p through-hole or the pole p through slot 8
After electric block 11 is electrically connected, each column p pole conductive column or the pole p conducting block 11 are electrically connected again in the other end and form p electricity
Pole.
As shown in Figure 4, Figure 5, the dielectric isolation layer 7 is integrally formed with wall 10 is dielectrically separated from.The current extending 6
Material uses the transparent conductive material of high-transmission rate, such as ITO, Ni/ graphene.7 material of dielectric isolation layer is titanium dioxide
Silicon or silicon nitride.
The packed LED chip of the utility model does not need to etch continuous table top, need to only etch rectangular array point
Cloth and the mutual disjunct pole n through-hole 5, recycle the continuous metal layer of dielectric isolation layer 7 to realize the pole n conductive column 12 continuous
Property be electrically connected and form n-electrode, realize the pole p conductive column or 11 continuity of the pole p conducting block be electrically connected and formed p electricity
Pole, n-electrode and p-electrode are in interdigitated electrode structure form；To reduce LED under the premise of not influencing current expansion performance
The loss of efficient lighting area, improves LED luminance.
A kind of production method of the pole array n as described above through-hole interdigital electrode packed LED chip, including walk as follows
It is rapid:
As shown in Figure 1, step A: providing substrate 1, then the successively epitaxial growth n-type semiconductor from bottom to top on substrate 1
Layer 2, luminescent layer 3 and p-type semiconductor layer 4；
As shown in Fig. 2, step B: etching luminescent layer 3 and p-type semiconductor layer 4, formation are exposed to the more of n-type semiconductor layer 2
A pole n through-hole 5,5 rectangular array of the pole n through-hole are distributed and are mutually not attached to；
As shown in figure 3, step C: the deposition current extension layer 6 in p-type semiconductor layer 4, while on current extending 6 with
The corresponding position of the pole n through-hole 5 is performed etching to upwardly extend the pole n through-hole 5；
As shown in figure 4, step D: depositing dielectric isolation layer 7 on current extending 6, dielectric isolation layer 7 covers electric current and expands
Exhibition layer 6 simultaneously fills the pole n through-hole 5；
Step E: position corresponding with the pole n through-hole 5 is performed etching to upwardly extend the pole n through-hole 5 on dielectric isolation layer 7,
Wall 10 is dielectrically separated from the formation of 5 inner wall of the pole n through-hole simultaneously；Etched on dielectric isolation layer 7 multiple row p pole through-hole arranged side by side or
The pole person p through slot 8, the column pole a p through-hole or the pole p through slot 8 are alternately arranged with the column pole a n through-hole 5 and are formed interdigital in left-right direction
Structure, the pole p through-hole or the pole p through slot 8 go directly current extending 6；
As shown in Figure 5 and Figure 6, step F: a layer photoresist is coated on dielectric isolation layer 7, and photoetching is carried out to photoresist
Interdigital structure electrode vacancy figure is formed, then in evaporation metal electrode material above, the pole n through-hole 5 is filled and forms the pole n conductive column
12, it fills the pole p through-hole or the pole p through slot 8 and forms the pole p conductive column 11, finally by remaining photoresist and be deposited on residual lithographic
Evaporation metal electrode material removal on glue, to form the n-electrode and p-electrode in interdigitated electrode structure.Specifically, same column n
After pole conductive column 12 is electrically connected, the pole each column n conductive column 12 is electrically connected again at one end and forms n-electrode, and same column p is led pole
Electric column after perhaps the pole p conducting block 11 is electrically connected each column p pole conductive column or the pole p conducting block 11 in the other end carry out electrical property again
It connects and forms p-electrode.The material of n-electrode and p-electrode is one or more of chromium, platinum, gold, silver, copper, titanium, lead and nickel.
Wherein, used mask plate is identical when performing etching in the step B and step C.
The packed LED chip production method of the utility model, in the distribution of production rectangular array, mutually disjunct n is extremely logical
Corresponding mask plate need to be only used when hole 5, producing efficiency is high, at low cost；It uses and is deposited on dielectric isolation layer 7 simultaneously
The mode of metal layer forms the pole n conductive column 12, the pole p conductive column or the pole p conducting block 11, ensure that each electrode was electrically connected
Stability, then the n-electrode and p-electrode in interdigitated electrode structure form are formed using metal lift-off material, production quality is high, imitates
Rate is high.
Finally, it should be noted that above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；
Although the utility model is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that:
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is carried out etc.
With replacement, but these are modified or replaceed, various embodiments of the utility model technology that it does not separate the essence of the corresponding technical solution
The spirit and scope of scheme.
Claims (4)
1. a kind of pole array n through-hole interdigital electrode packed LED chip, successively include from bottom to top substrate, n-type semiconductor layer,
Luminescent layer and p-type semiconductor layer, which is characterized in that the electric current being electrically connected with p-type semiconductor layer is equipped in p-type semiconductor layer
Extension layer is equipped with the dielectric isolation layer with current extending insulation connection on current extending, is equipped on dielectric isolation layer
The pole the n through-hole of rectangular array distribution, the pole n through-hole extends to n-type semiconductor layer from top to bottom, on the through-hole wall of the pole n
Equipped with being dielectrically separated from wall；It is equipped with the pole multiple row p the through-hole perhaps pole the p through slot pole the p through-hole or p side by side on dielectric isolation layer
Pole through slot extends to current extending from top to bottom, in left-right direction the column pole a p through-hole or the pole p through slot and the column pole a n through-hole
It is alternately arranged and forms interdigital structure；The pole n conductive column is equipped in the through-hole of the pole n, after same column n pole conductive column is electrically connected, each column n
Pole conductive column is electrically connected again at one end and forms n-electrode, in the pole p through-hole or the pole p through slot be equipped with the pole p conductive column or
The pole person p conducting block, the pole same column p conductive column after perhaps the pole p conducting block is electrically connected each column p pole conductive column or the pole p conducting block exist
The other end is electrically connected again and forms p-electrode.
2. the pole array n according to claim 1 through-hole interdigital electrode packed LED chip, which is characterized in that the insulation
Separation layer is integrally formed with wall is dielectrically separated from.
3. the pole array n according to claim 1 through-hole interdigital electrode packed LED chip, which is characterized in that the electric current
Extension layer material is transparent conductive material.
4. the pole array n according to any one of claims 1 to 3 through-hole interdigital electrode packed LED chip, feature exist
In the dielectric isolation layer material is silica or silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822024668.6U CN208939000U (en) | 2018-12-04 | 2018-12-04 | A kind of pole array n through-hole interdigital electrode packed LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822024668.6U CN208939000U (en) | 2018-12-04 | 2018-12-04 | A kind of pole array n through-hole interdigital electrode packed LED chip |
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| CN208939000U true CN208939000U (en) | 2019-06-04 |
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|---|---|---|---|
| CN201822024668.6U Expired - Fee Related CN208939000U (en) | 2018-12-04 | 2018-12-04 | A kind of pole array n through-hole interdigital electrode packed LED chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109360881A (en) * | 2018-12-04 | 2019-02-19 | 九江职业技术学院 | The pole a kind of array n through-hole interdigital electrode packed LED chip and preparation method thereof |
| CN112582510A (en) * | 2019-09-29 | 2021-03-30 | 山东浪潮华光光电子股份有限公司 | Gallium arsenide-based LED chip and preparation method thereof |
-
2018
- 2018-12-04 CN CN201822024668.6U patent/CN208939000U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109360881A (en) * | 2018-12-04 | 2019-02-19 | 九江职业技术学院 | The pole a kind of array n through-hole interdigital electrode packed LED chip and preparation method thereof |
| CN112582510A (en) * | 2019-09-29 | 2021-03-30 | 山东浪潮华光光电子股份有限公司 | Gallium arsenide-based LED chip and preparation method thereof |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190604 Termination date: 20211204 |