CN208904889U - Power supply timing control circuit - Google Patents
Power supply timing control circuit Download PDFInfo
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- CN208904889U CN208904889U CN201821708842.2U CN201821708842U CN208904889U CN 208904889 U CN208904889 U CN 208904889U CN 201821708842 U CN201821708842 U CN 201821708842U CN 208904889 U CN208904889 U CN 208904889U
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Abstract
Disclose a kind of power supply timing control circuit, input terminal connects multichannel loading via output end by power supply unit and provides power supply, timing control unit is used to control the power supply timing of multichannel loading at least loaded all the way, it include: first comparator, one end connects output end via the first potential-divider network, and one end is connected to the network input terminal via pressure stabilizing；Second comparator, one end connect first comparator output end via the second potential-divider network, and the other end is separately connected the first path terminal and output end of first switch tube；Timing controller is connected to output end and at least all the way between the load of multichannel loading of the second comparator, and the control terminal of first switch tube connects input terminal, and alternate path end passes through first resistor ground connection.The power supply timing control circuit of the application so that foregoing circuit provides reliable and stable timing control to load after power supply unit is fully powered up and when power down, and makes the voltage range that powers on of power supply timing control circuit become larger by timing control unit.
Description
Technical field
The utility model relates to power supply power supply technical field, in particular to a kind of power supply timing control circuit.
Background technique
Test device currently used for testing 4K display device generally uses high performance programmable gate array, each
Built-in function region individually powers, therefore electrifying timing sequence to power supply and power supply ripple require high, and power supply design will be improper to be led
Cause test device permanent damage.
Fig. 1 shows a kind of power supply timing control circuit of the prior art, and power supply timing control circuit 100 includes input terminal
Vin, output end vo ut, main power supply unit 110, timing control unit 120 and multichannel loading 130.Main power supply unit 110 wraps
Include the diode D1 being connect with input terminal Vin forward direction, diode D2, the DC/DC converter being connected between two diodes and
The anode of capacitor C1 and capacitor C2, two capacitors are connected and are connected between diode D2 cathode and output end vo ut, cathode connection
And it is grounded.Timing control unit includes comparator U1 and timing controller, and the positive input of comparator U1 is via series connection
Resistance R2, resistance R1 connection input list Vin, the one end resistance R3 connect resistance R2 and resistance R1 between, the other end be grounded, reversely
Input terminal connects the divider node of resistance R4 and resistance R5, and the one end resistance R4 connects output end vo ut, and the one end resistance R5 is grounded, just
Output end is terminated to power supply, the output end of reverse electrical source end ground connection, comparator U1 connects timing controller.Output end vo ut with
The feeder ear of multichannel loading connects, and timing controller and every load all the way connect, load for example, FPGA (programmable gate
Array).The DC/DC converter of the circuit 100 works, and comparator powers on load after powering on, and timing controller makes to be able to achieve
To the power supply timing control of each road load.Through detecting, power supply timing control circuit 100 as shown in Figure 2 is 5V's in external voltage
Upper electrical waveform under environment, L1 are output end voltage waveform, and L2 is the voltage waveform of timing controller, due to capacitive load shadow
It rings, 120 power-on time of power supply unit is longer, and load supplying shakiness timing sequence control chip is caused to work, can not be to more
The power supply timing of road load effectively controls, and the electric current of surging of a few roads load is larger, causes timing control can not be just to it
Often control.And when the down circuitry, timing controller cannot power off in time, and the use voltage range of the circuit is narrow,
Circuit does not work when the external voltage of 12V exports the circuit.
Therefore, providing a reliable and stable electrifying timing sequence to high performance test device is particularly important.
Utility model content
In view of the above problems, the purpose of this utility model is to provide a kind of power supply timing control circuits, to mention to load
For reliable and stable timing control.
One side according to the present utility model provides a kind of power supply timing control circuit, including input, output end, confession
Electric unit, input terminal receive external voltage and connect multichannel loading offer power supply via output end by processing, further includes: timing control
Unit processed, for controlling at least power supply timing of the load all the way of load described in multichannel, comprising: first comparator, one end
The output end is connected via the first potential-divider network, the other end is connected to the network the input terminal via pressure stabilizing；Second comparator, one
End connects the first comparator output end via the second potential-divider network, and the other end is separately connected the first access of first switch tube
End and the output end；And timing controller, be connected to second comparator output end and multichannel described in load
At least all the way between load, wherein the control terminal of the first switch tube connects the input terminal, and the of the first switch tube
Two path terminals are grounded by first resistor.
It preferably, further include third potential-divider network, the input terminal is via third potential-divider network connection described first
The divider node of switching tube, the third potential-divider network connects the control terminal of the first switch tube.
Preferably, one end of the first comparator is positive input, described described first point of positive input connection
The divider node of pressure network network, the other end of the first comparator are reverse input end, and the reverse input end connection is described steady
The output end of pressure network network, the positive power end of the first comparator connect the output end, the first comparator it is reversed
Power end ground connection.
Preferably, one end of second comparator is positive input, described described second point of positive input connection
The other end of the divider node of pressure network network, second comparator is reverse input end, and the reverse input end is separately connected institute
The first path terminal for stating first switch tube connects the output end with the positive power end of the second comparator described in the output end,
The reverse electrical source end of second comparator is grounded.
Limitedly, said supply unit includes: DC/DC converter, first diode and institute of the one end via Opposite direction connection
Input terminal connection is stated, the other end connects the output end via the second diode of forward direction connection；And first capacitor and second
The positive terminal of capacitor, two capacitors is connected and is connect with the output end, the negative pole end connect and ground of two capacitors.
Preferably, the power supply timing control circuit further include: second switch, one end connects the input terminal, another
End is connect with said supply unit and the timing control unit.
Preferably, load described in multichannel includes at least programmable gate array all the way.
Preferably, first potential-divider network includes the second resistance and 3rd resistor being sequentially connected in series, one end with it is described defeated
Outlet connection, the other end are grounded, the divider node with first potential-divider network between the connection of two resistance；Second partial pressure
Network includes the 5th resistance and the 6th resistance being sequentially connected in series, and one end is connect with the output end of the first comparator, the other end
It is grounded, the divider node with second potential-divider network between the connection of two resistance；And the third potential-divider network include according to
Secondary concatenated 7th resistance and the 8th resistance, one end are connect with the input terminal, other end ground connection, are had between the connection of two resistance
The divider node of the third potential-divider network.
Preferably, the pressure stabilizing network includes the 4th resistance and the voltage-stabiliser tube with the 4th resistance Opposite direction connection, described
One end of 4th resistance connects the input terminal, the plus earth of the voltage-stabiliser tube, the 4th resistance and voltage-stabiliser tube yin
Output end with the pressure stabilizing network between the connection of pole.
Preferably, the first switch tube is N-type metal-oxide-semiconductor, and the second switch is selected from any of triode, diode
Kind.
Power supply timing control circuit provided by the utility model receives external voltage and powers on, the DC/DC conversion of power supply unit
After device is fully powered up, the enabled control terminal for opening timing controller is controlled by timing control unit.Sequence controls while power is being supplied
When second switch or the Sofe Switch power-off of circuit, make can control by timing control unit closing timing control chip
End, above-mentioned power supply timing control circuit provide to load stablize, reliable electrifying timing sequence, and above-mentioned timing control unit
It is arranged so that the voltage range that powers on of power supply timing control circuit becomes larger, the availability of circuit is higher.
Preferably, timing control unit is exported by first comparator voltage value of the voltage equal to output end vo ut and
First switch tube K1 conducting ensures that DC/DC powers on completion so that the voltage of the second comparator output is equal to the voltage of output end vo ut
Value, and then enabled control terminal is opened in timing controller work, and then realizes the power supply timing at least one of multichannel loading
It control effectively.
Preferably, timing control unit is 0 and first switch tube K1 closing or first by first comparator output
The setting of resistance is come the second comparator when making output end voltage when ensuring second switch or Sofe Switch power down lower than setting value
Output is 0, and then enabled control terminal is opened in timing controller work, and then realizes the power supply at least one of multichannel loading
Timing control effectively.
Preferably, guarantee timing control unit in voltage-stabiliser tube, first switch tube and power supply unit DC/DC converter
Under the premise of normal work, the voltage range of foregoing circuit input terminal broadens compared with the prior art.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic diagram of power supply timing control circuit according to prior art；
Waveform diagram is powered on Fig. 2 shows power supply timing control circuit according to prior art；
Fig. 3 shows the schematic diagram of the power supply timing control circuit according to the utility model embodiment；
Fig. 4, which is shown, powers on waveform diagram according to the power supply timing control circuit of the utility model embodiment；
Fig. 5 shows the power down waveform diagram of the power supply timing control circuit according to the utility model embodiment.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the various embodiments of the utility model.In various figures, identical
Element is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not drawn to draw
System.
With reference to the accompanying drawings and examples, specific embodiment of the present utility model is described in further detail.
Fig. 3 shows the schematic diagram of the power supply timing control circuit according to the utility model embodiment.
As shown in figure 3, power supply timing control circuit 200 includes input terminal Vin, output end vo ut, second switch K2, supplies
Electric unit 210, timing control unit 220.Input terminal Vin receives external voltage by passing through after processing by exporting Vout connection multichannel
Load 300 provides power supply, and timing control unit 220 is for controlling the power supply timing that multichannel loading 300 at least loads all the way.
Power supply unit 210 includes that the DC/DC being connected between first diode D1 cathode and the second diode D2 anode turns
Parallel operation, first capacitor C1 and the second capacitor C2, specifically, input terminal Vin pass through second switch K2 connection first diode
The anode of D1, the anode connection of cathode connection the output end vo ut, first capacitor C1 and the second capacitor C2 of the second diode D2 are simultaneously
It is connect with output end vo ut, the cathode connect and ground of first capacitor C1 and the second capacitor C2.
Timing control unit 220 includes first comparator U1, the second comparator U2 and timing controller 225, specifically
Ground, the positive input of first comparator U1 connect the divider node of the first potential-divider network 221 and via the first potential-divider networks 221
Output end vo ut is connected, reverse input end connects the output end of pressure stabilizing network 222 and via pressure stabilizing network 222 and two switching tubes
K2 connection input terminal Vin, positive power end connect output end vo ut, reverse electrical source end ground connection.The forward direction of second comparator U2 is defeated
Enter the divider node of the second potential-divider network 223 of end connection and via the output of the second potential-divider network 223 connection first comparator U1
End, reverse input end are separately connected the first path terminal of first switch tube K1 and via the tenth resistance R10 connection output ends
Vout, positive power end connect institute output end vo ut, reverse electrical source end ground connection.Wherein, the control terminal of first switch tube K1 passes through
The divider node of 9th resistance R9 connection third potential-divider network 224 simultaneously passes through third potential-divider network 224 and second switch K2
Input terminal Vin is connected, the alternate path end of first switch tube K1 is grounded by first resistor R1.225 one end of timing controller
The output end of the second comparator is connected, other end connection multichannel loading 300 at least loads all the way.
Multichannel loading 300 includes at least FPGA (programmable gate array) all the way, bears in the present embodiment for example including 6 tunnels
It carries, i.e. FPGA1-FPGA6.
More specifically, the first potential-divider network 221 includes the second resistance R2 and 3rd resistor R3 that are sequentially connected in series, one end with it is defeated
Outlet Vout connection, the other end are grounded, the divider node with the first potential-divider network 221 between the connection of two resistance.Second partial pressure
Network 223 includes the 5th resistance R5 and the 6th resistance R6 being sequentially connected in series, and one end is connect with the output end of first comparator U1, separately
One end is grounded, the divider node with the second potential-divider network 223 between the connection of two resistance.Third potential-divider network 224 includes successively
Concatenated 7th resistance R7 and the 8th resistance R8, one end are connect with input terminal Vin, other end ground connection, are had between the connection of two resistance
There is the divider node of third potential-divider network 224.Pressure stabilizing network 222 include sequentially connected 4th resistance R4 and with voltage-stabiliser tube D3,
One end of 4th resistance R4 connects input terminal Vin, the plus earth of voltage-stabiliser tube D3, and the 4th resistance R4 is connect with voltage-stabiliser tube D3 cathode
Between with pressure stabilizing network 222 output end.
It should be noted that the first capacitor C1 and the second capacitor C2 in the utility model embodiment are, for example, to be electrolysed electricity
Hold, resistance R9, resistance R10 for example can be the protective resistance of first switch tube K1.First resistor R1 is small resistance, such as can be with
It is 100 Ω.First switch tube K1 is, for example, N-type metal-oxide-semiconductor, second switch K2 for example selected from triode, diode it is any,
It such as can be metal-oxide-semiconductor.
The power supply timing control circuit 200 of the present embodiment receives external voltage and powers on, the DC/DC conversion of power supply unit 210
After device is fully powered up, timing controller is opened by the first comparator of timing control unit 220 and the control of the second comparator
Enabled control terminal.When the second switch K2 of sequence control circuit 200 or Sofe Switch power off while power is being supplied, pass through timing control
The enabled control terminal of the first comparator of unit 220 and the second comparator control chip of closing timing control immediately.Above-mentioned power supply
The concrete operating principle of sequential control circuit 200 will be in conjunction with following upper down circuit waveform diagram descriptions.
Fig. 4, which is shown, powers on waveform diagram according to the power supply timing control circuit of the utility model embodiment.
In conjunction with Fig. 3, it is the voltage that DC/DC allows that the input terminal Vin of power supply timing control circuit 200, which receives external voltage,
When, second switch K2 is opened, and third potential-divider network 224 divides so that first switch tube K1 is connected, and first comparator U1's is anti-
Receiving the voltage of voltage regulation that pressure stabilizing network 222 exports to input terminal is, for example, 4.7V, and the reverse input end of the second comparator U2 is by defeated
The voltage influence of outlet Vout.As the voltage that DC/DC converter powers at rear output end vo ut constantly increases, work as output end
When voltage at Vout is less than setting value, setting value for example can be 4.8V for the voltage value greater than 222 output end of pressure stabilizing network,
First comparator U1 output be 0, at this time because of the effect of first resistor R1 so that the second comparator U2 output be 0, timing control core
Piece 225 does not work；When voltage at output end vo ut is more than or equal to setting value, the voltage value of first comparator U1 output is equal to
Voltage at output end vo ut, the voltage value of the second comparator U2 output are equal to the voltage at output end vo ut, timing control core
Enabled control terminal, the power supply timing that control multichannel loading 300 at least loads all the way are opened in the work of piece 225.
Specifically, as shown in figure 4, waveform L1 is the voltage waveform of output end, waveform L2 is enabled for timing controller 225
The voltage waveform at end, when the voltage of output end is fully powered up and stablizes, accordingly the enable end of timing controller 225 is powered on
It opens, realizes and 300 power supply timing of multichannel loading is effectively controlled.
Fig. 5 shows the power down waveform diagram of the power supply timing control circuit according to the utility model embodiment.
In conjunction with Fig. 3, when the second switch K2 of sequence control circuit 200 is disconnected while power is being supplied, the front end first diode D1 electricity
Pressing moment is 0, and output end Vout voltage is gradually reduced, and first switch tube K1 is disconnected, and the voltage of first comparator U1 output is still
Equal to the voltage value of output end vo ut, voltage is equal to the voltage value of output end vo ut at the reverse input end of the second comparator U2,
Therefore the output of the second comparator U2 is 0.When output end Vout voltage is less than setting value, first comparator U1 output is 0, the
It is 0 that two comparator U2, which are persistently exported,.Therefore after second switch K2 is disconnected, timing controller 225 does not work and closes enabled
End.
After the Sofe Switch of sequence control circuit 200 disconnects while power is being supplied, second switch K2 is still connected, at this time the one or two pole
Pipe D1 front voltage is still equal to external voltage value, and output end Vout voltage is gradually reduced.First switch tube K1 is connected at this time, the
The voltage of one comparator U1 output is still equal to the voltage value of output end vo ut, and the voltage of the second comparator U2 output is equal to output
Hold the voltage value of Vout.When output end Vout voltage is less than setting value, first comparator U1 output is 0, the second comparator U2
Also output is 0.Therefore after Sofe Switch disconnects, timing controller does not work and closes enable end.
Specifically, as shown in figure 5, waveform L1 is the voltage waveform of output end, waveform L2 is enabled for timing controller 225
The voltage waveform at end, when the voltage of output end drops to the voltage of setting value, the accordingly enable end of timing controller 225
Power down is closed, and be ensure that and is effectively controlled 300 power supply timing of multichannel loading.
The minimum cut-in voltage of the first switch tube K1 of the power supply timing control circuit 200 of the present embodiment is, for example, 1.2V,
It can guarantee that the minimum voltage that the end input terminal Vin that foregoing circuit 200 works allows is 4.8V by calculating.By DC/ in the circuit
The influence of DC converter, voltage control between 28V, and guarantees that voltage-stabiliser tube D3 is worked normally in 5.6V, at input terminal Vin
When voltage range is within the scope of 5.6-25V, foregoing circuit 200 can be worked normally.
It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe,
Also not limiting the utility model is only the specific embodiment.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With so that skilled artisan be enable to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (10)
1. a kind of power supply timing control circuit, including input, output end, power supply unit, input terminal receives external voltage and passes through
Processing provides power supply via output end connection multichannel loading, which is characterized in that further include:
Timing control unit, for controlling at least power supply timing of the load all the way of load described in multichannel, comprising:
First comparator, one end connect the output end via the first potential-divider network, described in the other end is connected to the network via pressure stabilizing
Input terminal；
Second comparator, one end connect the first comparator output end via the second potential-divider network, and the other end is separately connected the
First path terminal of one switching tube and the output end；And
Timing controller, be connected to second comparator output end and multichannel described in load at least load it all the way
Between,
Wherein, the control terminal of the first switch tube connects the input terminal, and the alternate path end of the first switch tube passes through
First resistor ground connection.
2. power supply timing control circuit according to claim 1, which is characterized in that it further include third potential-divider network, it is described
Input terminal connects the first switch tube via the third potential-divider network, and the divider node of the third potential-divider network connects institute
State the control terminal of first switch tube.
3. power supply timing control circuit according to claim 1, which is characterized in that one end of the first comparator is positive
To input terminal, the positive input connects the divider node of first potential-divider network, the other end of the first comparator
For reverse input end, the reverse input end connects the output end of the pressure stabilizing network, the positive power supply of the first comparator
End connects the output end, the reverse electrical source end ground connection of the first comparator.
4. power supply timing control circuit according to claim 1, which is characterized in that one end of second comparator is positive
To input terminal, the positive input connects the divider node of second potential-divider network, the other end of second comparator
For reverse input end, the reverse input end be separately connected the first switch tube the first path terminal and the output end, institute
The positive power end for stating the second comparator connects the output end, the reverse electrical source end ground connection of second comparator.
5. power supply timing control circuit according to claim 1, which is characterized in that said supply unit includes:
DC/DC converter, one end are connect via the first diode of Opposite direction connection with the input terminal, and the other end connects via forward direction
The second diode connect connects the output end；And
The positive terminal of first capacitor and the second capacitor, two capacitors is connected and is connect with the output end, and the negative pole end of two capacitors connects
It connects and is grounded.
6. power supply timing control circuit according to claim 1, which is characterized in that the power supply timing control circuit is also wrapped
It includes:
Second switch, one end connect the input terminal, and the other end is connect with said supply unit and the timing control unit.
7. power supply timing control circuit according to claim 1, which is characterized in that load described in multichannel includes at least all the way
Programmable gate array.
8. power supply timing control circuit according to claim 2, which is characterized in that
First potential-divider network includes: the second resistance and 3rd resistor being sequentially connected in series, and one end is connect with the output end, separately
One end is grounded, the divider node with first potential-divider network between the connection of two resistance；
Second potential-divider network includes: the 5th resistance and the 6th resistance being sequentially connected in series, one end and the first comparator
Output end connection, the other end are grounded, the divider node with second potential-divider network between the connection of two resistance；And
The third potential-divider network includes: the 7th resistance and the 8th resistance being sequentially connected in series, and one end is connect with the input terminal, separately
One end is grounded, the divider node with the third potential-divider network between the connection of two resistance.
9. power supply timing control circuit according to claim 1, which is characterized in that the pressure stabilizing network includes:
One end of 4th resistance and voltage-stabiliser tube with the 4th resistance Opposite direction connection, the 4th resistance connects the input
End, the plus earth of the voltage-stabiliser tube have the pressure stabilizing network between the 4th resistance and pressure stabilizing tube cathode connection
Output end.
10. power supply timing control circuit according to claim 6, which is characterized in that the first switch tube is N-type MOS
Pipe, the second switch be selected from triode, diode it is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821708842.2U CN208904889U (en) | 2018-10-22 | 2018-10-22 | Power supply timing control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821708842.2U CN208904889U (en) | 2018-10-22 | 2018-10-22 | Power supply timing control circuit |
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| CN208904889U true CN208904889U (en) | 2019-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821708842.2U Active CN208904889U (en) | 2018-10-22 | 2018-10-22 | Power supply timing control circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110209233A (en) * | 2019-06-03 | 2019-09-06 | 长沙优力电驱动系统有限公司 | Power module |
| CN111082801A (en) * | 2019-12-06 | 2020-04-28 | 杭州迪普科技股份有限公司 | Time sequence control system and electronic equipment |
| CN112115670A (en) * | 2020-08-31 | 2020-12-22 | 深圳天狼芯半导体有限公司 | Power network layout method and device of chip |
| CN112180798A (en) * | 2020-10-09 | 2021-01-05 | 珠海格力电器股份有限公司 | Time sequence control circuit, power supply control circuit and frequency converter |
-
2018
- 2018-10-22 CN CN201821708842.2U patent/CN208904889U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110209233A (en) * | 2019-06-03 | 2019-09-06 | 长沙优力电驱动系统有限公司 | Power module |
| CN111082801A (en) * | 2019-12-06 | 2020-04-28 | 杭州迪普科技股份有限公司 | Time sequence control system and electronic equipment |
| CN111082801B (en) * | 2019-12-06 | 2023-09-26 | 杭州迪普科技股份有限公司 | Time sequence control system and electronic equipment |
| CN112115670A (en) * | 2020-08-31 | 2020-12-22 | 深圳天狼芯半导体有限公司 | Power network layout method and device of chip |
| CN112115670B (en) * | 2020-08-31 | 2024-06-07 | 深圳天狼芯半导体有限公司 | Power supply network layout method and device for chip |
| CN112180798A (en) * | 2020-10-09 | 2021-01-05 | 珠海格力电器股份有限公司 | Time sequence control circuit, power supply control circuit and frequency converter |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
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