CN208904000U - Integrated circuit package body - Google Patents

Integrated circuit package body Download PDF

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Publication number
CN208904000U
CN208904000U CN201821394117.2U CN201821394117U CN208904000U CN 208904000 U CN208904000 U CN 208904000U CN 201821394117 U CN201821394117 U CN 201821394117U CN 208904000 U CN208904000 U CN 208904000U
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CN
China
Prior art keywords
glue film
chip
package substrate
integrated circuit
circuit package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201821394117.2U
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Chinese (zh)
Inventor
王政尧
林子翔
郭桂冠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Riyuexin Semiconductor Suzhou Co ltd
Original Assignee
Suzhou ASEN Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Suzhou ASEN Semiconductors Co Ltd filed Critical Suzhou ASEN Semiconductors Co Ltd
Priority to CN201821394117.2U priority Critical patent/CN208904000U/en
Application granted granted Critical
Publication of CN208904000U publication Critical patent/CN208904000U/en
Active legal-status Critical Current
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model is about integrated circuit package body.One embodiment of the utility model provides an integrated circuit package body comprising: package substrate, surface are provided with conductive contact;Chip comprising: first surface;The second surface opposite with first surface;And metal structure, it is set to first surface;Metal structure is connect with conductive contact, and cavity is collectively formed with the surface of the first surface of chip, package substrate;Glue film extends at least above height of the first surface of chip from the surface of package substrate and seals cavity;And packaging body, covering package substrate, glue film and chip.The utility model can be realized with a low cost highly reliable product quality.

Description

Integrated circuit package body
Technical field
The utility model relates to field of semiconductor package, more particularly to integrated circuit package body and manufacture integrated circuit envelope The method for filling body.
Background technique
Surface acoustic wave (Surface acoustic wave, SAW) filter is one of component indispensable in communication apparatus. When SAW filter chip or chip (hereafter referred to collectively as " SAW filter chip ") are integrated to the surface of conductor package substrate When upper, needed to guarantee the sky that there is the interdigital transducer (Inter-Digital Transducer, IDT) for accommodating SAW filter Chamber, to realize the effect of IDT filtering.Other than the condition of formation to be met and protection cavity, also need to guarantee that encapsulating products have Good reliability and it can be realized quick volume production.
SAW filter chip quickly and is in batches encapsulated for how to realize, while it is good to guarantee that the product after encapsulation has Reliability, there are still considerable technical problem urgent need to resolve in the industry.
Utility model content
One of the purpose of this utility model is the method for providing integrated circuit package body and manufacturing integrated circuit package body, It can simple processing procedure and technique realize the integrated circuit package body of low-cost and high-quality.
One embodiment of the utility model provides an integrated circuit package body comprising: package substrate, surface are provided with Conductive contact;Chip comprising: first surface;Second surface, the second surface are opposite with the first surface;And metal Structure is set to the first surface;The metal structure is connect with the conductive contact, and the first table with the chip Face, the package substrate surface cavity is collectively formed;Glue film extends at least above institute from the surface of the package substrate It states the height of the first surface of chip and seals the cavity;And packaging body, cover the package substrate, the glue film and institute State chip.
In another embodiment of the utility model, the glue film is formed by the colloid or dry film of processing fluidity difference.? In the another embodiment of the utility model, the second surface of the glue film covering chip.In another embodiment of the utility model In, the thickness of the glue film is at least more than 1 micron.In the another embodiment of the utility model, the packaging body and glue film by Different materials are formed, and the processing fluidity for forming the material of packaging body is greater than the processing fluidity for forming the material of glue film.? In another embodiment of the utility model, forms the thermal expansion coefficient of the material of the packaging body and form the package substrate The similar thermal expansion coefficient of material.In the another embodiment of the utility model, the chip is filter wafer.
Another embodiment of the utility model provides the method for a manufacture integrated circuit package body comprising: encapsulation is provided Substrate, the package substrate include surface, and the surface is provided with conductive contact;Chip is provided, the chip includes: the first table Face;Second surface, the second surface are opposite with the first surface;And metal structure, it is set to the first surface;It will The chip is set to the surface of the package substrate, wherein the metal structure is configured to connect to the conductive contact, And with the first surface of the chip, the package substrate surface between form cavity;Glue film is set in the package substrate Surface so that the glue film extends to the height of the first surface of at least above described chip from the surface of the package substrate It spends and seals the cavity;And form packaging body, the packaging body at least cover the surface of the package substrate, the glue film and The chip.
Integrated circuit package body provided by the embodiment of the utility model and its manufacturing method can not only guarantee IDT cavity Completely, additionally it is possible to which the product after guaranteeing encapsulation has good reliability, realizes the production of integrated circuit package body rapid batch Purpose, and also have many advantages, such as that manufacturing process is simple and manufacturing cost is low.
Detailed description of the invention
Hereinafter will be briefly explained attached drawing necessary in order to describe the utility model embodiment or the prior art with Convenient for describing the utility model embodiment.It should be evident that the attached drawing in being described below is merely the part in the utility model Embodiment.To those skilled in the art, under the premise of not needing creative work, still can according to these attached drawings in Illustrated by structure obtain the attached drawings of other embodiments.
Fig. 1 is the longitudinal cross-section schematic diagram according to the integrated circuit package body of an embodiment of the present invention
Fig. 2 a-2d is the flow diagram that integrated circuit package body is manufactured according to an embodiment of the present invention, can be made Make integrated circuit package body shown in FIG. 1
Fig. 3 a-3c is the flow diagram that integrated circuit package body is manufactured according to another embodiment of the utility model, can Manufacture integrated circuit package body shown in FIG. 1
Specific embodiment
Embodiments herein will be shown hereinafter by detailed retouch.In present specification full text, by identical or Similar component and component with the same or similar function are indicated by like reference numerals.It is described herein to have Closing the embodiment of attached drawing is illustrative, graphic nature and the basic comprehension for providing to the application.The reality of the application It applies example and is not construed as limitations of the present invention.
In the present specification, unless except being specified or being limited, the word of relativity for example: it is " central ", " longitudinal ", " lateral ", " front ", " rear ", " right ", " left ", " internal ", " external ", " lower ", " higher ", " horizontal ", " vertically ", " being higher than ", " being lower than ", " top ", " lower section ", " top ", " bottom " And its derivative word (such as " horizontally ", " down ", " upward " etc.) should be construed to reference under discussion It is described or retouch the direction shown in the accompanying drawings.The word of these relativities be only used for description on convenience, and be not required for by The application construction or operation in a certain direction.
As used herein, term " substantially ", " generally ", " essence " and " close " is to describe and illustrate small change Change.When being used in combination with event or situation, the term can be referred to the example that wherein event or situation accurately occur and its The example that middle event or situation pole approximatively occur.For example, when combination numerical value is in use, term can be referred to be less than or equal to ± 10% variation range of the numerical value, e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, it is less than or equal to ± 2%, is less than or equal to ± 1%, is less than or equal to ± 0.5%, is less than or equal to ± 0.1% or small In or equal to ± 0.05%.For example, if difference between two values be less than or equal to the average value of described value ± 20% (e.g., less than or equal to ± 10%, be less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, it is small In or be equal to ± 2%, be less than or equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or be less than or wait In ± 0.05%), then it is assumed that described two numerical value " generally " are identical and " close ".
Furthermore for ease of description, " first ", " second ", " third " etc. can be used to distinguish herein a figure or one The different components of series of drawing." first ", " second ", " third " etc. are not intended to describe corresponding component.
In this application, unless except being specified or being limited, " setting ", " connection ", " coupling ", " fixation " and with Its similar word is that widely, and those skilled in the art can understand above-mentioned use according to specific circumstances in use Word can be, for example, fixedly connected, removable connection or integrated connection;It is also possible to mechanically connection or electrical ties;Its It can be the indirect link for directly linking or passing through intermediary agent structure;It is also possible to the internal communication of two components.
It note that " chip " as referred to herein refers to any kind of chip or chip for convenience of describing.
Fig. 1 is the longitudinal cross-section schematic diagram according to the integrated circuit package body 100 of an embodiment of the present invention.Such as Fig. 1 It is shown, the integrated circuit package body 100 according to an embodiment of the present invention include: package substrate 10, chip 12, glue film 14 and Packaging body 16.
The package substrate 10 includes surface 101, and the surface 103 opposite with surface 101.Surface 101 is provided with one or more A conductive contact 105, surface 103 are provided with one or more external pin (not shown)s.The package substrate 10 can be this Common various package substrates in field, such as printed circuit board, papery copper foil laminates, composite copper foil laminates, or polymerization The glass fibre class copper foil laminates of object dipping.The package substrate 10 may include interconnection structure, for example, redistribution layer (RDL) or Earth element.
The chip 12 includes surface 121, the surface 123 opposite with surface 121, metal structure 125 and is located on surface 121 Interdigital transducer IDT (not shown).The chip 12 is SAW filter chip.The metal structure 125 can be Tin ball, metal column or other structures commonly used in the art.The chip 12 can by upside-down mounting die bond (Flip-Chip Die Bond, FC Die Bond) mode the surface 101 of package substrate 10, and metal structure 125 and envelope are set to via metal structure 125 The conductive contact 105 for filling substrate 10 connects, so that chip 12 may be electrically connected to package substrate 10 by metal structure 125.It should The cavity for accommodating the IDT of chip 12 is collectively formed with the surface 121 of chip 12, the surface 101 of package substrate 10 for metal structure 125 18。
The glue film 14 extends to the height roughly the same with surface 123 from the surface of package substrate 10 101 upward and encloses Cavity 18 is sealed, to play the role of protecting cavity 18.Glue film 14 is by processing fluidity difference and to form bearing height Colloid or dry film.The thickness D (referring to Fig. 1) of glue film 14 is at least more than 1 micron.In another embodiment of the application, glue film 14 Thickness D at least more than 10 microns.In the another embodiment of the application, the thickness D of glue film 14 is at least more than 20 microns.Glue film 14 thickness D guarantees that when being packaged processing procedure to form packaging body 16, there is glue film 14 enough intensity to prevent cavity 18 from meeting with To destroying to protect the complete of cavity 18, the stability of product is improved.
In another embodiment of the application, which extends at least upward from the surface of package substrate 10 101 Higher than the surface 121 of filter wafer 12 height and seal cavity 18.For example, glue film 14 is from the surface of package substrate 10 101 The height roughly the same with surface 121 or height between surface 121 and surface 123 are extended to upward and seal cavity 18 or glue film 14 extend to above the height on surface 123 upward from the surface of package substrate 10 101 and seal cavity 18, And glue film 14 covers the surface 123 of filter wafer 12.
The packaging body 16 covers package substrate 10, chip 12 and glue film 14.The encapsulating material for forming packaging body 16 can be this Synthetic resin, plastics or the ceramic material of common various insulation in field, such as, but not limited to, epoxy resin.In some realities It applies in example, forms the thermal expansion coefficient phase of the thermal expansion coefficient and the material for forming package substrate 10 of the material of the packaging body 16 Closely, to reduce the warped degree of integrated circuit package body 100, for example, forming the thermal expansion coefficient and shape of the material of the packaging body 16 About ± 20% is differed at the thermal expansion coefficient of the package substrate 10, preferably, about ± 10%.Packaging body 16 and glue film 14 are by difference Material formed.It is heat cured for forming the material of glue film 14, therefore glue film 14 will not occur again after by hot setting Fusing, so that glue film 14 will not be affected by temperature still seal cavity during forming packaging body 16 18.In some embodiments, the processing fluidity for forming the material of packaging body 16 is greater than the processing stream for forming the material of glue film 14 Dynamic property.Further, since forming the material of packaging body 16 has good processing fluidity, thus joint filling is stronger, thus in shape It can prevent steam from entering during at packaging body 16, to improve the reliability of integrated circuit package body 100.
The embodiment of the present application also provides the methods for manufacturing integrated circuit package body 100.
Fig. 2 a-2d is the flow diagram that integrated circuit package body 100 is manufactured according to one embodiment of the application, can be manufactured Integrated circuit package body 100 as shown in Figure 1.
As shown in Figure 2 a, package substrate 10 is provided.The package substrate 10 includes surface 101, and the table opposite with surface 101 Face 103.Surface 101 is provided with one or more conductive contacts 105, and surface 103 is provided with one or more external pins and (does not show in figure Out).The package substrate 10 can be various package substrates commonly used in the art, such as printed circuit board, papery copper foil are laminated Object, composite copper foil laminates or polymer impregnated glass fibre class copper foil laminates.The package substrate 10 may include mutually linking Structure, such as redistribution layer (RDL) or earth element.
Then, chip 12 is provided.The chip 12 includes surface 121, the surface 123 opposite with surface 121, metal structure 125 and the interdigital transducer IDT (not shown) on surface 121.The chip 12 is SAW filter.The metal Structure 125 can be tin ball, metal column or other structures commonly used in the art.Pass through upside-down mounting die bond (Flip-Chip Die Bond, FC Die Bond) mode the chip 12 is set to the surface 101 of package substrate 10 via metal structure 125, make It obtains metal structure 125 to connect with conductive contact 105, so that chip 12 may be electrically connected to package substrate by metal structure 125 10.The IDT for accommodating chip 12 is collectively formed with the surface 121 of chip 12, the surface 101 of package substrate 10 for the metal structure 125 Cavity 18.
As shown in Figure 2 b, glue film 14 is set in the surface of package substrate 10 101 by way of suppressing glue film 14, so that Glue film 14 extends to the height on covering surface 123 upward from the surface of package substrate 10 101 and seals cavity 18, to play Protect the effect of cavity 18.Glue film 14 is the colloid or dry film shape that can for example, form bearing height by processing fluidity difference At so that good protection of the cavity 18 by glue film 14.Then, technological means commonly used in the art is used to make glue film 14 solid Change.
As shown in Figure 2 c, hemisection (half cut) technique is used to remove cured part glue film 14 in package substrate 10 Surface 101 on form encapsulated space, remaining glue film 14 extends to and chip 12 upward from the surface of package substrate 10 101 Surface 123 roughly the same height and still seal cavity 18, to protect cavity 18.In some embodiments, remaining The thickness D of glue film 14 is (referring to Fig. 1 and Fig. 2 c) at least more than 1 micron.In another embodiment of the application, remaining glue film 14 Thickness D at least more than 10 microns.In the another embodiment of the application, the thickness D of remaining glue film 14 is micro- at least more than 20 Rice.The thickness D of remaining glue film 14 guarantees that when being packaged processing procedure to form packaging body 16, glue film 14 has enough intensity Prevent cavity 18 by destroying to protect the complete of cavity 18.
In another embodiment of the application, part glue film 14 can be removed using other this field any suitable techniques To form encapsulated space on the surface of package substrate 10 101, wherein remaining glue film 14 from the surface of package substrate 10 101 to Shangdi extends to the height on the surface 121 of at least above filter wafer 12 and seals cavity 18.In the another implementation of the application In example, remaining glue film 14 can extend to upward between surface 121 and surface 123 from the surface of package substrate 10 101 Height and seal cavity 18.In another embodiment of the application, remaining glue film 14 from the surface of package substrate 10 101 to Shangdi extends to above the height on surface 123 and seals cavity 18, and glue film 14 covers the surface 123 of chip 12.
As shown in Figure 2 d, packaging body 16 is formed using compression molding (compression molding) technique, so that encapsulation Body 16 at least covers surface 101, glue film 14 and the chip 12 of package substrate 10.The material of packaging body 16 can be commonly used in the art Various insulation synthetic resin, plastics or ceramic material, such as, but not limited to, epoxy resin.In some embodiments, it is formed The similar thermal expansion coefficient of the material of the thermal expansion coefficient and formation of the material of the packaging body 16 package substrate 10, to reduce collection At the warped degree of circuit package 100, for example, forming the thermal expansion coefficient of the material of the packaging body 16 and forming the package substrate The thermal expansion coefficient difference about ± 20% of 10 material, preferably, about ± 10%.Packaging body 16 and glue film 14 are by different materials It is formed.It is heat cured for forming the material of glue film 14, therefore glue film 14 will not melt again after by hot setting, from And glue film 14 will not be affected by temperature still seal cavity 18 during forming packaging body 16.Some In embodiment, the processing fluidity for forming the material of packaging body 16 is greater than the processing fluidity for forming the material of glue film 14.In addition, Material due to forming packaging body 16 has good processing fluidity, thus joint filling is stronger, thus forming packaging body 16 During can prevent steam from entering, to improve the reliability of integrated circuit package body 100.
In another embodiment of the application, transmission mold forming (transfer molding) or other this fields can be used Any suitable technique forms packaging body 16, so that packaging body 16 at least covers surface 101, glue film 14 and the crystalline substance of package substrate 10 Piece 12.
Then, the packaging body for completing injection molding is identified, the content of mark is personalized.Then, to multiple collection It is split at circuit package 100, to obtain integrated circuit package body 100 as shown in Figure 1.
Fig. 3 a-3c is the flow diagram that integrated circuit package body is manufactured according to another embodiment of the utility model, can Manufacture integrated circuit package body shown in FIG. 1.
As shown in Figure 3a, package substrate 10 is provided.The package substrate 10 includes surface 101, and the table opposite with surface 101 Face 103.Surface 101 is provided with one or more conductive contacts 105, and surface 103 is provided with one or more external pins and (does not show in figure Out).The package substrate 10 can be various package substrates commonly used in the art, such as printed circuit board, papery copper foil are laminated Object, composite copper foil laminates or polymer impregnated glass fibre class copper foil laminates.The package substrate 10 may include mutually linking Structure, such as redistribution layer (RDL) or earth element.
Then, chip 12 is provided.The chip 12 includes surface 121, the surface 123 opposite with surface 121, metal structure 125 and the interdigital transducer IDT (not shown) on surface 121.The chip 12 is SAW filter.The metal Structure 125 can be tin ball, metal column or other structures commonly used in the art.Pass through upside-down mounting die bond (Flip-Chip Die Bond, FC Die Bond) mode the chip 12 is set to the surface 101 of package substrate 10 via metal structure 125, make It obtains metal structure 125 to connect with conductive contact 105, so that chip 12 may be electrically connected to package substrate by metal structure 125 10.The IDT for accommodating chip 12 is collectively formed with the surface 121 of chip 12, the surface 101 of package substrate 10 for the metal structure 125 Cavity 18.
As shown in Figure 3b, glue film 14 is arranged in the surface of package substrate 10 101, so that glue film 14 by mode for dispensing glue It is extended to upward from the surface of package substrate 10 101 and the roughly the same height on the surface 123 of chip 12 and seals cavity 18, to play the role of protecting cavity 18.Glue film 14 is the glue that can for example, form bearing height by processing fluidity difference Body or dry film are formed, so that good protection of the cavity 18 by glue film 14.Then, made using technological means commonly used in the art Glue film 14 is obtained to solidify.
In some embodiments, the thickness D (referring to Fig. 3 b) of glue film 14 is at least more than 1 micron.In another reality of the application It applies in example, the thickness D of glue film 14 is at least more than 10 microns.In the another embodiment of the application, the thickness D of glue film 14 is at least big In 20 microns.The thickness D of glue film 14 guarantees that when being packaged processing procedure to form packaging body 16, glue film 14 has enough intensity Prevent cavity 18 by destroying to protect the complete of cavity 18.
In another embodiment of the application, glue film 14 extends at least high upward from the surface of package substrate 10 101 In the surface of filter wafer 12 121 height and seal cavity 18.In the another embodiment of the application, glue film 14 can be from envelope The height that is extended between surface 121 and surface 123 upward of surface 101 of dress substrate 10 simultaneously seals cavity 18.At this In another embodiment of application, glue film 14 extends to above the height on surface 123 simultaneously from the surface of package substrate 10 101 upward Cavity 18 is sealed, and glue film 14 covers the surface 123 of chip 12.
In another embodiment of the application, glue film 14 is set by way of drawing glue in the surface of package substrate 10 101.
As shown in Figure 3c, packaging body 16 is formed using compression molding (compression molding) technique, so that encapsulation Body 16 at least covers surface 101, glue film 14 and the chip 12 of package substrate 10.The material of packaging body 16 can be commonly used in the art Various insulation synthetic resin, plastics or ceramic material, such as, but not limited to, epoxy resin.In some embodiments, it is formed The similar thermal expansion coefficient of the material of the thermal expansion coefficient and formation of the material of the packaging body 16 package substrate 10, to reduce collection At the warped degree of circuit package 100, for example, forming the thermal expansion coefficient of the material of the packaging body 16 and forming the package substrate The thermal expansion coefficient difference about ± 20% of 10 material, preferably, about ± 10%.Packaging body 16 and glue film 14 are by different materials It is formed.It is heat cured for forming the material of glue film 14, therefore glue film 14 will not melt again after by hot setting, from And glue film 14 will not be affected by temperature still seal cavity 18 during forming packaging body 16.Some In embodiment, the processing fluidity for forming the material of packaging body 16 is greater than the processing fluidity for forming the material of glue film 14.In addition, Material due to forming packaging body 16 has good processing fluidity, thus joint filling is stronger, thus forming packaging body 16 During can prevent steam from entering, to improve the reliability of integrated circuit package body 100.
In another embodiment of the application, transmission mold forming (transfer molding) or other this fields can be used Any suitable technique forms packaging body 16, so that packaging body 16 at least covers surface 101, glue film 14 and the crystalline substance of package substrate 10 Piece 12.
Then, the packaging body for completing injection molding is identified, the content of mark is personalized.Then, to multiple collection It is split at circuit package 100, to obtain integrated circuit package body 100 as shown in Figure 1.
The embodiment of the present application guarantees the complete of IDT cavity by using glue film, has manufacturing cost low, packaging technology letter Many advantages, such as list, suitable rapid batch production.
The technology contents and technical characterstic of the utility model have revealed that as above, however those skilled in the art still may be used Can teaching based on the utility model and announcement and make various replacements and modification without departing substantially from the spirit of the present invention.Therefore, originally The protection scope of utility model should be not limited to the revealed content of embodiment, and should include various replacing without departing substantially from the utility model It changes and modifies, and covered by present patent application claims.

Claims (7)

1. a kind of integrated circuit package body, characterized in that it comprises:
The surface of package substrate, the package substrate is provided with conductive contact;
Chip comprising:
First surface;
Second surface, the second surface are opposite with the first surface;And
Metal structure is set to the first surface;The metal structure is connect with the conductive contact, and with the chip The first surface, the package substrate the surface cavity is collectively formed;
Glue film extends to the height of the first surface of at least above described chip from the surface of the package substrate And seal the cavity;And
Packaging body covers the package substrate, the glue film and the chip.
2. integrated circuit package body according to claim 1, which is characterized in that the glue film by processing fluidity difference glue Body or dry film are formed.
3. integrated circuit package body according to claim 1, which is characterized in that the glue film covers the second of the chip Surface.
4. integrated circuit package body described in any one of -3 claims according to claim 1, which is characterized in that the glue film Thickness at least more than 1 micron.
5. integrated circuit package body described in any one of -3 claims according to claim 1, which is characterized in that the encapsulation Body and the glue film are formed from different materials, and the processing fluidity for forming the material of the packaging body, which is greater than, forms the glue film Material processing fluidity.
6. integrated circuit package body described in any one of -3 claims according to claim 1, which is characterized in that described in formation The similar thermal expansion coefficient of the material of the thermal expansion coefficient and formation package substrate of the material of packaging body.
7. integrated circuit package body described in any one of -3 claims according to claim 1, which is characterized in that the chip It is filter wafer.
CN201821394117.2U 2018-08-28 2018-08-28 Integrated circuit package body Active CN208904000U (en)

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Application Number Priority Date Filing Date Title
CN201821394117.2U CN208904000U (en) 2018-08-28 2018-08-28 Integrated circuit package body

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Application Number Priority Date Filing Date Title
CN201821394117.2U CN208904000U (en) 2018-08-28 2018-08-28 Integrated circuit package body

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Publication Number Publication Date
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110689820A (en) * 2019-10-09 2020-01-14 深圳市科伦特电子有限公司 LED lamp panel and manufacturing process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110689820A (en) * 2019-10-09 2020-01-14 深圳市科伦特电子有限公司 LED lamp panel and manufacturing process

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Address after: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province

Patentee after: Riyuexin semiconductor (Suzhou) Co.,Ltd.

Address before: 215021 Suzhou City, Jiangsu Province No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou City, Jiangsu Province

Patentee before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd.

CP03 Change of name, title or address