CN208888807U - A kind of automatic addressing system of universal serial bus - Google Patents
A kind of automatic addressing system of universal serial bus Download PDFInfo
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- CN208888807U CN208888807U CN201821759827.0U CN201821759827U CN208888807U CN 208888807 U CN208888807 U CN 208888807U CN 201821759827 U CN201821759827 U CN 201821759827U CN 208888807 U CN208888807 U CN 208888807U
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Abstract
The utility model relates to a kind of automatic addressing systems of universal serial bus, including multiple equipment with MCU, it is connected between the RX/TX interface of the MCU of each equipment by one wire system half-duplex communication circuit, also confirms that circuit is connected by mode between prime equipment and subsequent equipment.The utility model can be realized the automatic addressing of bus apparatus.
Description
Technical field
The utility model relates to technical field of industrial control, more particularly to a kind of automatic addressing system of universal serial bus.
Background technique
In most cases, in industrial control system, for realize it is digital control would generally be there are two types of control mode: Yi Zhongwei
Point-to-point control, the i.e. control of orientation equipment, realize the Digital Control of single equipment；One kind is bus-control, that is, is used
The mode of communication bus realizes the Digital Control of more equipment.In actual field equipment management, and serial bus type controlling party
Formula is using in the majority, such as ModBus bus and PMBus bus etc..When being controlled, need to address field device, mesh
Preceding method is to give each field device one address using manual mode, using being inconvenient.
Utility model content
The technical problem to be solved by the utility model is to provide a kind of automatic addressing systems of universal serial bus, can be realized
The automatic addressing of bus apparatus.
The technical scheme adopted by the utility model to solve the technical problem is as follows: providing a kind of automatic addressing of universal serial bus
System, it is logical by one wire system half-duplex between the RX/TX interface of the MCU of each equipment including multiple equipment with MCU
Believe circuit connection, also confirms that circuit is connected by mode between prime equipment and subsequent equipment.
The one wire system half-duplex communication circuit includes transmitting portion and receiving portion, and the transmitting portion includes the one or three
The base stage of pole pipe and the second triode, first triode is connected with the collector of the second triode, and collector and input are defeated
Outlet is connected, emitter ground connection；The base stage of second triode is connected with the transmitting terminal of MCU, emitter ground connection；Receiving portion
Including operational amplifier, the inverting input terminal of the operational amplifier is connected with input/output terminal, normal phase input end and reference electricity
Pressure is connected, and output end is connected with the receiving end of MCU.
The mode confirmation circuit includes prime mode confirmation circuit and rear class mode confirmation circuit, and the prime mode is true
Recognizing circuit includes first resistor and second resistance, wherein the AD input interface phase of one end of first resistor and prime equipment MCU
Even, the other end is connected with one end of second resistance, and the other end of second resistance is grounded, one end of the second resistance also with the same level
The end LIN_A of equipment MCU is connected；The rear class mode confirmation circuit includes 3rd resistor, one end of the 3rd resistor and electricity
Source is connected, and the other end is connected with the end LIN_B of the AD input interface of prime equipment MCU and the same level equipment MCU respectively.
An invalid address is stored in each equipment.
Beneficial effect
Due to the adoption of the above technical solution, the utility model compared with prior art, has the following advantages that and accumulates
Pole effect: digital communication and configuration feature when the utility model uses the serial digital interface based on TTL to realize automatic addressing,
Integrated one wire system half-duplex communication circuit is wherein sent and received using communication.System model confirms that circuit uses input and output
Two-stage mode, to confirm the transceiver mode of equipment.In system, configure equipment main control MCU addressed in pattern switching,
And the digital communication during automatic addressing.In the pattern switching of equipment, uses analog circuit and AD is combined to sample with this
To realize being automatically repaired for the address after automatic pattern switching and new equipment addition.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model；
Fig. 2 is one wire system half-duplex communication circuit figure in the utility model；
Fig. 3 is the circuit diagram of mode confirmation circuit prime part in the utility model；
Fig. 4 is the circuit diagram of mode confirmation circuit rear class part in the utility model.
Specific embodiment
The present invention will be further illustrated below in conjunction with specific embodiments.It should be understood that these embodiments are merely to illustrate this
Utility model rather than limitation the scope of the utility model.In addition, it should also be understood that, in the content for having read the utility model instruction
Later, those skilled in the art can make various changes or modifications the utility model, and such equivalent forms equally fall within this Shen
It please the appended claims limited range.
The embodiments of the present invention is related to a kind of automatic addressing system of universal serial bus, as shown in Figure 1, including multiple
Equipment with MCU is connected by one wire system half-duplex communication circuit between the RX/TX interface of the MCU of each equipment, preceding
Also confirm that circuit is connected by mode between grade equipment and subsequent equipment.After the system electrification, equipment is true according to front stage mode
Recognize circuit and determine the position of equipment in the bus, after having equipment addition, is carried out certainly in conjunction with addressing communication and defaulting confirmation circuit
Adapt to addressing.
For the automatic addressing communication for realizing bus apparatus, serial single line half-duplex operation mode is used in system design,
The most simplified of communications line is realized with this.As shown in Fig. 2, one wire system half-duplex communication circuit includes transmitting portion and receiving unit
Point, the transmitting portion includes the first triode Q1 and the second triode Q2, the base stage and the two or three of the first triode Q1
The collector of pole pipe Q2 is connected, and collector is connected with input/output terminal, emitter ground connection；The base stage of the second triode Q2 and
The transmitting terminal of MCU is connected, emitter ground connection；Receiving portion includes operational amplifier, the inverting input terminal of the operational amplifier
It is connected with input/output terminal, normal phase input end is connected with reference voltage, and output end is connected with the receiving end of MCU.
The one wire system half-duplex communication circuit is that the serial communication based on TTL carries out single line half duplex mode of communication, knot
Certain level shifting circuit has been closed, it is made to increase corresponding driving capability.The circuit is by the data transmission and reception of Transistor-Transistor Logic level
The single line mode for being converted to specified level externally carries out data communication.
The transmission (TX) of corresponding equipment TTL digital communication and RX (reception) are ultimately converted to the Lin of external input and output, with
This realizes the digital communication of bus apparatus.Transmitting portion is passed through two-stage transistor control circuit in circuit and is realized to specified level
Conversion；Digital signal in input signal cable is compared by receiving portion with given voltage, while realizing clamper, is realized
Number isolation, ensure that the power protection of the control system of signal anti-interference and system module.
As shown in Figure 3 and Figure 4, mode confirmation circuit includes prime mode confirmation circuit and rear class mode confirmation circuit, institute
Stating prime mode confirmation circuit includes first resistor R1 and second resistance R17, wherein one end of first resistor R1 and prime equipment
The AD input interface of MCU is connected, and the other end is connected with one end of second resistance R17, the other end ground connection of second resistance R17, institute
The one end for stating second resistance R17 is also connected with the end LIN_A of the same level equipment MCU；The rear class mode confirmation circuit includes third
Resistance R13, one end of the 3rd resistor R13 are connected with power end, the other end AD input interface with prime equipment MCU respectively
It is connected with the end LIN_B of the same level equipment MCU.
System confirms that circuit confirms the position of equipment in the bus by front stage mode, and such as equipment is opened bus
Begin, placed in the middle or ending.In Fig. 3, prime mode confirms corresponding AD input in the A1 access prime device controller in circuit
Interface, to confirm whether equipment has other equipment in the prime of bus；In Fig. 4, the A2 in rear class mode confirmation circuit is connect
Enter the AD input interface in subsequent equipment controller, confirming whether equipment has an other equipment in rear class, and output refers to
Determine the communication that level is addressed to inform subsequent equipment.
In use, one invalid address of main control processor caching default of equipment, the mark as unallocated address.When into
After row system wiring, device handler in bus determines whether prime deposits according to the sample circuit in prime mode circuit
In equipment, and level sampling is carried out first for rear class mode confirmation circuit, it has been determined that whether access subsequent equipment, make if without if
For the end equipment of bus；Subsequent equipment if it exists, then after row address determines, modification rear class mode confirms circuit corresponding A D
Sample port is IO output, to inform that subsequent equipment carries out addressing communication, to complete the realization of automatic addressing.When there is new equipment
It is added, then can carry out the adaptive of equipment addressing automatically according to addition point.
It is not difficult to find that digital communication when the utility model uses the serial digital interface based on TTL to realize automatic addressing
With configuration feature, integrated one wire system half-duplex communication circuit is sent and received wherein using and communicating.System model confirms circuit
Using input and output two-stage mode, to confirm the transceiver mode of equipment.In system, the main control MCU for configuring equipment is addressed
In pattern switching and the digital communication during automatic addressing.In the pattern switching of equipment, using analog circuit and tie
It closes AD sampling and being automatically repaired for the address after automatic pattern switching and new equipment are added is realized with this.
Claims (4)
1. the automatic addressing system of a kind of universal serial bus, including multiple equipment with MCU, which is characterized in that each band
Have and connected between the RX/TX interface of the MCU of the equipment of MCU by one wire system half-duplex communication circuit, prime equipment and rear class are set
Also confirm that circuit is connected by mode between standby.
2. the automatic addressing system of universal serial bus according to claim 1, which is characterized in that the one wire system half-duplex is logical
Letter circuit includes transmitting portion and receiving portion, and the transmitting portion includes the first triode and the second triode, and described first
The base stage of triode is connected with the collector of the second triode, and collector is connected with input/output terminal, emitter ground connection；Described
The base stage of two triodes is connected with the transmitting terminal of MCU, emitter ground connection；Receiving portion includes operational amplifier, and the operation is put
The inverting input terminal of big device is connected with input/output terminal, and normal phase input end is connected with reference voltage, the receiving end of output end and MCU
It is connected.
3. the automatic addressing system of universal serial bus according to claim 1, which is characterized in that the mode confirms circuit packet
Prime mode confirmation circuit and rear class mode confirmation circuit are included, the prime mode confirmation circuit includes first resistor and the second electricity
Resistance, wherein one end of first resistor is connected with the AD input interface of prime equipment MCU, one end phase of the other end and second resistance
Even, the other end ground connection of second resistance, one end of the second resistance is also connected with the end LIN_A of the same level equipment MCU；After described
Grade mode confirmation circuit includes 3rd resistor, and one end of the 3rd resistor is connected with power end, and the other end is set with prime respectively
The AD input interface of standby MCU is connected with the end LIN_B of the same level equipment MCU.
4. the automatic addressing system of universal serial bus according to claim 1, which is characterized in that be stored with one in each equipment
A invalid address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821759827.0U CN208888807U (en) | 2018-10-29 | 2018-10-29 | A kind of automatic addressing system of universal serial bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821759827.0U CN208888807U (en) | 2018-10-29 | 2018-10-29 | A kind of automatic addressing system of universal serial bus |
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| Publication Number | Publication Date |
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| CN208888807U true CN208888807U (en) | 2019-05-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821759827.0U Active CN208888807U (en) | 2018-10-29 | 2018-10-29 | A kind of automatic addressing system of universal serial bus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114553830A (en) * | 2022-02-14 | 2022-05-27 | 浙江台州昀瑞电子科技有限公司 | Serial port based bidirectional cascade communication circuit system and addressing method |
-
2018
- 2018-10-29 CN CN201821759827.0U patent/CN208888807U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114553830A (en) * | 2022-02-14 | 2022-05-27 | 浙江台州昀瑞电子科技有限公司 | Serial port based bidirectional cascade communication circuit system and addressing method |
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