CN208888626U - A kind of automatic Pilot computing system - Google Patents
A kind of automatic Pilot computing system Download PDFInfo
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- CN208888626U CN208888626U CN201821926132.7U CN201821926132U CN208888626U CN 208888626 U CN208888626 U CN 208888626U CN 201821926132 U CN201821926132 U CN 201821926132U CN 208888626 U CN208888626 U CN 208888626U
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Abstract
The utility model discloses a kind of automatic Pilot computing system, including MPSOC master unit, MPSOC subelement and crosspoint, and the MPSOC master unit is connect with MPSOC subelement, crosspoint respectively；MPSOC master unit receives laser radar data and vision data, and handle first laser radar data and First look data, wherein, the laser radar data includes first laser radar data and second laser radar data, and the vision data includes First look data and the second vision data；MPSOC subelement receives and processes the second laser radar data and the second vision data of the transmission of MPSOC master unit, and processing result is sent back MPSOC master unit；Crosspoint is equipped with Ethernet expansion interface.Crosspoint realizes common Ethernet extension.While technical solutions of the utility model are intended to reduce computing system volume, improve reliability, reinforces and extend the computing capability of computing system, the computing system is made to can be applied to automatic Pilot scene.
Description
Technical field
The utility model relates to automatic Pilot technical field, in particular to a kind of automatic Pilot computing system.
Background technique
Traditional computing system mostly uses greatly industrial personal computer, and industrial personal computer computing capability is strong, but volume is big, and reliability is low, power consumption
Height is not suitable for the very high automatic Pilot scene application of vehicular applications, especially reliability requirement.
Utility model content
The main purpose of the utility model is to provide a kind of automatic Pilot computing system, it is intended to reduce computing system volume,
While improving reliability, reinforces and extend the computing capability of computing system, the computing system is made to can be applied to automatic Pilot
Scene.
To achieve the above object, the utility model proposes automatic Pilot computing system, including MPSOC master unit, MPSOC
Subelement and crosspoint, the MPSOC master unit are connect with MPSOC subelement, crosspoint respectively；MPSOC master unit connects
Laser radar data and vision data are received, and handles reason first laser radar data and First look data, wherein the laser
Radar data includes first laser radar data and second laser radar data, and the vision data includes First look data
And second vision data；
MPSOC subelement receives and processes the second laser radar data and the second vision data of MPSOC master unit transmission,
And processing result is sent back into MPSOC master unit；Crosspoint is equipped with Ethernet expansion interface.
It preferably, further include power supply unit, the power supply unit is connect with the MPSOC subelement, the power supply unit
It is connect by MPSOC subelement with the MPSOC master unit, passes through the MPSOC subelement and the MPSOC master unit and institute
State crosspoint connection.
Preferably, the MPSOC master unit is connected by GPIO bus extender and MIPI interface and the MPSOC subelement
It connects.
Preferably, the MPSOC master unit is connect by RGMII interface and SPI interface with the crosspoint.
Preferably, the MPSOC master unit is also respectively connected with camera and laser radar.
Preferably, MPSOC master unit includes the first MOSOC processor and serdes chip, the first MOSOC processor
Including the first PS module and the first PL module, the first PS module, the first PL module are connect with serdes chip respectively；
The first PS module includes with the first ethernet controller, CAN controller, 2 I2C controllers, 2 first
SDIO controller, the first PCIE controller and the first DDR controller；
First ethernet controller is connect by RGMII interface and SPI interface with crosspoint, the first ether
Net controller is also connected with the first ethernet PHY chip, and the first ethernet PHY chip connects the first network interface；The CAN controller connects
CAN transceiver is connect, the CAN transceiver is connect with vehicle CAN bus；One of them described I2C controller connects serdes core
Piece, another I2C controller are separately connected power sensor, temperature sensor；One first SDIO controller connects SD
Card, another described first SDIO controller connect EMMC memory；
The first PL module includes the second DDR controller, the external first DDR memory of the second DDR controller；
The serdes chip is connect with camera, the first PL module by MIPI interface and DVP interface with
The connection of serdes chip, the first PL module are connect by parallel interface and MIPI interface with MPSOC subelement, described parallel
Interface includes multiple GPIO.
Preferably, the MPSOC subelement includes the 2nd MOSOC processor, and the 2nd MOSOC processor includes second
PS module and the 2nd PL module；
The 2nd PS module include with the second too net controller, 2 the second SDIO controllers, the 2nd PCIE controllers,
And third DDR controller；Second ethernet controller connects the second ethernet PHY chip, the connection of the second ethernet PHY chip
Second network interface, second SDIO controller connect SD card, another described second SDIO controller connection EMMC storage
Device；
The 2nd PL module includes the 4th DDR controller, the external 2nd DDR memory of the 4th DDR controller；It is described
2nd PL module is connect by parallel interface and MIPI interface with MPSOC master unit, and the parallel interface includes multiple GPIO.
Preferably, described further includes power supply unit, and the power supply unit is connect with the MPSOC subelement, the power supply
Unit is connect by MPSOC subelement with the MPSOC master unit, and the MPSOC subelement and the MPSOC master unit are passed through
It is connect with the crosspoint.
Preferably, the MPSOC master unit and MPSOC subelement further include clock unit, and the clock unit includes being
System reference clock, memory reference clock and serdes reference clock.
Preferably, the serdes chip is also connected with FAKRA connector, and is connected by FAKRA connector and camera
It connects.
Preferably, the first PL module is also connected with HDMI transmitter, and the HDMI transmitter connects filter, described
Filter passes through HDMI attachment base connection display equipment.
The utility model automatic Pilot computing system, including MPSOC master unit, MPSOC subelement and crosspoint, it is described
MPSOC master unit is connect with MPSOC subelement, crosspoint respectively；MPSOC master unit receives laser radar data and vision number
According to, and handle the laser radar data of a part and the vision data of a part；MPSOC subelement receives and processes MPSOC master
Another part laser radar data and another part vision data that unit is sent, and processing result is sent back into the main list of MPSOC
Member expands the logical resource of MPSOC master unit；Crosspoint extends common Ethernet.By using MPSOC unit, MPSOC is mono-
It is integrated with multiple processor cores in member, and there is powerful calculating operational efficiency, passes through MPSOC master unit and MPSOC subelement
A part of data, when the received data volume of MPSOC master unit is big, can be sent to MPSOC subelement while located by connection
Reason, and there are multiple flexible interfaces and resource expansion to design module for MPSOC master unit and MPSOC subelement, it can be with modularization
It arranges in pairs or groups other sensors and convergence platform, further strengthens and extend the computing capability of computing system, extended using crosspoint
Common Ethernet strengthens the transmission rate of system, and the computing system is small in size, high reliablity, and the computing system is enable to answer
For automatic Pilot scene, automatic Pilot is made to can speed up processing deep learning and data fusion.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model automatic Pilot computing system first embodiment；
Fig. 2 is the structural schematic diagram of the utility model automatic Pilot computing system second embodiment；
Fig. 3 is the structural schematic diagram of the utility model automatic Pilot computing system 3rd embodiment；
Fig. 4 is the structural schematic diagram of the utility model automatic Pilot computing system fourth embodiment；
Fig. 5 is the structural schematic diagram of the 5th embodiment of the utility model automatic Pilot computing system.
Drawing reference numeral explanation:
| MPSOC master unit 1 | MPSOC subelement 2 | Crosspoint 3 | Power supply unit 4 |
| Third network interface 5 | First PCIE controller 6 | SD card 7 | CAN transceiver 8 |
| First network interface 9 | 2nd PCIE controller 10 | Plug connector 11 | Second network interface 12 |
| FAKRA connector 13 | HDMI connector 14 | —— | —— |
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
With reference to the accompanying drawing and specific embodiment is described further with regard to the technical solution of the utility model.It should manage
Solution, specific embodiment described herein are only used to explain the utility model, are not used to limit the utility model.
The utility model proposes a kind of automatic Pilot computing systems, and small in size, high reliablity, computing capability is strong, the calculating
System can be applied to automatic Pilot scene.
It is the structural schematic diagram of the utility model automatic Pilot computing system first embodiment referring to figs. 1 to 5, Fig. 1；Fig. 2
For the structural schematic diagram of the utility model automatic Pilot computing system second embodiment；Fig. 3 is the utility model automatic Pilot meter
The structural schematic diagram of calculation system 3rd embodiment；Fig. 4 is the structure of the utility model automatic Pilot computing system fourth embodiment
Schematic diagram；Fig. 5 is the structural schematic diagram of the 5th embodiment of the utility model automatic Pilot computing system；
In the utility model embodiment, the automatic Pilot computing system, including MPSOC master unit 1, MPSOC subelement 2
With crosspoint 3, the MPSOC master unit 1 is connect with MPSOC subelement 2, crosspoint 3 respectively；MPSOC master unit 1 receives
Laser radar data and vision data, and handle first laser radar data and First look data, wherein the laser radar
Data include first laser radar data and second laser radar data, the vision data include First look data and
Second vision data；
MPSOC subelement 2 receives and processes the second laser radar data and the second vision number of the transmission of MPSOC master unit 1
According to, and processing result is sent back into MPSOC master unit 1, expand the logical resource of MPSOC master unit 1；Crosspoint 3 be equipped with
Too net expansion interface；As shown in Figure 1.
Technical solutions of the utility model are integrated with multiple processor cores on MPSOC unit by using MPSOC unit, and
It with powerful calculating operational efficiency, is connected by MPSOC master unit 1 and MPSOC subelement 2, MPSOC master unit 1 is received
When data volume is big, a part of data can be sent to MPSOC subelement 2 while being handled, and 1 He of MPSOC master unit
There are MPSOC subelement 2 multiple flexible interfaces and resource expansion to design module, with the other sensors of modularization collocation and can melt
Platform is closed, further strengthens and extends the computing capability of computing system, common Ethernet is extended using crosspoint 3, is strengthened
The transmission rate of system, the computing system is small in size, high reliablity, and the computing system is made to can be applied to automatic Pilot scene,
Automatic Pilot is set to can speed up processing deep learning and data fusion.
It further, further include power supply unit 4, the power supply unit 4 is connect with the MPSOC subelement 2, the power supply
Unit 4 is connect by MPSOC subelement 2 with the MPSOC master unit 1, and the MPSOC subelement 2 and the MPSOC master are passed through
Unit 1 is connect with the crosspoint 3, as shown in Figure 2.
The power supply that power supply unit 4 is responsible for providing in automobile is allocated or is converted into circuit devcie required voltage, leads to
The intelligent management for crossing power supply unit 4 reduces the power consumption of computing system, and power supply unit 4 connects automobile electricity by plug connector 11
Source obtains from automobile power source and powers, provide power supply for MPSOC master unit 1, the MPSOC subelement 2, crosspoint 3, should
Plug connector 11 is also connected with automobile CAN-bus, is connect by automobile CAN-bus with CAN transceiver 8.The main electricity of automobile FPGA board
Source input is 12V or 24V, and the power supply of all power modules requires to generate from this 12V or 24V on plate.It is bigger for electric current
Load, power supply unit 4 uses switch power module, smaller for electric current or to the higher load of power requirement, power supply
Unit 4 is using LDO (low pressure difference linear voltage regulator) chip as power supply chip.Power supply unit 4 is to MPSOC master unit 1, described
MPSOC subelement 2, crosspoint 3 provide the voltages such as 5V, 3.3V, 2.5V, 1.8V, 1.2V, 0.85V and 0.6V, and to meet
MPSOC master unit 1, MPSOC subelement 2, crosspoint 3 to every kind of voltage requirements, power consumption demand, power supply characteristic index demand,
And also to support the monitoring of the control and power supply status to electric sequence.In order to achieve this goal, power supply unit 4 uses CPLD
(Complex Programmable Logic Devices) the control other modules of whole plate power on.
Further, the MPSOC master unit 1 is single by GPIO bus extender and MIPI interface and MPSOC
Member 2 connects.
MPSOC master unit 1 is controlled by the asynchronous serial communication of UART asynchronous receiving-transmitting transmitter with MPSOC subelement 2
Order and low volume data interaction；There are multiple GPIO signals to be connected between MPSOC master unit 1 and MPSOC subelement 2, such as has 72
A GPIO signal is connected, these signals are all to be connected by the PL module of MPSOC master unit 1 with the PL module of MPSOC subelement 2
And may be used as high speed GPIO, multiple GPIO constitute parallel communication interfaces, bandwidth are improved, for MPSOC master unit 1 to, MPSOC
Vision data or treated result data are transmitted between subelement 2；MIPI interface is single to MPSOC for MPSOC master unit 1
Member 2 transmits vision data, and MIPI CSI2.0 interface is corresponding with MIPI CSI2.0 interface standard；MIPI CSI2.0 interface mark
Standard is MIPI (Mobile Industry Processor Interface, i.e. mobile industry processor interface) camera interface
The upgraded version of standard.
Further, the MPSOC master unit 1 is connect by RGMII interface and SPI interface with the crosspoint 3.
Crosspoint 3 is for realizing the extension of common Ethernet interface.In hardware design, including common Ethernet exchanging core
Piece.Common Ethernet switching chip is corresponding with standard ethernet, standard ethernet can be understood as it is all kinds of it is common it is traditional with
Too net；Crosspoint 3 is externally provided with third network interface 5, and the third network interface 5 can be 3, and the third network interface 5 includes
RJ45 Ethernet interface is internally connected by RGMII interface and SPI interface with MPSOC.RGMII interface (Reduced
Gigabit Media Independent Interface), i.e. Gigabit Media stand-alone interface.RGMII interface can be used 4
Bit data interface, work clock 125MHz, and in rising edge and failing edge simultaneous transmission data, transmission rate is reachable
1000Mbps can reduce circuit cost using RGMII interface, and reduce the number of pins for realizing the device of the interface (such as from 25
It is reduced to 14).The MPSOC master unit 1 carries out laser radar data by RGMII interface and SPI interface and crosspoint 3
With vision data interaction, SPI interface is synchronous serial Peripheral Interface.
Further, the MPSOC master unit 1 is also respectively connected with camera and laser radar.
MPSOC master unit 1 is the core processing unit of system, is separately connected camera and laser radar, is responsible for processing and swashs
Optical radar data and vision data.The Serdes chip of MPSOC master unit 1 connects camera, and Serdes chip is connect by MIPI
Mouth or DVP interface are connected with the PL module of MPSOC master unit 1, and the vision data that Serdes chip receives multi-path camera is laggard
Row unstrings, then the vision data after unstringing is sent to PL resume module, and PL module can receive multichannel 720 by MIPI interface and divide
The vision data of the camera of 30 frame of resolution, or the vision number of the camera by 720 resolution ratio of DVP interface multichannel, 30 frame
According to MPSOC master unit 1 can receive the point cloud data of No. 3 laser radars by network interface connection laser radar.
Further, MPSOC master unit 1 includes the first MOSOC processor and serdes chip, at the first MOSOC
Managing device includes the first PS module and the first PL module, and the first PS module, the first PL module are connect with serdes chip respectively；
The first PS module includes with the first ethernet controller, CAN controller, 2 I2C controllers, 2 first
SDIO controller, the first PCIE controller 6 and the first DDR controller；
First ethernet controller is connect by RGMII interface and SPI interface with crosspoint 3, first with
Too net controller is also connected with the first ethernet PHY chip, and the first ethernet PHY chip connects the first network interface 9；The CAN control
Device connects CAN transceiver 8, and the CAN transceiver 8 is connect with vehicle CAN bus；One of them described I2C controller connection
Serdes chip, another I2C controller are separately connected power sensor, temperature sensor；One the first SDIO control
Device connects SD card 7, another described first SDIO controller connects EMMC memory；
The first PL module includes the second DDR controller, the external first DDR memory of the second DDR controller；
The serdes chip is connect with camera, the first PL module by MIPI interface and DVP interface with
The connection of serdes chip, the first PL module are connect by parallel interface and MIPI interface with MPSOC subelement, described parallel
Interface includes multiple GPIO, as shown in Figure 3；
MOSOC master unit includes the first MOSOC processor (FPGA+ARM+GPU) and serdes chip.At first MOSOC
Managing device includes the first PS module and the first PL module on hardware.First PS module includes the first DDR controller (8 of 72 bits
Bit is used as ECC function), it is possible to provide the memory headroom of 2.5GB or more.The SERDES of first PS module is configured to
First PCIE controller 6 of Endpoint attribute is reserved resource expansion and is used, passes through the attachment base and gold of the first PCIE controller 6
Finger can be cascaded with other board systems, and the interaction of very fast high-bandwidth data and resource are spreaded, such as this calculating acceleration system two
A or multiple connections or this calculating acceleration system are connected with emerging system.
PCIE controller is a kind of controller of high speed serialization computer bus standard, and the first PCIE controller 6 includes
PCIe2.0x4Lanes controller, described " 2.0 " are second generation standard, bus speed 5GT/s；" x4Lanes " refers to use
Four buses (Lane), a bus support the transmission rate of 500MB/s, and MPSOC master unit 1 can integrate two
The attribute of PCIe2.0x4Lanes controller, controller can be configured according to actual needs, such as be configured to RC (Root
Complex, i.e. root complex) attribute or EP (Endpoint, i.e. endpoint device) attribute.Wherein, by one of them
PCIe2.0x4Lanes controller is configured to RC attribute；By the PCIe2.0x4Lanes controller, MPSOC master unit 1 and its
Its board data interaction, another PCIe2.0x4Lanes controller can be configured as RC attribute, and be connected to clamping plate type
PCIE connector, to reserve resource expansion.
First ethernet controller GEM2 of PS module connects (MAC and MAC are interconnected) with crosspoint 3 with RGMII interface,
Plug-in first ethernet PHY chip of GEM3 connects the first network interface 9, and the first network interface 9 includes RJ45 Ethernet interface, connects laser thunder
It reaches, for debugging or accessing laser radar data.The CAN controller of PS module connects CAN transceiver 8, the CAN transceiver 8
It is connect by CAN interface with vehicle CAN bus；Realize that the other system data communications of vehicle are handed over by connecting with vehicle CAN bus
Mutually, Information expansion, such as with the ECU system of vehicle or sensor communication interaction etc. obtains the motion state of vehicle, real-time vehicle
The information such as speed, wheel steering；
First PS module includes two the first SDIO controllers, one of them first SDIO controller mounts EMMC, is used for
The storage of MPSOC program；Another first SDIO controller mounts SD card 7, uses for debugging.I2C (the synchronous serial of PS module
Bus) controller is connected to serdes chip completion serdes and the configuration of camera initializes, and one of I2C controller connects
It is connected to the detection that the chips such as power sensor and temperature sensor complete whole plate power and temperature.
The first PL module can example dissolve the second DDR controller of 80 bits, the memory headroom of 2.5GB is provided, may be used also
First DDR memory of external 5 bits；
Serdes chip is connect with camera, the first PL module HP BANK can example dissolve MIPI interface, the MIPI interface
Including MIPI CSI-2RX, the first PL module is connect by MIPI interface with serdes chip, and serdes chip is by vision data
It unstrings and is sent to the end the PL processing of MPSOC for MIPI or DVP interface data.PL module can pass through 4 tunnel vision of MIPI interface
Data, vision data include LVDS vision data.PL module connects 2 road cameras of serdes chip by DVP interface
The vision data (outer synchronous) that sends of parallel interface, parallel interface includes multiple GPIO.PL module reserves MIPI interface and 72
The parallel interface of bit is connected to MPSOC subelement 2, realizes that the data between MPSOC master unit 1 and MPSOC subelement 2 are handed over
Mutually.
Further, the MPSOC subelement 2 includes the 2nd MOSOC processor, and the 2nd MOSOC processor includes
2nd PS module and the 2nd PL module；
The 2nd PS module includes the second ethernet controller, 2 the second SDIO controllers, the 2nd PCIE interfaces, with
And third DDR controller；Second ethernet controller connects the second ethernet PHY chip, the second ethernet PHY chip connection the
Two network interfaces 12, second SDIO controller connect SD card 7, another described second SDIO controller connection EMMC storage
Device；
The 2nd PL module includes the 4th DDR controller, the external 2nd DDR memory of the 4th DDR controller；It is described
2nd PL module is connect by parallel interface and MIPI interface with MPSOC master unit 1, and the parallel interface includes multiple GPIO,
As shown in Figure 3.
MPSOC subelement 2 is used to expand the logical resource of MPSOC master unit 1.Master unit is assisted to carry out the processing of data,
The calculating operating rate of quickening system, in hardware design, including the 2nd MOSOC processor (FPGA+ARM+GPU).Second
MPSOC processor includes the 2nd PS module and the 2nd PL module on hardware.2nd PS module contains the DDR control of 72 bits
Device processed (8 bits are used as ECC function).The SERDES of 2nd PS module is configured to the 2nd PCIE of Root complex attribute
Controller 10, the 2nd PCIE controller 10 include PCIe2.0x4Lanes controller, reserve resource expansion and use.2nd PS
The plug-in ethernet PHY chip of second ethernet controller GEM3 of module is connected to the second network interface of rear panel 12, and described
Two network interfaces 12 include RJ45 Ethernet interface, can also be free by multiple Ethernet interfaces and extraneous other systems for debugging
Flexibly connection and resource are spreaded.2nd PS module includes 2 the second SDIO controllers, the mounting of one of them second SDIO controller
EMMC, the storage for MPSOC program；Another second SDIO controller mounts SD card 7, uses for debugging.
2nd PL module can example dissolve the DDR4 controllers of 80 bits, provide the memory headroom of 2.5GB, and can be 5 external
The DDR4 memory of 16 bits.2nd PL module reserves MIPI interface and the parallel interface of 72 bits is connected to MPSOC master unit 1
First PL module, the parallel interface include multiple GPIO, realize the data between MPSOC subelement 2 and MPSOC master unit 1
Interaction.
Further, the MPSOC master unit 1 and MPSOC subelement 2 further include clock unit, the clock unit
Including System Clock Reference, memory reference clock and serdes reference clock.
The reference clock that MPSOC processor needs when working includes System Clock Reference (33.33333MHz), memory reference
Clock (100MHz) and SerDes reference clock (100MHz) etc. are provided by external LVDS difference crystal oscillator.
Further, the serdes chip is also connected with FAKRA connector 13, and passes through FAKRA connector 13 and take the photograph
As head connection, as shown in Figure 4.
FAKRA connector 13 is vehicle-mounted common connector, and for connecting external camera, the camera includes LVDS
High-definition camera.Camera vision data unstrings by serdes chip, passes through MIPI interface and DVP interface and the main list of MPSOC
First PL module of member 1 is connected.
Further, the first PL module is also connected with HDMI transmitter, and the HDMI transmitter connects filter, institute
State filter by HDMI attachment base connection display equipment, as shown in Figure 5.
The data to be shown of MPSOC master unit 2 issue HDMI transmitter, HDMI hair by the parallel interface of the first PL module
LVDS signal of the device through parallel interface data conversion at difference is sent, HDMI connector 14 is sent to using filter, finally leads to
It crosses HDMI connector 14 and is sent to the display equipment connecting with HDMI connector 14, by showing that equipment is shown.
Further, the MPSOC master unit 1 and the MPSOC subelement 2 are also connected with USB2.0 connector, pass through
USB2.0 connector reserves outbound data transmission storage and debugging.
It should be noted that the technical solution of each embodiment of the utility model can be combined with each other, but must be
Based on can be realized by those skilled in the art, when there is conflicting or cannot achieve when in the combination of technical solution should
People thinks that the combination of this technical solution is not present, also not within the protection scope of the requires of the utility model.
The above is only the preferred embodiment of the present invention, and therefore it does not limit the scope of the patent of the utility model,
Equivalent structure transformation made by using the description of the utility model and the drawings is applied directly or indirectly in other phases
The technical field of pass, is also included in the patent protection scope of the utility model.
Claims (10)
1. a kind of automatic Pilot computing system, which is characterized in that including MPSOC master unit, MPSOC subelement and crosspoint,
The MPSOC master unit is connect with MPSOC subelement, crosspoint respectively；
MPSOC master unit receives laser radar data and vision data, and handles first laser radar data and First look number
According to, wherein the laser radar data includes first laser radar data and second laser radar data, the vision data
Including First look data and the second vision data；
MPSOC subelement receives and processes the second laser radar data and the second vision data of MPSOC master unit transmission, and will
Processing result sends back MPSOC master unit；
Crosspoint is equipped with Ethernet expansion interface.
2. automatic Pilot computing system as described in claim 1, which is characterized in that it further include power supply unit, the power supply list
First to connect with the MPSOC subelement, the power supply unit is connect by MPSOC subelement with the MPSOC master unit, is passed through
The MPSOC subelement and the MPSOC master unit are connect with the crosspoint.
3. automatic Pilot computing system as claimed in claim 2, which is characterized in that the MPSOC master unit is total by GPIO
Line expander and MIPI interface are connect with the MPSOC subelement.
4. automatic Pilot computing system as claimed in claim 3, which is characterized in that the MPSOC master unit is connect by RGMII
Mouth and SPI interface are connect with the crosspoint.
5. automatic Pilot computing system as claimed in claim 4, which is characterized in that the MPSOC master unit is also respectively connected with
Camera and laser radar.
6. the automatic Pilot computing system as described in any one of claim 1 to 5, which is characterized in that MPSOC master unit packet
The first MOSOC processor and serdes chip are included, the first MOSOC processor includes the first PS module and the first PL module,
The first PS module, the first PL module are connect with serdes chip respectively；
The first PS module includes with the first ethernet controller, CAN controller, 2 I2C controllers, 2 the first SDIO controls
Device, the first PCIE controller and the first DDR controller processed；
First ethernet controller is connect by RGMII interface and SPI interface with crosspoint, the first ether network control
Device processed is also connected with the first ethernet PHY chip, and the first ethernet PHY chip connects the first network interface；The CAN controller connection
CAN transceiver, the CAN transceiver are connect with vehicle CAN bus；One of them described I2C controller connects serdes chip,
Another I2C controller is separately connected power sensor, temperature sensor；One first SDIO controller connects SD card,
Another described first SDIO controller connects EMMC memory；
The first PL module includes the second DDR controller, the external first DDR memory of the second DDR controller；
The serdes chip is connect with camera, and the first PL module passes through MIPI interface and DVP interface and serdes core
Piece connection, the first PL module are connect by parallel interface and MIPI interface with MPSOC subelement, and the parallel interface includes
Multiple GPIO.
7. automatic Pilot computing system as claimed in claim 6, which is characterized in that the MPSOC subelement includes second
MOSOC processor, the 2nd MOSOC processor include the 2nd PS module and the 2nd PL module；
The 2nd PS module include with the second too net controller, 2 the second SDIO controllers, the 2nd PCIE controllers, and
Third DDR controller；Second ethernet controller connects the second ethernet PHY chip, the second ethernet PHY chip connection second
Network interface, second SDIO controller connect SD card, another described second SDIO controller connects EMMC memory；
The 2nd PL module includes the 4th DDR controller, the external 2nd DDR memory of the 4th DDR controller；Described second
PL module is connect by parallel interface and MIPI interface with MPSOC master unit, and the parallel interface includes multiple GPIO.
8. automatic Pilot computing system as claimed in claim 7, which is characterized in that the MPSOC master unit and MPSOC are single
Member further includes clock unit, and the clock unit includes System Clock Reference, memory reference clock and serdes reference clock.
9. automatic Pilot computing system as claimed in claim 8, which is characterized in that the serdes chip is also connected with
FAKRA connector, and connect by FAKRA connector with camera.
10. automatic Pilot computing system as claimed in claim 9, which is characterized in that the first PL module is also connected with
HDMI transmitter, the HDMI transmitter connect filter, and the filter passes through HDMI attachment base connection display equipment.
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| CN201821926132.7U CN208888626U (en) | 2018-11-21 | 2018-11-21 | A kind of automatic Pilot computing system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110647484A (en) * | 2019-08-23 | 2020-01-03 | 东软集团股份有限公司 | Vehicle-mounted system |
| CN111078475A (en) * | 2019-12-31 | 2020-04-28 | 上海汽车集团股份有限公司 | Visual image data processing system and method and automatic driving automobile |
| CN112019808A (en) * | 2020-08-07 | 2020-12-01 | 华东师范大学 | Vehicle-mounted real-time video information intelligent recognition device based on MPSoC |
-
2018
- 2018-11-21 CN CN201821926132.7U patent/CN208888626U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110647484A (en) * | 2019-08-23 | 2020-01-03 | 东软集团股份有限公司 | Vehicle-mounted system |
| CN111078475A (en) * | 2019-12-31 | 2020-04-28 | 上海汽车集团股份有限公司 | Visual image data processing system and method and automatic driving automobile |
| CN111078475B (en) * | 2019-12-31 | 2024-01-19 | 上海汽车集团股份有限公司 | Visual image data processing system and method and automatic driving automobile |
| CN112019808A (en) * | 2020-08-07 | 2020-12-01 | 华东师范大学 | Vehicle-mounted real-time video information intelligent recognition device based on MPSoC |
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