CN208848928U - Packaging structure of sound surface filtering chip - Google Patents
Packaging structure of sound surface filtering chip Download PDFInfo
- Publication number
- CN208848928U CN208848928U CN201821842565.4U CN201821842565U CN208848928U CN 208848928 U CN208848928 U CN 208848928U CN 201821842565 U CN201821842565 U CN 201821842565U CN 208848928 U CN208848928 U CN 208848928U
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- chip
- wiring
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001914 filtration Methods 0.000 title claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 96
- 229910052751 metal Inorganic materials 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000012528 membrane Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 8
- 238000005538 encapsulation Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000010897 surface acoustic wave method Methods 0.000 abstract description 5
- 238000012536 packaging technology Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000005022 packaging material Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 68
- 238000003466 welding Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
The utility model discloses a packaging structure of sound surface filtering chip belongs to semiconductor chip packaging technology field. The metal columns (40) are distributed in the encapsulating material layer (30) according to a pre-designed scheme; a plurality of rewiring layers are arranged on the upper surface of the packaging material layer (30), and are connected with the metal posts (40), and a plurality of metal connecting blocks (12) are arranged on the upper surface of the rewiring layers; the surface acoustic wave filter chip (10) is fixedly connected with a plurality of rewiring layers in a multi-point flip manner through metal connecting blocks (12), and the plurality of rewiring layers are connected with metal columns (40) to conduct electric signals of the surface acoustic wave filter chip (10) downwards; the encapsulating film forms a cavity (14) above the multilayer rewiring layer and below the surface acoustic wave filter chip (10), and the chip functional area (11) is placed in the cavity (14). The utility model discloses need not adopt ceramic substrate encapsulation sound surface filtering chip, improved surface acoustic wave filter's yield.
Description
Technical field
The utility model relates to a kind of encapsulating structures of sound surface filtering chip, belong to semiconductor chip packaging technology neck
Domain.
Background technique
SAW filter is the important component of communication terminal product, raw material be using piezo-electric crystal production and
At.With the miniaturization of mobile terminal, cost effective, the encapsulation of SAW filter is required also to be correspondingly improved.Together
When because of SAW filter properties of product and design function demand, it is any to need to guarantee that filtering chip functional area cannot contact
The design of substance, i.e. cavity structure.Demand and cavity surface based on SAW filter to encapsulating structure cavity structure
The requirement of flatness and cleanliness, traditional SAW filter mostly use greatly ceramic substrate encapsulation to combine hot pressing ultrasonic welding
Mode be packaged.As shown in Figure 1, being equipped with gold plated pads 3 on ceramic substrate 2, it is equipped with tin paste layer 4 on pad 3, is welding
Ceramic substrate 2 around disk 3 is equipped with insulating layer 5；It is implanted with gold goal 6 in the welding surface of chip 1, chip 1 passes through gold goal 6 and tin cream
The mode of layer 4 phases welding is fastened together with ceramic substrate 2.Existing this kind of SAW filter encapsulating structure exists
Following defect: one, ceramic substrate must use the hot pressing ultrasonic welding of gold goal, cause material and process costs high；Two,
Ceramic substrate thickness itself and weight are all larger, so that encapsulating structure volume is big, complex process cost performance is low, and mobile whole
End demand it is thin, small, gently run in the opposite direction；Three, accuracy, angle of influence, welding of signal conductor etc. of device installation this
The uncertainty of series just causes the inconsistency of device performance, or even damages to SAW filter.
Summary of the invention
The purpose of the utility model is to overcome the deficiencies in the prior art, provide one kind and are not required to using ceramic substrate
The encapsulating structure of the sound surface filtering chip of encapsulation, to improve the yield rate of SAW filter.
Purpose of the utility model is realized as follows:
A kind of encapsulating structure of sound surface filtering chip of the utility model comprising front is equipped with the sound table in chip functions area
Surface wave filter chip further includes metal link block, multilayer wiring layer, metal column and the encapsulating bed of material again, the metal connection
The periphery in the chip functions area is arranged in block, and the metal column has several, is distributed in encapsulating material by the scheme being pre-designed
In layer；
Wiring layer includes at least one layer of dielectric layer and at least one layer of wiring metal graph layer again to the multilayer again, is mutually handed over
Mistake setting, the dielectric layer wrap up wiring metal graph layer again and/or are filled between the adjacent graph layer of wiring metal again, institute
Stating again wiring metal graph layer, presence is selectively electrically connected with each other, and is opened up multilayer at lowest level dielectric layer and be routed again
Layer opening, the multilayer again wiring layer the undermost graph layer of wiring metal again by multilayer again wiring layer opening and metal column
It is connected；
The cloth again that the SAW filter chip passes through metal link block and the multilayer top layer of wiring layer again
Line metal pattern layer upside-down mounting is connected, and wiring layer and metal column are connected the electric signal of SAW filter chip the multilayer again
Conduction downwards；
Using the encapsulated membranes of membrane-like, laminated technique, by the SAW filter chip and multilayer wiring layer again
Exposed surface encapsulating, meanwhile, multilayer again the top of wiring layer, SAW filter chip lower section formed cavity, it is described
Chip functions area is placed in cavity.
The thickness range of metal link block described in the utility model is 6 ~ 12 microns.
The material of metal link block described in the utility model is the one or more of copper, gold, silver, and top is equipped with solder
Layer.
The thickness of metal column described in the utility model is equal with the encapsulating thickness of the bed of material and flushes.
One-to-one metal layer is set below metal column described in the utility model, under metal column upper surface and metal layer
Surface is flushed with the lower surface of the upper surface of the encapsulating bed of material and the encapsulating bed of material respectively, and the metal layer is the defeated of entire encapsulating structure
Enter/output pin.
Therefore, in the encapsulation for coping with next-generation SAW filter, the utility model offer sound surface filtering chip
Encapsulating structure be considered as most possibly solving the problems, such as the means of current encapsulation.
Beneficial effect
The ingenious concept using wafer-level packaging of the utility model and again wiring metal technique, by way of reconstructing wafer
Realize the encapsulation of SAW filter, cavity needed for SAW filter is formed in the way of face-down bonding, is dropped
Low technology difficulty, and make cavity thickness less than 22 microns, the integral thickness of packaging body is thus greatly reduced, is thereby reduced
Overall weight, realizes the encapsulating structure of SAW filter small in size, at low cost, and improves package reliability, is
The important solutions of next-generation SAW filter encapsulation.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of the encapsulating structure of traditional sound surface filtering chip；
Fig. 2 and Fig. 3 is a kind of two diagrammatic cross-sections of the embodiment of the encapsulating structure of sound surface filtering chip of the present invention；
Fig. 4, Fig. 5 are that the chip functions area of sound surface filtering chip and the position of metal block are closed in the embodiment of Fig. 2 and Fig. 3
It is schematic diagram；
In figure:
SAW filter chip 10
Chip functions area 11
Metal link block 12
Cavity 14
Encapsulated membranes 16
Wiring metal graph layer 20 again
Dielectric layer 23
Dielectric layer opening 231
Encapsulate the bed of material 30
Encapsulate bed of material upper surface 31
Encapsulate bed of material lower surface 33
Metal column 40
Metal column upper surface 41
Metal column lower surface 43
Carrier disk 50
Adhesive layer 53
Metal layer 70.
Specific embodiment
Specific embodiment of the present utility model is described in detail with reference to the accompanying drawing.It for ease of explanation, can be with
Use space relative terms (" in ... lower section ", " under ", " lower part ", " in ... top ", " top " etc.) to describe in figure
The relationship of a shown element or component and another element or component.In addition to orientation shown in figure, spatially relative term
Further include using or operation in equipment be differently directed.Device, which can be oriented otherwise, (to be rotated by 90 ° or fixed in other
To), therefore the opposite description in space used herein can carry out similar explanation.
Embodiment
A kind of encapsulating structure of sound surface filtering chip of the utility model, as shown in Fig. 2, Fig. 3, Fig. 4 and Fig. 5, wherein figure
2 and Fig. 3 is two diagrammatic cross-sections of the utility model embodiment；Fig. 4, Fig. 5 are sound surface filter in the embodiment of Fig. 2 and Fig. 3
The chip functions area 11 of wave chip and the positional diagram of metal link block 12.SAW filter chip 10 is sound table
Face filter chip, thickness range are 200-250 microns, and front is equipped with chip functions area 11.SAW filter core
The periphery setting metal link block 12 in the chip functions area 11 of piece 10, metal link block 12 at least two surround chip functions area
11 settings, as shown in Figure 4, Figure 5.Metal link block 12 mainly plays support SAW filter chip 10, can be with
The short side in chip functions area 13 is set, the long side in chip functions area 13 also can be set, or set according to actual needs
It sets.By metal link block 12 and multilayer, wiring layer upside-down mounting is connected SAW filter chip 10 again, and wiring layer is again again for multilayer
By multilayer, Open Side Down connect with metal column 40 and conduct the electric signal of SAW filter chip 10 downwards for wiring layer again.
Specifically, a kind of encapsulating structure of sound surface filtering chip of the utility model from top to bottom includes that surface acoustic wave is filtered
Wave device chip 10, multilayer wiring layer, metal link block 12 and metal column 40 again.In Fig. 2, several metal columns 40 are by being pre-designed
Scheme be distributed in the encapsulating bed of material 30, metal column runs through the encapsulating bed of material 30, metal column upper surface 41 and metal column following table up and down
Face 43 is flushed with encapsulating bed of material upper surface 31 and encapsulating bed of material lower surface 33 respectively, and metal column lower surface 43 is entire encapsulating structure
Input/output terminal II.Generally, the thickness range of metal column 40 is 30 ~ 50 microns, encapsulates the thickness and metal column of the bed of material 30
40 thickness is equal.
In Fig. 3, several metal columns 40 are distributed in the encapsulating bed of material 30 by the scheme being pre-designed, and are set below metal column 40
Set one-to-one metal layer 70, the lower surface of metal column upper surface and metal layer 70 respectively with the upper surface of the encapsulating bed of material and packet
The lower surface of the envelope bed of material flushes, and metal layer 70 is the input/output pin of entire encapsulating structure.Generally, the thickness of metal column 40
Spending range is 30 ~ 50 microns.
The upper surface setting multilayer of the encapsulating bed of material 30 wiring layer and under opening up downward multilayer wiring layer opening being with it again again
Metal column 40 connect, wiring layer includes at least one layer of dielectric layer and at least one layer of wiring metal graph layer again to multilayer again.Dielectric
Layer and again wiring metal graph layer are staggered, and can form two layers or two layers or more of multilayer wiring metal graph layer again, then
Wiring metal graph layer exists each other to be selectively electrically connected with, to enhance the input/output function of entire encapsulating structure.Again
The material of wiring metal graph layer includes but is not limited to copper, nickel, tin, silver.Dielectric material package again wiring metal graph layer and/or
It is filled between the adjacent graph layer of wiring metal again and forms dielectric layer, play insulating effect.In diagram 2 and diagram 3, packet is only shown
Seal one layer of 30 upper surface of the bed of material wiring metal graph layer 20 and one dielectric layer 23 and dielectric layer opening 231 again.It is routed again
Metal pattern layer 20 is connect by dielectric layer opening 231 with metal column upper surface 41, and in the upper of wiring metal graph layer 20 again
Surface forms several input/output terminals I 21, and metal link block 12, metal link block 12 are arranged in input/output terminal I 21
Thickness range be 6 ~ 12 microns.Metal link block 12 is pre-designed in the chip functions area of SAW filter chip 10
11 periphery, material include but is not limited to copper, gold, silver, generally, circular in cross-section or rectangle, or with sound surface
The bond pad shapes of wave filter chip 10 are consistent.
Using the encapsulated membranes 16 of membrane-like, laminated technique, by SAW filter chip 10 and multilayer wiring layer again
Exposed surface encapsulating, meanwhile, multilayer again the top of wiring layer, SAW filter chip 10 lower section formed cavity 14,
The chip functions area 11 is placed in cavity 14.In order to guarantee the realization of cavity 14, identical temperature and humidity conditions (such as: temperature
80 DEG C, humidity 20%) and mechanical compression in the case where, obtain following data by many experiments:
| H(microns of the height of cavity) | Encapsulated membranes get into the probability of SAW filter beneath chips | Assessment |
| 3-8 | 30%-40% | Cavity height is too small, because of capillary effect, leads to the chip functions region of encapsulated membranes colloid Yi Yizhi cavity |
| 8-15 | 3%-12% | Void space is enough, and metal coupling easily shapes, and cavity surface flatness is good, and it is good that cavity shapes consistency |
| 15-22 | 10%-20% | Void space is enough, and metal coupling easily shapes, and cavity surface flatness is good, and it is slightly worse that cavity shapes consistency |
| 22-30 | 40%-60% | The chip functions region of mechanical presses encapsulated membranes colloid Yi Yizhi cavity |
| 30 or more | 100% | It is meaningless |
According to the above experimental data, in conjunction with the thickness of solder thickness and the multilayer graph layer of wiring metal again of wiring layer again,
It is preferred with the thickness range of metal link block 12 at 6 ~ 12 microns, the height h of cavity 14 is not more than 22 microns at this time, encapsulated membranes quilt
The probability for getting into SAW filter beneath chips is no more than 20%, formability, cavity surface flatness and the forming one of cavity
Cause property can receive, and the chip functions area 13 of SAW filter chip 10 is made to reach design requirement.
Above-described specific embodiment, to the purpose of this utility model, technical scheme and beneficial effects carried out into
It is described in detail to one step, it should be understood that being not used to the foregoing is merely specific embodiment of the present utility model
Limit the protection scope of the utility model.Within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (5)
1. a kind of encapsulating structure of sound surface filtering chip comprising SAW filter chip (10), front are equipped with core
Piece functional areas (11),
It is characterized in that, it further includes metal link block (12), multilayer wiring layer, metal column (40) and the encapsulating bed of material (30) again,
The metal link block (12) is arranged in the periphery of the chip functions area (11), and the metal column (40) has several, by pre-
The scheme first designed is distributed in the encapsulating bed of material (30)；
Wiring layer includes at least one layer of dielectric layer and at least one layer wiring metal graph layer again to the multilayer again, interlaced to set
Set, the dielectric layer package wiring metal graph layer and/or is filled between the adjacent graph layer of wiring metal again again, it is described again
Wiring metal graph layer exists each other to be selectively electrically connected with, and at lowest level dielectric layer opens up multilayer wiring layer is opened again
Mouthful, the multilayer again wiring layer the undermost graph layer of wiring metal again by multilayer again wiring layer opening with metal column (40)
It is connected；
The SAW filter chip (10) passes through metal link block (12) and the multilayer top layer of wiring layer again
The upside-down mounting of wiring metal graph layer is connected again, and wiring layer and metal column (40) are connected SAW filter chip the multilayer again
(10) electric signal conducts downwards；
Using the encapsulated membranes (16) of membrane-like, laminated technique, by the SAW filter chip (10) and multilayer cloth again
The exposed surface of line layer is encapsulated, meanwhile, multilayer again the top of wiring layer, SAW filter chip (10) lower section form sky
Chamber (14), the chip functions area (11) are placed in cavity (14).
2. the encapsulating structure of sound surface filtering chip according to claim 1, which is characterized in that the metal link block
(12) thickness range is 6 ~ 12 microns.
3. the encapsulating structure of sound surface filtering chip according to claim 2, which is characterized in that the metal link block
(12) material is the one or more of copper, gold, silver, and top is equipped with solder layer.
4. the encapsulating structure of sound surface filtering chip according to claim 1, which is characterized in that the metal column (40)
Thickness is equal with the encapsulating thickness of the bed of material (30) and flushes.
5. the encapsulating structure of sound surface filtering chip according to claim 1, which is characterized in that under the metal column (40)
The lower surface of the one-to-one metal layer (70) of side's setting, metal column upper surface and metal layer (70) is upper with the encapsulating bed of material respectively
Surface and the lower surface of the encapsulating bed of material flush, and the metal layer (70) is the input/output pin of entire encapsulating structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821842565.4U CN208848928U (en) | 2018-11-09 | 2018-11-09 | Packaging structure of sound surface filtering chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821842565.4U CN208848928U (en) | 2018-11-09 | 2018-11-09 | Packaging structure of sound surface filtering chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208848928U true CN208848928U (en) | 2019-05-10 |
Family
ID=66376821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821842565.4U Active CN208848928U (en) | 2018-11-09 | 2018-11-09 | Packaging structure of sound surface filtering chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208848928U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244230A (en) * | 2018-11-09 | 2019-01-18 | 江阴长电先进封装有限公司 | Packaging structure and packaging method of sound surface filtering chip |
| WO2021023306A1 (en) * | 2019-08-08 | 2021-02-11 | 厦门云天半导体科技有限公司 | Three-dimensional packaging structure and method for bonding wall fan-out device |
-
2018
- 2018-11-09 CN CN201821842565.4U patent/CN208848928U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244230A (en) * | 2018-11-09 | 2019-01-18 | 江阴长电先进封装有限公司 | Packaging structure and packaging method of sound surface filtering chip |
| CN109244230B (en) * | 2018-11-09 | 2024-03-26 | 江阴长电先进封装有限公司 | Packaging structure and packaging method of acoustic surface filter chip |
| WO2021023306A1 (en) * | 2019-08-08 | 2021-02-11 | 厦门云天半导体科技有限公司 | Three-dimensional packaging structure and method for bonding wall fan-out device |
| US12014965B2 (en) | 2019-08-08 | 2024-06-18 | Xiamen Sky Semiconductor Technology Co. Ltd. | Three-dimensional packaging structure and method for fan-out of bonding wall of device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7973310B2 (en) | Semiconductor package structure and method for manufacturing the same | |
| US7691681B2 (en) | Chip scale package having flip chip interconnect on die paddle | |
| KR100604821B1 (en) | Stack type Ball grid array package and method for manufacturing the same | |
| WO2007026392A1 (en) | Semiconductor device and method for manufacturing same | |
| TWI541966B (en) | Package stacking structure and manufacturing method thereof | |
| US20200058610A1 (en) | Semiconductor device and method of manufacturing the same | |
| JP4896010B2 (en) | Multilayer semiconductor device and manufacturing method thereof | |
| CN208848928U (en) | Packaging structure of sound surface filtering chip | |
| CN109244230A (en) | Packaging structure and packaging method of sound surface filtering chip | |
| CN109411597A (en) | Packaging structure and packaging method of sound surface filtering chip | |
| CN114629463A (en) | Fan-out type filter chip packaging structure of integrated inductor and manufacturing method thereof | |
| CN209000954U (en) | Packaging structure of sound surface filtering chip | |
| CN209000955U (en) | Packaging structure of sound surface filtering chip | |
| TWI311806B (en) | Cob type ic package for improving bonding of bumps embedded in substrate and method for fabricating the same | |
| CN208848929U (en) | Packaging structure of sound surface filtering chip | |
| JP2003318360A (en) | Semiconductor device and method of manufacturing the same | |
| CN105990298A (en) | Chip packaging structure and preparation method thereof | |
| TWI387068B (en) | Cavity chip package structure and package-on-package using the same | |
| CN209497436U (en) | A kind of stack encapsulation structure of filter | |
| TW202139396A (en) | Dual-die semiconductor package and manufacturing method thereof | |
| TWI435434B (en) | Semiconductor packaging method to save interposer and bottom chip utilized for the same | |
| KR100394775B1 (en) | wire bonding method and semiconductor package using it | |
| CN101447443B (en) | Method for manufacturing high-frequency integrated circuit encapsulation structure | |
| JP2001291821A (en) | Semiconductor device and its manufacturing method | |
| CN202178252U (en) | Multi-loop arranged carrier-free double-IC chip packaging part |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |