CN208848906U - Integrating device, display device and electronic equipment with film transistor device - Google Patents
Integrating device, display device and electronic equipment with film transistor device Download PDFInfo
- Publication number
- CN208848906U CN208848906U CN201821680859.1U CN201821680859U CN208848906U CN 208848906 U CN208848906 U CN 208848906U CN 201821680859 U CN201821680859 U CN 201821680859U CN 208848906 U CN208848906 U CN 208848906U
- Authority
- CN
- China
- Prior art keywords
- integrating device
- chip
- film transistor
- connecting line
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Provide a kind of integrating device with film transistor device, display device and electronic equipment.The integrating device includes: substrate, chip and film transistor device；The top of the substrate is arranged in the film transistor device；Wherein, the upper surface of the substrate has been downwardly extending groove-like structure, and at least one connecting line is provided in the groove-like structure, and the chip is arranged in the groove-like structure, and is connect by least one connecting line with the film transistor device.Integrating device provided by the embodiments of the present application, thin film transistor (TFT) (TFT) is formed by substrate and film transistor device, and further, so that the integrated chip for controlling TFT is in the substrate of TFT, not only avoid effective work area that chip occupies TFT, the external connection terminals of integrating device can also be greatly reduced simultaneously, and then be effectively simplified the overall structure of integrating device.
Description
Technical field
The invention relates to electronic fields, and more particularly, to the integrated dress with film transistor device
It sets, display device and electronic equipment.
Background technique
It, can be with currently, since thin film transistor (TFT) (Thin film transistor, TFT) to be produced in liquid crystal display panel
Reduce the stability interfered with each other and promote picture between each pixel.Further, using non-silicon-based bottom, (such as substrate of glass has
Machine polymer-based end etc.) TFT technology can fundamentally solve the cost problem of large-scale semiconductive integrated circuit.This
Outside, since TFT technology also can be realized large area production, large-scale production and circuit devcie integration production (for example, can be with
Integrally formed drive circuit area and pixel region).Therefore, TFT technology is widely used in FPD and plane photoelectricity
The fields such as sensor.
But due to the limitation of TFT technique itself, so that the performances such as the line width of TFT, operating rate are all not as good as integrated electricity
Road.Therefore, external corresponding integrated circuit is needed in the work of the driving and signal-obtaining that carry out tft array
(Integrated Circuit, IC) chip.Usual tft array and IC chip pass through flexible circuit board (Flexible
Printed Circuit, FPC) it is attached, external discrete is then connected to by the electric connecting part of FPC and PCB etc. again
Device.For example, power supply unit etc..
Specifically, every row of tft array requires to be attached with IC chip with each column, if share 200*200 picture
Plain unit (general display device is far longer than this numerical value), at least 400 terminals will be attached with IC chip, therefore, TFT
Connection of the array between IC chip can occupy excessive space, while need a large amount of FPC as connection medium, reduce whole
The effective area for showing or detecting in a system structure, so that the internal structure of liquid crystal display panel is too fat to move many and diverse.
Therefore, how the connection of simplification, miniaturization tft array between IC chip is that this field is currently badly in need of solving
The technical issues of.
Utility model content
A kind of integrating device and preparation method thereof with film transistor device is provided, it being capable of simplification, miniaturization
Connection of the tft array between IC chip.
In a first aspect, providing a kind of integrating device including film transistor device, comprising:
Substrate, chip and film transistor device；
The top of the substrate is arranged in the film transistor device；
Wherein, the upper surface of the substrate has been downwardly extending groove-like structure, is provided at least in the groove-like structure
One connecting line, the chip are arranged in the groove-like structure, and brilliant by least one connecting line and the film
The connection of body tube device.
In some possible implementations, the film transistor device at least covers the opening of the groove-like structure.
In some possible implementations, the thickness of the chip is less than or equal to the depth of the groove-like structure.
In some possible implementations, the depth of the groove-like structure is greater than 100 microns of um.
In some possible implementations, what the lower surface of the side of the groove-like structure and the groove-like structure was formed
Angle is greater than predetermined angle.
In some possible implementations, the material that at least one connecting line uses is any in following material
Kind:
Molybdenum-aluminium-molybdenum Mo-Al-Mo structural metallic material, titanium-aluminium-titanium Ti-Al-Ti structural metallic material, electro-conductive glass material
Material and metal material.
In some possible implementations, the chip is connected by conducting resinl at least one connecting line.
In some possible implementations, the chip is provided at least one pad.
In some possible implementations, at least one described pad is provided on the lower surface of the chip.
In some possible implementations, at least one described pad is provided on the upper surface of the chip.
In some possible implementations, at least one described pad and at least one connecting line are corresponded.
In some possible implementations, the chip includes data driving chip, and the data driving chip passes through
At least one connecting line is connected to the electrode layer in the film transistor device.
In some possible implementations, the chip includes scanning drive chip, and the scanning drive chip passes through
At least one connecting line is connected to the electrode layer in the film transistor device.
In some possible implementations, the integrating device further include:
Packing material in the groove-like structure, the packing material are used to the chip being fixed on the groove-like structure
It is interior.
In some possible implementations, the thermal expansion coefficient of the thermal expansion coefficient of the packing material and the substrate
Difference be less than or equal to preset threshold.
In some possible implementations, the material of the packing material and the substrate is same material.
In some possible implementations, the packing material is flowable before curing.
In some possible implementations, at least one connecting line is arranged in the substrate and the packing material
Between.
In some possible implementations, at least one connecting line be arranged in the packing material upper surface and
The upper surface of the groove-like structure.
In some possible implementations, the packing material completely fills the groove-like structure.
In some possible implementations, the packing material is partially filled with the groove-like structure.
In some possible implementations, the film transistor device includes:
Articulamentum, the articulamentum are connected to external devices and/or at least one connecting line.
In some possible implementations, the integrating device further include:
Photodiode, the photodiode are arranged in the top of the substrate, the photodiode with it is described thin
Electrode layer in film transistor device is connected.
In some possible implementations, the material that the substrate uses is glass material or polyimide material.
In some possible implementations, the integrating device further include:
At least one connecting pin, at least one described connecting pin with extraneous device for being electrically connected, at least one described company
Connect the top that the substrate is arranged in end.
A connecting pin and described at least one in some possible implementations, at least one described connecting pin
A connecting line in connecting line is connected.
Electrode in some possible implementations, at least one described connecting pin and the film transistor device
Layer is connected.
In some possible implementations, the connecting pin is pad or tin ball.
Second aspect provides a kind of display device, comprising:
Integrating device described in any mode in the cards in first aspect or first aspect.
The third aspect provides a kind of electronic equipment, comprising:
Display device described in second aspect.
Fourth aspect provides a kind of method for preparing integrating device, in some possible implementations, comprising:
Groove-like structure is formed in the upper surface of substrate；
At least one connecting line is set in the groove-like structure；
Chip is arranged in the groove-like structure；
Film transistor device is prepared above the substrate, the chip passes through at least one connecting line and institute
State film transistor device connection.
In some possible implementations, the upper surface in substrate forms groove-like structure, comprising:
The position of the groove-like structure is determined by photoetching process；
In the position of the groove-like structure, the groove-like structure is formed by etching technics.
In some possible implementations, the etching technics includes at least one of following technique:
Dry etch process, wet-etching technology and laser etching process.
In some possible implementations, the thickness of the chip is less than or equal to the depth of the groove-like structure.
In some possible implementations, the depth of the groove-like structure is greater than 100 microns of um.
In some possible implementations, what the lower surface of the side of the groove-like structure and the groove-like structure was formed
Angle is greater than predetermined angle.
It is described that at least one connecting line is set in the groove-like structure in some possible implementations, comprising:
By way of deposition or the mode of plating, layer where forming connecting line in the groove-like structure；
By photoetching process in the position for determining at least one connecting line where the connecting line on layer；
It is performed etching in the position where the connecting line in layer except at least one connecting line, forms described at least one
Connecting line.
In some possible implementations, the mode of the deposition includes: physical vapour deposition (PVD) PVD mode and chemical gas
Mutually deposition CVD mode.
In some possible implementations, the material that at least one connecting line uses is any in following material
Kind:
Molybdenum-aluminium-molybdenum Mo-Al-Mo structural metallic material, titanium-aluminium-titanium Ti-Al-Ti structural metallic material, electro-conductive glass material
Material and metal material.
In some possible implementations, the chip is connected by conducting resinl at least one connecting line.
In some possible implementations, the chip is provided at least one pad.
In some possible implementations, at least one described pad is provided on the lower surface of the chip.
In some possible implementations, at least one described pad is provided on the upper surface of the chip.
In some possible implementations, at least one described pad and at least one connecting line are corresponded.
In some possible implementations, the chip includes data driving chip, and the data driving chip passes through
At least one connecting line is connected to the electrode layer in the film transistor device.
In some possible implementations, the chip includes scanning drive chip, and the scanning drive chip passes through
At least one connecting line is connected to the electrode layer in the film transistor device.
In some possible implementations, it is described prepare film transistor device above the substrate before, institute
State method further include:
The groove-like structure is filled using filler, the packing material is used to the chip being fixed on the channel-shaped
In structure.
In some possible implementations, the thermal expansion coefficient of the thermal expansion coefficient of the packing material and the substrate
Difference be less than or equal to preset threshold.
In some possible implementations, the material of the packing material and the substrate is same material.
In some possible implementations, the packing material is flowable before curing.
In some possible implementations, at least one connecting line is arranged in the substrate and the packing material
Between.
In some possible implementations, at least one connecting line is arranged in the packing material and the channel-shaped
The upper surface of structure.
It is described that the groove-like structure is filled using filler in some possible implementations, comprising:
The groove-like structure is completely filled using the packing material.
It is described that the groove-like structure is filled using filler in some possible implementations, comprising:
The groove-like structure is partially filled with using packing material.
In some possible implementations, the method also includes:
Articulamentum is set in the film transistor device, the articulamentum be connected to external devices and/or it is described extremely
A few connecting line.
In some possible implementations, the method also includes:
In the top of substrate setting photodiode, the photodiode and the film transistor device
Electrode layer is connected.
In some possible implementations, the material that the substrate uses is glass material or polyimide material.
In some possible implementations, the method also includes:
At least one connecting pin is set in the top of the substrate, at least one described connecting pin is used for and extraneous device electricity
Connection.
A connecting pin and described at least one in some possible implementations, at least one described connecting pin
A connecting line in connecting line is connected.
Electrode in some possible implementations, at least one described connecting pin and the film transistor device
Layer is connected.
In some possible implementations, the connecting pin is pad or tin ball.
5th aspect, provides a kind of display device, the display device may include according to above-mentioned fourth aspect
Prepare integrating device method preparation integrating device.
6th aspect, provides a kind of electronic equipment, and the electronic equipment may include aobvious described in above-mentioned 5th aspect
Showing device.
Based on above technical scheme, integrating device provided by the embodiments of the present application and the method for preparing integrating device will be used
In the integrated chip for controlling film transistor device in the substrate of the film transistor device, chip occupancy is not only avoided
Effective work area of film transistor device, additionally it is possible to the external connection terminals of integrating device be greatly reduced, and then effectively
Simplify the overall structure of integrating device.
Detailed description of the invention
Fig. 1 is the exemplary side cross-sectional view of the integrating device including film transistor device of the embodiment of the present application.
Fig. 2 is the exemplary side cross-sectional view of the film transistor device of integrating device shown in FIG. 1.
Fig. 3 is the exemplary planar sectional view of the integrating device including film transistor device of the embodiment of the present application.
Fig. 4 is the exemplary process flow figure of the preparation method of the integrating device of the embodiment of the present application.
Fig. 5 is the exemplary sectional view of the substrate before the fluting of the embodiment of the present application.
Fig. 6 is the exemplary sectional view of the substrate after the fluting of the embodiment of the present application.
Fig. 7 is the example of the structure formed after at least one connecting line of setting in the groove-like structure of substrate shown in Fig. 6
Property sectional view.
Fig. 8 is the exemplary of the structure that will be formed after at least one connecting line binding in chip and structure shown in Fig. 7
Sectional view.
Fig. 9 is the exemplary sectional view of the structure formed after the groove-like structure in filling structure shown in Fig. 8.
Specific embodiment
The embodiment of the present application provides the preparation method of a kind of integrating device comprising TFT device and the integrating device, institute
Stating the integrating device comprising TFT device may include multiple TFT, when the multiple TFT is distributed in array, the TFT device
Also known as tft array, tft array device or photoelectric sensor.The integrating device energy comprising TFT device of the embodiment of the present application
Connection between enough simplifications, miniaturization TFT device and IC chip.
Integrating device in the embodiment of the present application can be applied to TFT flat display field and the plate sensing based on TFT
Device and other products and application based on TFT technique.For example, the integrating device can be applied to active matrix
The electro-optical display device or self luminous electro-optical display device of (active matrix).Such as.Liquid crystal display device and organic
Electroluminescent (Electroluminescence, EL) display device.
Optionally, in some embodiments of the present application, the integrating device can be used as optical bio feature sensor,
Such as optical fingerprint sensor, for realizing biological characteristic inductive operation.Specifically, finger is placed in the upper of display screen by user
Fang Shi, the integrating device is received reflected via finger after the optical signal that is formed, and convert electric signal for the optical signal,
The electric signal is able to reflect the finger print information of user's finger.
In fingerprint identification process, the region of the integrating device is the induction region of the integrating device.It is described
Induction region can be located at the lower section of the display area of display screen, and user is needing to be unlocked the terminal device as a result,
Or when other biological signature verification, it is only necessary to by finger pressing on being located at the display screen, be located at the induction zone
The integrating device in domain can be carried out fingerprint inductive operation.
Application the present embodiment is not specifically limited the light emitting source of the optical signal for carrying out fingerprint recognition.For example, described
Light emitting source can be the light of the sending of the light emitting pixel in display screen, be also possible to the light that the backlight below display screen issues, institute
Stating backlight can be the light of LED lamp sending, and the LED lamp may include: red-light LED wick, blue-ray LED wick, green
Light LED lamp, infrared LED wick, ultraviolet LED wick and white light LEDs wick.It should be understood that the embodiment of the present application is to LED lamp
With no restrictions, can arrange in pairs or groups the LED lamp type specifically included different types of LED lamp according to the specific application occasions.
It should be understood that the integrating device is merely illustrative as optical fingerprint sensor, and in other alternate embodiments, institute
It states integrating device also and can be applied to color file scanning, vein imaging can also be applied to, counterfeit money can also be applied to and identified.
The embodiment of the present application is not particularly limited the purposes of integrating device.
Below in conjunction with Fig. 1 to Fig. 9 is combined, the integrating device of the embodiment of the present application is discussed in detail and prepares integrating device
Method.
It should be noted that for purposes of illustration only, identical appended drawing reference indicates identical portion in embodiments herein
Part, and for sake of simplicity, in different embodiments, omit the detailed description to same parts.It should be understood that this Shen shown in attached drawing
Please the thickness of various parts in embodiment, the integral thickness of length and width equidimension and integrating device, length and width equidimension be only to show
Example property explanation constitutes any restriction without coping with the application.
Fig. 1 is the exemplary block diagram of the integrating device including film transistor device of the embodiment of the present application.
As shown in Figure 1, the integrating device may include:
Substrate 100, chip 103 and film transistor device 105.
The top of the substrate 100 is arranged in the film transistor device 105.
Wherein, the upper surface of the substrate 100 has been downwardly extending groove-like structure 101, sets in the groove-like structure 101
It is equipped at least one connecting line 102, the chip 103 is arranged in the groove-like structure 101, and connects by described at least one
Wiring 102 is connect with the film transistor device 105.
In the concrete realization, it can be carried out at fluting by the partial region of the upper surface of the substrate 100 to integrating device
Reason, to form groove-like structure 101 shown in FIG. 1.Further, metal electric appliance articulamentum is carried out in the groove-like structure 101
Arrangement (at least one connecting line 102 i.e. shown in FIG. 1).Then, chip 103 is mounted in the groove-like structure 101, and
It is electrically connected at least one connecting line 102.Finally, when preparing the film layer 105 in the substrate 100, by institute
The electrode layer for stating film transistor device 105 is connected at least one connecting line 102.It is achieved in 103 He of chip
Connection between the film transistor device 105.
Integrating device in the embodiment of the present application, the chip 103 that will be used to control thin film transistor (TFT) (TFT) device 105 collect
At the effective work area in the substrate 100 of TFT device 105, not only avoiding the occupancy TFT device 105 of chip 103, moreover it is possible to
The external connection terminals of integrating device are enough greatly reduced, and then are effectively simplified the overall structure of integrating device.
Optionally, in some embodiments of the present application, the material of the substrate 100 can be the mark that TFT technique is related to
Quasi- base material, such as glass material or polyimide material.It should be understood that specific material of the embodiment of the present application to substrate 100
Model is without limitation.For example, the material of the substrate 100 can be alkali-free glass when being glass material.Due to the alkali-free glass
The strain temperature of glass can be higher than 625 DEG C, therefore, the substrate 100 can be made to have good chemical stability.
Optionally, in some embodiments of the present application, integrating device shown in FIG. 1 is for carrying out fingerprint recognition and described
When light emitting source is backlight, the material of the substrate 100 can be translucent material, thereby guarantee that the luminous energy that the backlight issues
Display screen is enough transmitted to by the substrate 100.For example, the substrate 100 can be substrate of glass.But the application to this not
It is limited, in other embodiments, the material of the substrate 100 can also be other translucent materials such as light-passing plastic.
Optionally, in some embodiments of the present application, the chip 103 be can be by wiring layer again
Chip after (Redistribution Layer, RDL) processing and micro convex point process.
Optionally, in some embodiments of the present application, the chip 103 can be flip-chip (FlipChip).
Optionally, in some embodiments of the present application, the thickness of the chip 103 is less than or equal to the groove-like structure
101 depth, and then guarantee that the chip 103 fully-integrated can be arranged in the substrate 100.
Optionally, in some embodiments of the present application, the depth of the groove-like structure 101 is greater than 100 microns (um).It answers
Understand, the depth of the groove-like structure 101 is greater than 100 microns (um) and is merely illustrative description, and the embodiment of the present application is without being limited thereto.
For example, it is also possible to determine the depth of the groove-like structure 101 according to the application scenarios of integrating device.
Optionally, in some embodiments of the present application, the film transistor device 105 at least covers the channel-shaped knot
The opening of structure 101.
For example, the film transistor device 105 the upper surface of the substrate 100 maximum width planar it is big
In the groove-like structure 101 opening the upper surface of the substrate 100 maximum width planar.
In another example the film transistor device 105 is put down where the upper surface of the substrate 100 in a direction
Width in face be greater than the opening of the groove-like structure 101 the upper surface of the substrate 100 width planar.
Optionally, in some embodiments of the present application, the side of the groove-like structure 101 and the groove-like structure 101
Lower surface formed angle be greater than predetermined angle, thereby, it is possible to reduce the chip 103 being mounted on the groove-like structure
Operation difficulty when 101.
Optionally, in some embodiments of the present application, the material that at least one connecting line 102 uses is following material
Any one of material: molybdenum-aluminium-molybdenum (Mo-Al-Mo) structural metallic material, titanium-aluminium-titanium (Ti-Al-Ti) structural metallic material are led
Electric glass material and metal material.Wherein, electro-conductive glass can be the conductive glass of tin indium oxide (Indium Tin Oxide, ITO)
Glass.
It should be understood that the embodiment of the present application does not make spy to the quantity of at least one connecting line 102 and specific wire laying mode
Different limitation, as long as at least one connecting line 102 described above, which can satisfy, is connected to the thin film transistor (TFT) for the chip 103
The requirement of device 105.
It should be understood that in other embodiments, the substrate 100 is alternatively referred to as substrate 100 or substrate 100.
It should be understood that the film transistor device 105 in the embodiment of the present application can be prepare on the substrate 100 it is various not
Same film.For example, semiconductor active layer, dielectric layer and metal electrode layer.It should be understood that the embodiment of the present application is brilliant to the film
The manufacture craft of body tube device 105 is not specifically limited.For example, the manufacture craft of the film transistor device 105 can be
The manufacture craft of the prior art.
Fig. 2 is the exemplary sectional view of the film transistor device 105 of the embodiment of the present application.
As shown in Fig. 2, the film transistor device 105 can be the film transistor device with bottom grating structure.
The grid 106 of the film transistor device 105 can be connected with driving scanning chip, and the driving scans chip
It is connected with external power supply, for providing scanning voltage for integrating device.The drain electrode 109 of the film transistor device 105 can be with
It is connect with the internal components of the film transistor device 105, the source electrode 108 of the film transistor device can be with Fig. 1 institute
At least one connecting line 102 shown is connected, the drain electrode 109 of the film transistor device 105 and the film transistor device
There are channel regions 107 between 105 source electrode 108.
Optionally, in some embodiments of the present application, the material of the channel region 107 includes but is not limited to: amorphous silicon
(a-Si) material, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) and low temperature polycrystalline silicon (low
Temperature poly-silicon, LTPS).For example, the translucent materials such as tin indium oxide or zinc oxide.
Optionally, in some embodiments of the present application, as shown in Fig. 2, the film transistor device 105 can also wrap
It includes: dielectric layer 111.
The dielectric layer includes but is not limited to: the insulating dielectric layer such as oxide and nitride.
Optionally, as shown in Fig. 2, in some embodiments of the present application, the integrating device shown in FIG. 1 can also be wrapped
Include photodiode 110.
The photodiode 110 is the element in various photodetector systems for realizing photoelectric conversion, the photoelectricity
Diode 110 is specifically used for optical signal (for example, infrared signal, visible light signal and ultraviolet signal) being transformed into telecommunications
Number.Further, the electric signal of conversion can be sent to film transistor device 105 by the photodiode 110, finally by
The film transistor device 105 exports the electric signal.It should be understood that in other embodiments, the photodiode 110 is again
Referred to as optoelectronic induction unit or optical detector.
As shown in Fig. 2, the photodiode 110 can be set in the top of the substrate 100, the photodiode
110 are connected with the electrode layer in the film transistor device 105.For example, the photodiode 110 and the film crystal
The drain electrode 109 of electrode layer in tube device 105 is connected.
Optionally, in some embodiments of the present application, integrating device shown in FIG. 1 may include multiple as shown in Figure 2
Photodiode 110, multiple photodiodes 110 can in array be distributed.Wherein, each photodiode 110
It is connected with a drain electrode in the electrode layer of the film transistor device 105.
Optionally, in some embodiments of the present application, wave-length coverage, the technological ability of the light of detection be can according to need
Etc. parameters determine the photodiode 110 structure and specific material constitute.But the embodiment of the present application is without being limited thereto.
Optionally, in some embodiments of the present application, the photodiode 110 can be PIN type photodiode
Or PN type photodiode.
By taking the photodiode 110 is PIN type photodiode as an example, the photodiode 110 may include: certainly
N-type doping semiconductor layer, intrinsic semiconductor layer, p-type doping semiconductor layer on down.Wherein, n-type doping semiconductor layer conduct
The cathode of photodiode 110, light absorbing layer of the intrinsic semiconductor layer as photodiode 110, p-type doping semiconductor layer are made
For the anode of photodiode 110.
It should be understood that the PIN type photodiode can also claim PIN junction diode, PIN diode.
Optionally, as shown in Fig. 2, in some embodiments of the present application, the film transistor device 105 can also be wrapped
It includes:
Articulamentum 112, the articulamentum 112 are connected to external devices and/or at least one connecting line 102.This Shen
Please be in embodiment, the articulamentum 112 can not only realize the company between the 105 each layer in inside of film transistor device
It connects, additionally it is possible to realize the connection and the chip 103 and external devices of the film transistor device 105 and external devices
Connection, and then realize the electrical interconnecting function of integrating device.In other words, the chip 103 and the thin film transistor (TFT) device
Part 105 can realize the other elements with 103 corresponding device of other peripheral circuits or the chip by the articulamentum 112
Electrical interconnection and signal transmission.
The material of the articulamentum 112 can be metal, be also possible to the transparent conductive materials such as ITO.The embodiment of the present application
Particular determination is not done to the specific material of the articulamentum 112.
In the embodiment of the present application, can according between the 105 each layer in inside of the film transistor device connection requirement,
Connection requirement and the thin film transistor (TFT) device inside the film transistor device between each layer and the chip 103
The each layer in 105 inside of part and the connection requirement of external devices determine the number of plies of the articulamentum 112.But the embodiment of the present application is to institute
State the specific number of plies of articulamentum 112 without limitation.
In the embodiment of the present application, the articulamentum 112 can be drawn from the upper surface of substrate 100, it can also be from described thin
The random layer of film transistor device 105 draws the articulamentum 112.Optionally, if from the upper surface of film transistor device 105
The articulamentum 112 is drawn, the material of the articulamentum 112 can use transparent conductive material.Such as ITO.Thereby guarantee that light
Normal transmission.
Optionally, as depicted in figs. 1 and 2, at least one pad can be set on the chip 103.
Optionally, in some embodiments of the present application, the chip 103 is connect by conducting resinl with described at least one
Line 102 is connected.Wherein, the conducting resinl includes but is not limited to:
Anisotropic conductive film (Anisotropic Conductive Film, ACF) and anisotropic-electroconductive adhesive
(Anisotropic Conductive Adhesive, ACA).
It is retouched it should be understood that the chip 103 is connected to be merely illustrative by conducting resinl at least one connecting line 102
It states, the embodiment of the present application is without being limited thereto.For example, the chip 103 can also connect with described at least one by welding
Wiring 102 is connected.In another example the chip 103 can also be with Direct Bonding (Bonding) at least one connecting line 102
On.
Optionally, in some embodiments of the present application, be provided on the lower surface of the chip 103 it is described at least one
Pad.At least one described pad can equally or disproportionately be distributed in the lower surface of chip 103.For example, such as Fig. 2 institute
The pad 104 shown.The chip 103 can be connected by conducting resinl at least one described pad as a result,.
In the embodiment of the present application, it may be implemented to collect by least one described pad and at least one connecting line 102
At in the substrate 100 the chip 103 and extraneous device and film transistor device 105 be electrically connected, but this Shen
Please embodiment the concrete form of at least one pad is not construed as limiting.Such as at least one described pad can be for
The solder joint or tin ball or any type of of flexible print circuit (Flexible Printed Circuit, FPC) electrical connection
Connecting pin.
It should be noted that the chip 103 in the embodiment of the present application can be before entering this integrated process flow
Through being prepared with the chip of pad (Pad) in surface thereof, for example, pad 104 as shown in Figure 1, the pad 104 passes through described
At least one connecting line 102 is electrically connected to film transistor device 105.The pad 104 can be understood as chip 103 and the external world
The pin of connection.In the embodiment of the present application, the front surface that the lower surface of chip 103 as enters this integrated process flow has been made
The one side for having pad, the one side opposite with the lower surface of the chip 103 are the upper surface of chip 103.
It should be understood that the lower surface that pad 104 shown in FIG. 1 is located at chip 103 is merely illustrative, the embodiment of the present application is not limited to
This.For example, being provided at least one described pad on the upper surface of the chip 103.Further, under the chip 103
Surface can directly be contacted with the bottom surface of the groove-like structure 101.In another example can also be in the side table of the chip 103
At least one described pad is arranged in face.
Optionally, in some embodiments of the present application, at least one described pad and at least one connecting line 102
It corresponds.In other words, at least one connecting line according to the arrangement of at least one pad
102。
It should be understood that the embodiment of the present application is to placement position of the chip 103 in the groove-like structure 101 and puts
Form is not specifically limited.
For example, the chip 103 can be including along the upper surface of substrate 100 parallel direction and/or vertical direction row
Multiple chips of column.The multiple chips arranged along the parallel direction of the upper surface of substrate 100 and/or vertical direction can be sealed
In the groove-like structure 101.Optionally, signal can be realized by way of electrical connection between the multiple chip 103
Transmission.
Optionally, in some embodiments of the present application, the chip 103 includes data driving chip, and the data are driven
Dynamic chip can be connected to the electrode layer in the film transistor device 105 by least one connecting line 102.Example
Such as, the data driving chip can be connected to the source electrode in the electrode layer by least one connecting line 102.
Optionally, in some embodiments of the present application, the chip 103 includes scanning drive chip, and the scanning is driven
Dynamic chip can be connected to the electrode layer in the film transistor device 105 by least one connecting line 102.Example
Such as, the scanning drive chip can be connected to the grid in the electrode layer by least one connecting line 102.
Optionally, as shown in Figure 1, in some embodiments of the present application, the integrating device can also include:
Packing material in the groove-like structure 101, the packing material are used to the chip 103 being fixed on the slot
In shape structure 101.
Optionally, in some embodiments of the present application, thermal expansion coefficient (the Coefficient of of the packing material
Thermal expansion, CTE) with the difference of the thermal expansion coefficient of the substrate 100 it is less than or equal to preset threshold.
Optionally, in some embodiments of the present application, the material of the packing material and the substrate 100 can be same
A kind of material.
Optionally, in some embodiments of the present application, the packing material can be epoxy resin injected molded compound
(Epoxy Molding Compound, EMC) material.
Optionally, in some embodiments of the present application, the packing material is flowable before curing, thereby guarantees that described
After packing material is filled into the groove-like structure 101 and solidifies, the upper surface of the packing material in the groove-like structure 101
It is flat surface.
In the description of the present application, the orientation or positional relationship of the instructions such as term " on ", "lower" is based on the figure
Orientation or positional relationship is merely for convenience of description the application rather than requires the application that must be constructed and be grasped with specific orientation
Make, therefore should not be understood as the limitation to the application.
For example, in the embodiment shown in fig. 1, the lower surface of the chip 103 is entering this integrated process flow
It is prepared with pad before, the bottom for the groove-like structure 101 with substrate 100 is bonded.But the embodiment of the present application is without being limited thereto.Example
Such as, in other alternate embodiments, chip 103 shown in FIG. 1 can also prepare pad in the upper surface of the chip, by
This can be by the bottom of upper surface and the groove-like structure 101 when the chip 103 to be fixed in the groove-like structure 101
Portion's fitting.
Optionally, in some embodiments of the present application, at least one connecting line 102 is arranged in the substrate 100
Between the packing material.
Optionally, in some embodiments of the present application, at least one connecting line 102 is arranged in the packing material
Upper surface and the groove-like structure 101 upper surface.For example, the pad of the chip 103 is located at the upper table of the chip 103
When face and the upper surface of the filler are lower than the upper surface of the chip 103, at least one connecting line 102 can be
The upper surface of the packing material and the upper surface of the groove-like structure 101 are set after having filled the filler.
Optionally, in some embodiments of the present application, the packing material completely fills the groove-like structure 101.
Optionally, in some embodiments of the present application, the packing material is partially filled with the groove-like structure 101.
Fig. 3 is the plane sectional view of the integrating device of the embodiment of the present application.
Optionally, as shown in figure 3, in some embodiments of the present application, the integrating device further includes at least one company
End 113 is connect, for being electrically connected with extraneous device, at least one connecting pin 113 setting exists at least one described connecting pin 113
The top of the substrate 100, at least one described connecting pin 113 allow the integrating device and other peripheral circuits or
The electrical interconnection and signal transmission of the other elements of the integrating device corresponding device.
Optionally, a connecting pin 113 in some embodiments of the present application, at least one described connecting pin 113
It is connected with a connecting line 102 at least one connecting line 102.
Optionally, in some embodiments of the present application, at least one described connecting pin 113 and the thin film transistor (TFT) device
Electrode layer in part 105 is connected.
Optionally, in some embodiments of the present application, the connecting pin is pad or tin ball.
It should be understood that in the embodiment shown in fig. 3, the integrating device includes 6 chips 103 and each chip 103
It is connected to a connecting pin 113 by a connecting line 102, but the embodiment of the present application is without being limited thereto.
Optionally, the embodiment of the present application also provides a kind of display device, the display device may include above-mentioned collection
At device.For example, liquid crystal display device.
The liquid crystal display device may include liquid crystal display panel and for the liquid crystal display panel provide light source backlight mould
Group.The liquid crystal display panel may include integrating device described above (including multiple thin film transistor (TFT)s) and criss-cross
Scan line and data line, the grid of the TFT of scanning line traffic control a line of every a line, the one column TFT's of data line connection of each column
Source electrode, the drain electrode of each TFT connect a pixel electrode to form pixel capacitance, and pixel capacitance includes opposite pixel electrode
And public electrode, pixel electrode are connected to the drain electrode of TFT, public electrode may be coupled to a constant voltage signal.Pixel
Liquid crystal molecule is filled between electrode and public electrode, by adjusting data line output voltage can control pixel electrode and
Pressure difference between public electrode realizes the control of luminous flux so as to adjust the deflection angle of liquid crystal molecule.
Optionally, the embodiment of the present application also provides a kind of electronic equipment, the electronic equipment may include above-mentioned display
Device.For example, the electronic equipment can be the terminal devices such as TV, mobile phone, tablet computer or e-book.
Fig. 4 is the schematic flow diagram of the method for preparing integrating device of the embodiment of the present application.It should be understood that side shown in Fig. 4
Method 200 can be used for preparing Fig. 1 to integrating device shown in Fig. 3.Method 200 shown in Fig. 4 can also be according to Fig. 5 to Fig. 9, figure
1 sequence prepares Fig. 1 to integrating device shown in Fig. 3.Below with reference to Fig. 1, Fig. 4 to Fig. 9 to the preparation collection of the embodiment of the present application
It is illustrated at the method for device.
As shown in figure 4, the method 200 for preparing integrating device may include:
S210 forms groove-like structure in the upper surface of substrate.
Optionally, in some embodiments of the present application, the S210 can be specifically included:
The position of the groove-like structure is determined by photoetching process；In the position of the groove-like structure, pass through etching technics
Form the groove-like structure.
For example, Fig. 5 be the embodiment of the present application fluting before substrate exemplary sectional view.Fig. 6 is the embodiment of the present application
Fluting after substrate exemplary sectional view.For Fig. 5 and Fig. 6, in the embodiment of the present application, photoetching process can be passed through
The position that groove-like structure 101 as shown in FIG. 6 is determined on the 100 of substrate shown in Fig. 5, then in the groove-like structure
101 position forms the groove-like structure 101 by etching technics.
Optionally, in some embodiments of the present application, the etching technics include but is not limited in following technique extremely
Few one kind: dry etch process, wet-etching technology and laser etching process.
Optionally, in some embodiments of the present application, dry etching (dry etching) technique may include with
At least one of lower etching technics: it is used as etching gas (etching using by tetrafluoromethane (CF4) and sulfur hexafluoride (SF6)
Gas reactive ion etching (ion etching)), chemical drying method etching (chemical dry etching) and wait from
Daughter etches (plasma etching) etc..
Optionally, it in some embodiments of the present application, can also be can change by changing the mixing ratio of etching gas
Etching speed.
Optionally, in some embodiments of the present application, the chemical raw material of the wet-etching technology may include but not
It is limited to the etching liquid of hydrofluoric acid containing.
Optionally, in some embodiments of the present application, the lithographic method combined using dry etching with wet etching,
Or the method using laser ablation combination wet etching, it can effectively ensure that shape and bottom surface flatness of etching etc..
At least one connecting line is arranged in S220 in the groove-like structure.
Optionally, in some embodiments of the present application, the S220 can be specifically included:
By way of deposition or the mode of plating, layer where forming connecting line in the groove-like structure；Pass through photoetching
Technique is in the position for determining at least one connecting line where the connecting line on layer；Where the connecting line in layer except it is described extremely
The position of a few connecting line performs etching, and forms at least one connecting line.
For example, Fig. 7 is the structure formed after at least one connecting line of setting in the groove-like structure of substrate shown in Fig. 6
Exemplary sectional view.For Fig. 6 and Fig. 7, in the embodiment of the present application, can by way of deposition or the mode of plating,
Position in groove-like structure 101 shown in Fig. 6 where at least one connecting line 102 as shown in Figure 7 forms conductive layer；Pass through
Photoetching process determines the position of at least one connecting line 102 as shown in Figure 7 on the conductive layer；It etches on the conductive layer
Except at least one connecting line 102 part, to form at least one connecting line 102 shown in Fig. 7.
Optionally, in some embodiments of the present application, the thickness of the chip is less than or equal to the groove-like structure
Depth.
Optionally, in some embodiments of the present application, the depth of the groove-like structure is greater than 100 microns of um.
Optionally, in some embodiments of the present application, the following table of the side of the groove-like structure and the groove-like structure
The angle that face is formed is greater than predetermined angle.
Optionally, in some embodiments of the present application, the mode of the deposition may include:
Physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) mode and chemical vapor deposition
(Chemical Vapor Deposition, CVD) mode and the mode of plating.
Optionally, in some embodiments of the present application, the material that at least one connecting line uses is following material
Any one of:
Molybdenum-aluminium-molybdenum (Mo-Al-Mo) structural metallic material, titanium-aluminium-titanium (Ti-Al-Ti) structural metallic material, conductive glass
Glass material and metal material.
Chip is arranged in the groove-like structure S230.
Optionally, in some embodiments of the present application, the chip can be by tying up at least one connecting line
The mode of fixed (bonding), is fixed in the groove-like structure.
Optionally, in some embodiments of the present application, the chip passes through conducting resinl and at least one connecting line
It is connected.
Optionally, in some embodiments of the present application, the chip is provided at least one pad.
For example, Fig. 8 is the knot that will be formed after at least one connecting line 102 binding in chip 103 and structure shown in Fig. 7
The exemplary sectional view of structure.As shown in figure 8, at least one pad 104 being arranged on chip 103, at least one described pad 104
It can be connected with one end of the bottom close to the groove-like structure 101 at least one connecting line 102.
Optionally, in some embodiments of the present application, at least one described weldering is provided on the lower surface of the chip
Disk.
Optionally, in some embodiments of the present application, at least one described weldering is provided on the upper surface of the chip
Disk.
Optionally, in some embodiments of the present application, at least one described pad and at least one connecting line one
One is corresponding.
Optionally, in some embodiments of the present application, the chip includes data driving chip, the data-driven core
Piece is connected to the electrode layer in the film transistor device by least one connecting line.
Optionally, in some embodiments of the present application, the chip includes scanning drive chip, the turntable driving core
Piece is connected to the electrode layer in the film transistor device by least one connecting line.
It should be understood that the embodiment of the present application to placement position of the chip in the groove-like structure and disposing way not
It is specifically limited.
Film transistor device is arranged in the top of the substrate in S240, and the chip is connected by described at least one
Line is connect with the film transistor device.
For example, as shown in Figure 1, film transistor device 105, the chip can be arranged in the top of the substrate 100
103 are connected with one end of the bottom close to the groove-like structure 101 of at least one connecting line 102, and described at least one
The other end of connecting line 102 is connected with the film transistor device 105.
It should be understood that the embodiment of the present application is to the concrete technology that the film transistor device is arranged in the top of the substrate
Without limitation with the particular use of the film transistor device.
For example, including but is not limited in the concrete technology that the film transistor device is arranged in the top of the substrate: base
In the TFT technique of amorphous silicon (amorphous silicon, a-Si), based on low temperature polycrystalline silicon (Low Temperature
Poly-silicon, LTPS) technology TFT technique and based on indium gallium zinc (Indium Gallium Zinc oxide,
IGZO TFT technique).
In another example the purposes of the film transistor device can include but is not limited to: flat-panel display device, photoelectricity plate
Sensing device or temperature plate inductor part.
Optionally, in some embodiments of the present application, thin film transistor (TFT) device is arranged in the top in the substrate 100
Before part, the method 200 may also include that
The groove-like structure is filled using filler, the packing material is used to the chip being fixed on the channel-shaped
In structure.
For example, Fig. 9 is the exemplary sectional view of the structure formed after the groove-like structure 101 in filling structure shown in Fig. 8.
As shown in figure 9, first filling the channel-shaped using filler before film transistor device is arranged above the substrate 100
Structure 101, the packing material is for the chip 103 to be fixed in the groove-like structure 101, then in the channel-shaped knot
The top of filler and the substrate 101 in structure 101, is arranged the film transistor device.
Optionally, in some embodiments of the present application, the heat of the thermal expansion coefficient of the packing material and the substrate
The difference of the coefficient of expansion is less than or equal to preset threshold.
Optionally, in some embodiments of the present application, the material of the packing material and the substrate is same material
Material.
Optionally, in some embodiments of the present application, the packing material can be epoxy resin injected molded compound
(Epoxy Molding Compound, EMC) material.
Optionally, in some embodiments of the present application, the packing material is flowable before curing.
Optionally, in some embodiments of the present application, at least one connecting line setting is in the substrate and described
Between packing material.
Optionally, in some embodiments of the present application, at least one connecting line setting in the packing material and
The upper surface of the groove-like structure.
Optionally, in some embodiments of the present application, the groove-like structure is completely filled using the packing material.
Optionally, in some embodiments of the present application, the groove-like structure is partially filled with using packing material.
Optionally, in some embodiments of the present application, the method also includes:
Articulamentum is set in the film transistor device, the articulamentum be connected to external devices and/or it is described extremely
A few connecting line.
For example, as shown in Fig. 2, articulamentum 112, the articulamentum can be arranged in the film transistor device 105
112 are connected to external devices and/or at least one connecting line.
Optionally, in some embodiments of the present application, the method 200 may also include that
In the top of substrate setting photodiode, the photodiode and the film transistor device
Electrode layer is connected.
For example, as shown in Fig. 2, photodiode 110, the light can be arranged in the film transistor device 105
Electric diode 110 is connected with the electrode layer in the film transistor device 105.
Optionally, in some embodiments of the present application, the material that the substrate uses is glass material or polyimides
Material.
Optionally, in some embodiments of the present application, the method 200 may also include that
At least one connecting pin is set in the top of the substrate, at least one described connecting pin is used for and extraneous device electricity
Connection.
For example, as shown in figure 3, an at least connecting pin arranged in parallel can be arranged in the upper surface of the substrate 100
113。
Optionally, in some embodiments of the present application, a connecting pin at least one described connecting pin with it is described
A connecting line 102 at least one connecting line 102 is connected.
Optionally, in some embodiments of the present application, at least one described connecting pin and the film transistor device
Electrode layer in 105 is connected.
In some possible implementations, the connecting pin is pad or tin ball.
It should be understood that embodiment of the method can be corresponded to each other with the embodiment of integrating device, similar description is referred to collect
At the specific embodiment of device.For sake of simplicity, details are not described herein.
It should also be understood that each embodiment of the above-mentioned method 200 for preparing integrating device enumerated, can by robot or
Numerical control processing mode executes, and the device software or technique for executing the method 200 can be stored in storage by executing
Computer program code in device executes the above method 200.
It should be noted that under the premise of not conflicting, in each embodiment described herein and/or each embodiment
Technical characteristic can arbitrarily be combined with each other, obtained technical solution should also fall into the protection scope of the application after combination.
It should be understood that magnitude of the sequence numbers of the above procedures are not meant to execute suitable in the various embodiments of the application
Sequence it is successive, the execution of each process sequence should be determined by its function and internal logic, the implementation without coping with the embodiment of the present application
Process constitutes any restriction.
For example, in the embodiment of the present application, packing material can be filled into after the groove-like structure 101 be arranged again it is described extremely
A few connecting line 102, also can be set the chip 103 is fixed on again after at least one connecting line 102 it is described
In groove-like structure 101.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
Scope of the present application.
In several embodiments provided herein, it should be understood that in disclosed integrating device, integrating device
Component and the method for preparing integrating device, may be implemented in other ways.For example, integrating device described above is implemented
Example is only exemplary, for example, the division of the component, only a kind of logical function partition, can have in actual implementation
Other division mode, such as multiple components or component can be combined or can be integrated into another system or some features
It can ignore, or not execute.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be with
It is the indirect coupling or communication connection of device or component through some interfaces, can be electrical property, mechanical or other forms.
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain
Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be based on the protection scope of the described claims.
Claims (30)
1. a kind of integrating device including film transistor device characterized by comprising
Substrate, chip and film transistor device；
The top of the substrate is arranged in the film transistor device；
Wherein, the upper surface of the substrate has been downwardly extending groove-like structure, is provided at least one in the groove-like structure
Connecting line, the chip are arranged in the groove-like structure, and pass through at least one connecting line and the thin film transistor (TFT)
Device connection.
2. integrating device according to claim 1, which is characterized in that the film transistor device at least covers the slot
The opening of shape structure.
3. integrating device according to claim 1, which is characterized in that the thickness of the chip is less than or equal to the channel-shaped
The depth of structure.
4. integrating device according to claim 3, which is characterized in that the depth of the groove-like structure is greater than 100 microns of um.
5. integrating device according to claim 1, which is characterized in that the side of the groove-like structure and the groove-like structure
Lower surface formed angle be greater than predetermined angle.
6. integrating device according to claim 1, which is characterized in that the material that at least one connecting line uses be with
Any one of lower material:
Molybdenum-aluminium-molybdenum Mo-Al-Mo structural metallic material, titanium-aluminium-titanium Ti-Al-Ti structural metallic material, conducting glass material and
Metal material.
7. integrating device according to claim 1, which is characterized in that the chip passes through conducting resinl and described at least one
Connecting line is connected.
8. integrating device according to claim 1, which is characterized in that the chip is provided at least one pad.
9. integrating device according to claim 8, which is characterized in that described in being provided on the lower surface of the chip at least
One pad.
10. integrating device according to claim 8, which is characterized in that described in being provided on the upper surface of the chip extremely
A few pad.
11. integrating device according to claim 8, which is characterized in that at least one described pad and described at least one
Connecting line corresponds.
12. integrating device according to claim 1, which is characterized in that the chip includes data driving chip, the number
The electrode layer being connected to according to driving chip by least one connecting line in the film transistor device.
13. integrating device according to claim 1, which is characterized in that the chip includes scanning drive chip, described to sweep
Retouch the electrode layer that driving chip is connected in the film transistor device by least one connecting line.
14. integrating device according to claim 1, which is characterized in that the integrating device further include:
Packing material in the groove-like structure, the packing material is for the chip to be fixed in the groove-like structure.
15. integrating device according to claim 14, which is characterized in that the thermal expansion coefficient of the packing material with it is described
The difference of the thermal expansion coefficient of substrate is less than or equal to preset threshold.
16. integrating device according to claim 14, which is characterized in that the packing material and the material of the substrate are
Same material.
17. integrating device according to claim 14, which is characterized in that the packing material is flowable before curing.
18. integrating device according to claim 14, which is characterized in that at least one connecting line is arranged in the base
Between bottom and the packing material.
19. integrating device according to claim 14, which is characterized in that at least one connecting line setting is filled out described
Fill the upper surface of material and the upper surface of the groove-like structure.
20. integrating device according to claim 14, which is characterized in that the packing material completely fills the channel-shaped knot
Structure.
21. integrating device according to claim 14, which is characterized in that the packing material is partially filled with the channel-shaped knot
Structure.
22. integrating device according to claim 1, which is characterized in that the film transistor device includes:
Articulamentum, the articulamentum are connected to external devices and/or at least one connecting line.
23. integrating device according to claim 1, which is characterized in that the integrating device further include:
The top of the substrate is arranged in photodiode, the photodiode, and the photodiode and the film are brilliant
Electrode layer in body tube device is connected.
24. integrating device according to claim 1, which is characterized in that the material that the substrate uses for glass material or
Polyimide material.
25. integrating device according to claim 1, which is characterized in that the integrating device further include:
At least one connecting pin, at least one described connecting pin with extraneous device for being electrically connected, at least one described connecting pin
The top of the substrate is set.
26. integrating device according to claim 25, which is characterized in that a connection at least one described connecting pin
End is connected with a connecting line at least one connecting line.
27. integrating device according to claim 25, which is characterized in that at least one described connecting pin and the film are brilliant
Electrode layer in body tube device is connected.
28. integrating device according to claim 25, which is characterized in that the connecting pin is pad or tin ball.
29. a kind of display device characterized by comprising
Integrating device described in any one of claim 1 to 28.
30. a kind of electronic equipment characterized by comprising
Display device described in claim 29.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680859.1U CN208848906U (en) | 2018-10-16 | 2018-10-16 | Integrating device, display device and electronic equipment with film transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680859.1U CN208848906U (en) | 2018-10-16 | 2018-10-16 | Integrating device, display device and electronic equipment with film transistor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208848906U true CN208848906U (en) | 2019-05-10 |
Family
ID=66375501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821680859.1U Active CN208848906U (en) | 2018-10-16 | 2018-10-16 | Integrating device, display device and electronic equipment with film transistor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208848906U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109496352A (en) * | 2018-10-16 | 2019-03-19 | 深圳市汇顶科技股份有限公司 | Integrating device and preparation method thereof with film transistor device |
-
2018
- 2018-10-16 CN CN201821680859.1U patent/CN208848906U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109496352A (en) * | 2018-10-16 | 2019-03-19 | 深圳市汇顶科技股份有限公司 | Integrating device and preparation method thereof with film transistor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20180012069A1 (en) | Fingerprint sensor, fingerprint sensor package, and fingerprint sensing system using light sources of display panel | |
| CN104934455B (en) | Photoelectric conversion device and electronic equipment | |
| CN106775173A (en) | A kind of touch-control display panel and touch control display apparatus | |
| KR20180081378A (en) | Display device using semiconductor light emitting device | |
| CN108010969B (en) | Sensing unit and manufacturing method thereof | |
| KR20150057110A (en) | Display device using semiconductor light emitting device | |
| KR102316326B1 (en) | Display device using semiconductor light emitting device | |
| KR20180086003A (en) | Display device using semiconductor light emitting device | |
| KR20190076929A (en) | Display device using micro led and manufacturing method thereof | |
| CN103295996B (en) | Base plate for packaging and making method thereof | |
| CN105655378A (en) | Array substrate, OLED display panel, manufacturing method and display device | |
| CN111596796B (en) | Three-dimensional touch module, driving method thereof and display device | |
| KR20180102424A (en) | Display device using semiconductor light emitting device and method for manufacturing | |
| CN109300944A (en) | Display panel and its manufacturing method, display device | |
| KR20180120527A (en) | Method for manufacturing display device using semiconductor light emitting device | |
| CN107452283A (en) | Display module and its manufacture method, display device | |
| KR20160008385A (en) | Phase Detection Auto Focus Pixel and Image Sensor therewith | |
| CN107919059A (en) | Display base plate, display panel and display device | |
| US10811624B2 (en) | Electroluminescent display and method of manufacturing the same | |
| CN110197834A (en) | Array substrate and preparation method thereof, display panel and fingerprint recognition display device | |
| CN208848906U (en) | Integrating device, display device and electronic equipment with film transistor device | |
| US11955080B2 (en) | Display module and electronic device | |
| CN109496352A (en) | Integrating device and preparation method thereof with film transistor device | |
| US11296259B2 (en) | Micro semiconductor chip, micro semiconductor structure, and transfer device | |
| KR102659984B1 (en) | Display device using micro led and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |