CN208834745U - Power source regulating circuit and memory - Google Patents
Power source regulating circuit and memory Download PDFInfo
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- CN208834745U CN208834745U CN201821778493.1U CN201821778493U CN208834745U CN 208834745 U CN208834745 U CN 208834745U CN 201821778493 U CN201821778493 U CN 201821778493U CN 208834745 U CN208834745 U CN 208834745U
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Abstract
The disclosure is directed to a kind of power source regulating circuit and memories, comprising: frequency control module, clock module and charge pump；Frequency control module is used to determine the frequency of memory according to the Configuration Values at the column address subcommand time interval of memory；Clock module is connected with the frequency control module, and the clock signal of assigned frequency is exported for the frequency height according to memory；Charge pump is connected with the clock module, and the clock signal carries out reduced pressure operation to supply voltage for controlling the charge pump, exports negative supply.The disclosure realizes the real-time adjusting to the working frequency of charge pump, improves the transient response speed of the negative supply when memory operation frequencies change.And reduce the noise on negative supply according to the working frequency that the working frequency of memory adjusts charge pump in real time.
Description
Technical field
This disclosure relates to memory technology field, in particular to a kind of power source regulating circuit and memory.
Background technique
With the development of technology and progress, memory chip in each electronic product using more and more extensive, depositing
In the course of work of reservoir, the switching frequency of wordline and the working frequency of memory chip are related, and negative supply VKK is wordline
Shutdown provides negative supply, therefore the stability of negative supply VKK is extremely important to the normal work of memory chip.
Currently, usual dynamic realtime monitors VKK voltage magnitude, and then controls electricity in the course of work of memory chip
The running clock of lotus pump circuit is turned on or off, to obtain stable negative supply VKK.However when the work of memory frequency
When rate changes, the clock frequency of charge pump circuit, which can't make, to be adaptively adjusted, this will lead to the wink of negative supply VKK
State response speed is low, and the noise of negative supply VKK is larger.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of power source regulating circuit and memory, and then overcomes at least to a certain extent
Due to the relevant technologies limitation and defect caused by negative supply VKK transient response speed is low, noise is big problem.
According to the disclosure in a first aspect, providing a kind of power source regulating circuit, comprising:
Frequency control module, the first control of Configuration Values output for the column address subcommand time interval according to memory are believed
Number；
Clock module is connected with the frequency control module, for exporting assigned frequency according to the first control signal
Clock signal；
Charge pump is connected with the clock module, the clock signal for control the charge pump to supply voltage into
Row reduced pressure operation exports the negative supply for turning off wordline.
According to an embodiment of the disclosure, the frequency control module includes:
Selection circuit, the selection circuit obtain the Configuration Values at column address subcommand time interval, according to the column ground
The Configuration Values at location subcommand time interval determine the frequency of the memory, and export first control signal.
According to an embodiment of the disclosure, the power source regulating circuit further include:
Mode register is connected with the frequency control module, for storing matching for column address subcommand time interval
Set value.
According to an embodiment of the disclosure, the power source regulating circuit further include:
Comparator, input terminal are connected with the output end of the charge pump, and output end is connected with the clock module, are used
The clock module is fed back in the negative supply and preset voltage value, and by comparison result.
According to an embodiment of the disclosure, the clock module includes:
Oscillator is connected with the frequency control module, for generating the first clock letter according to the first control signal
Number；
Non-overlapping clock generation circuit, input terminal are connected with the oscillator, and output end is connected with the charge pump,
For converting second clock signal for the first clock signal；
Wherein, the second clock signal be non-overlapping clock signal, for control the charge pump to supply voltage into
Row reduced pressure operation.
According to an embodiment of the disclosure, the memory includes dynamic random access memory.
According to the second aspect of the disclosure, a kind of memory, including above-mentioned power source regulating circuit are provided.
The disclosure provides a kind of power source regulating circuit, and the frequency of memory, clock module are determined by frequency control module
According to the clock signal of the rate-adaptive pacemaker assigned frequency of memory, charge pump is controlled by clock signal and exports negative supply.By
It is determined in clock signal according to the Configuration Values at column address subcommand time interval, when the Configuration Values at column address subcommand time interval occur
Variation, clock module according to the Configuration Values at column address subcommand time interval export respective frequencies clock signal, charge pump according to
Clock signal export negative supply, realize to negative supply according to reservoir working frequency variation be adjusted, solve by
In memory frequency variation and clock signal frequency it is constant caused by negative supply transient response speed is low and noise asking greatly
Topic, improves the transient response speed of negative supply, and reduce the noise of negative supply.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of schematic diagram for power source regulating circuit that disclosure exemplary embodiment provides.
Fig. 2 is a kind of circuit diagram for selection circuit that disclosure exemplary embodiment provides.
Fig. 3 is the flow chart for the first power supply adjusting method that disclosure exemplary embodiment provides.
Fig. 4 is the flow chart for second of power supply adjusting method that disclosure exemplary embodiment provides.
Fig. 5 is the flow chart for second of power supply adjusting method that disclosure exemplary embodiment provides.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical attached drawing in figure
Label indicates same or similar structure, thus the detailed description that will omit them.
Term "one", " one ", "the", " described " and "at least one" be to indicate that there are one or more elements/groups
At part/etc.；Term " comprising " and " having " is to indicate the open meaning being included and refer in addition to listing
Element/component part/also may be present except waiting other element/component part/etc.；Term " first ", " second " and " third "
It is used as to mark Deng only and use, be not the quantity limitation to its object.
Block diagram shown in the drawings is only functional entity, not necessarily must be corresponding with physically separate entity.
I.e., it is possible to realize these functional entitys using software form, or these are realized in the module of one or more softwares hardening
A part of functional entity or functional entity, or realized in heterogeneous networks and/or processor device and/or microcontroller device
These functional entitys.
In the related technology, the wordline in memory is triggered by internal negative pressure power supply VKK, the frequency and wordline of memory
Switching frequency it is related.When the frequency of memory changes, the clock frequency of charge pump circuit can not make adaptability tune
It is whole, cause the transient response speed of negative supply VKK low, the problem of vulnerable to noise jamming.
A kind of power source regulating circuit is provided firstly in this example embodiment, as shown in Figure 1, the power source regulating circuit packet
It includes, frequency control module 100, clock module 200 and charge pump 300, frequency control module 100 is with being used for the column according to memory
The Configuration Values at location subcommand time interval (tCCD_L, Cas to Cas Delay Latency) export first control signal；Clock
Module 200 and the frequency control module 100 connect, and receive first control signal, for according to the first specified frequency of control output
The clock signal of rate；Charge pump 300 and the clock module 200 connect, and clock signal is for controlling 300 pairs of electricity of the charge pump
Source voltage carries out reduced pressure operation, exports negative supply VKK.Wherein, charge pump 300, which carries out decompression to power supply, can be charge pump
300 over the ground, that is to say that zero potential carries out reduced output voltage negative supply.
The power source regulating circuit that the embodiment of the present disclosure provides determines the frequency of memory by frequency control module 100, when
Clock module 200 controls charge pump 300 by clock signal and exports according to the clock signal of the rate-adaptive pacemaker assigned frequency of memory
Negative supply VKK.Since clock signal is determined according to the Configuration Values of tCCD_L, when the frequency of memory changes,
The Configuration Values of tCCD_L change, and clock module 200 exports the clock signal of respective frequencies, electricity according to the Configuration Values of tCCD_L
Lotus pump 300 exports negative supply VKK according to clock signal.When the configuration of memory operation frequencies changes, negative supply
The load current of VKK changes, and the clock signal frequency of clock module output is constant, leads to the transient state of negative supply VKK
Response speed is low and noise is big, and the disclosure efficiently solves the above problem.
When the working frequency of memory changes, the working frequency and operating current of the connect load of negative supply VKK
Value can also change, and when wordline shutdown, the voltage value of negative supply VKK can be fluctuated, by and memory operation frequencies
The matched clock signal of institute, can quickly adjust negative supply VKK is restored to it in predetermined voltage range.Improve negative pressure electricity
Source VKK reduces due to the noise that load changes the influence to negative supply VKK and generates the response speed of load variation.
Further, the power source regulating circuit that the embodiment of the present disclosure provides further includes mode register 500, mode register
500 Configuration Values and frequency control module 100 for storing tCCD_L connect.Wherein, mode register 500 can be MRS and post
Storage.
The configuration value signal of tCCD_L is obtained in 100 slave pattern register 500 of frequency control module.The Configuration Values of tCCD_L
It is set in advance in mode register 500, the Configuration Values of tCCD_L can be corresponded with memory cycle, be that is to say and stored
The frequency of device corresponds, for example, the Configuration Values of tCCD_L and the corresponding relationship of memory cycle can be as shown in table 1.
Table 1
| Read or write speed | tCCD_L |
| ≤1333Mb/s | 4clocks |
| >1333Mb/s and≤1866Mb/s | 5clocks |
| >1866Mb/s and≤2400Mb/s | 6clocks |
| >2400Mb/s and≤2666Mb/s | 7clocks |
| >2666Mb/s and≤3200Mb/s | 8clocks |
Current tCCD_L signal is obtained in true rate control module slave pattern register 500, is matched according to current tCCD_L
Set the frequency that value determines memory.Clock module can preset multiple operating modes corresponding with tCCD_L Configuration Values, by with
A kind of operating mode of tCCD_L Configuration Values corresponding first control signal selection clock module, make its export predeterminated frequency when
Clock signal.
Frequency control module 100 may include selection circuit, and selection circuit has multi-channel input, mode register 500
When exporting tCCD_L configuration value signal, outputting multiplex signals, every corresponding selection electricity of road tCCD_L configuration value signal can be
The input terminal on road.
For example, tCCD_L as shown in Table 1, mode register 500 can export three road signals, and control selections circuit determines
Corresponding tCCD_L Configuration Values, and then determine the frequency of memory.Selection circuit as shown in Figure 2 has the input of three road signals
End.The signal of first input end S1 inputs five and door respectively, wherein first with door A1, second and door A2, third and door A3 and
Phase inverter is provided between first input end S1；The signal of second input terminal S2 inputs five and door respectively, wherein second and door
Phase inverter is provided between A2, third and door A3 and the second input terminal S2, the signal of third input terminal S3 inputs five and door,
In be provided with phase inverter between first and door A1, third and door A3 and third input terminal S3.
First it is corresponding with door A1 output signal be 4clocks, second it is corresponding with door A2 output signal be 5clocks,
It is 6clocks that third is corresponding with door A3 output signal, the 4th it is corresponding with door A4 output signal be 7clocks, the 5th and door
Corresponding A5 output signal is 8clocks, the corresponding relationship of tCCD_L signal and tCCD_L that mode register 500 exports, such as
Shown in table 2.
Table 2
| tCCD_L | TCCD_L signal | |
| ≤1333Mb/s | 4clocks | 000 |
| >1333Mb/s and≤1866Mb/s | 5clocks | 001 |
| >1866Mb/s and≤2400Mb/s | 6clocks | 010 |
| >2400Mb/s and≤2666Mb/s | 7clocks | 011 |
| >2666Mb/s and≤3200Mb/s | 8clocks | 100 |
| reserved | 101 | |
| reserved | 110 | |
| reserved | 111 |
In table, tCCD_L configures value signal and arranges according to the sequence of first the second input terminal of input, third input terminal.
For another example, if tCCD_L Configuration Values are 4bit, its value can be 0000~1111, when tCCD_L=0000~
When 0011, frequency control module exports first control signal 00；As tCCD_L=0100~0111, frequency control module output
First control signal 01；As tCCD_L=1000~1011, frequency control module exports first control signal 10；Work as tCCD_L
When=1100~1111, frequency control module exports first control signal 11.Oscillator can preset four kinds of operating modes at this time,
And 00~11 respectively control oscillator four kinds of operating modes, generate the clock signal of four kinds of different frequencies.
Clock module 200 may include: oscillator 210 and non-overlapping clock generation circuit 220, oscillator 210 and described
Frequency control module 100 connects, for generating the first clock signal according to the frequency of the memory；Non-overlapping clock generates electricity
220 input terminal of road and the oscillator 210 connect, and output end and the charge pump 300 connect, for turning the first clock signal
Turn to second clock signal；Wherein, the second clock signal is non-overlapping clock signal, for controlling the charge pump 300
Reduced pressure operation is carried out to supply voltage, exports negative supply VKK.
Frequency control module 100 is after determining memory frequency, output first control signal control oscillator 210 output the
One clock signal.First clock signal can be voltage signal, and oscillator 210 can be voltage controlled oscillator at this time, according to storage
The frequency of device determines the frequency for the first clock signal that oscillator 210 needs to export, and is controlled by the voltage signal of response amplitude
First clock signal of the output assigned frequency of oscillator 210.For example, being provided with matching for eight tCCD_L in mode register 500
Value is set, the output frequency that memory frequency corresponding to the Configuration Values of each tCCD_L needs voltage controlled oscillator 210 can be calculated,
According to 210 output frequency demand of oscillator, eight control voltage values are set, and are corresponded with first control signal, when corresponding
First control signal be triggered, pass through corresponding voltage signal control oscillator 210 export the first clock signal.
Certainly oscillator 210 is also possible to other kinds of oscillator in practical applications, can be believed by the first control
The input current or the capacitor in oscillator 210 of number control oscillator 210, to control the first clock of the output of oscillator 210
The frequency of signal, the embodiment of the present disclosure are not specifically limited in this embodiment.
In order to avoid capacitor enters working condition in not complete charge and discharge in charge pump 300, turn-on time is influenced
With switching tube performance, non-overlapping second clock can be converted for the first clock signal by non-overlapping clock generation circuit 220
Signal, second clock signal control charge pump 300 and export negative supply VKK, ensure that the accurate of 300 turn-on time of charge pump
Property, switch performance is improved, wherein second clock signal may include two paths of signals.
Compared by the working condition that second clock signal controls charge pump 300 when negative supply VKK voltage is lower
Device 400 does not work, and second clock signal generates, and negative supply VKK voltage is increased；When negative supply VKK voltage is higher, than
Compared with the signal that device 400 generates shutdown clock module 200, the shutdown of second clock signal, negative supply VKK is gradually decreased.Carry out
When memory word line triggers, the voltage value of triggering wordline shutdown could be provided when negative supply VKK reaches predeterminated voltage, preset
Voltage value is the voltage value that the wordline in memory can be made to turn off.In order to control the size of negative supply VKK, the disclosure is implemented
The power source regulating circuit that example provides can also include: comparator 400, and input terminal is connected with the output end of the charge pump 300,
Its output end and the oscillator 210 connect, and are used for the negative supply VKK and preset voltage value.Comparator 400 obtains
The negative supply VKK that charge pump 300 exports, and negative supply VKK and preset voltage value are compared, if negative supply VKK
Greater than preset voltage value, the first clock signal that oscillator 210 adjusts output is controlled, reduces negative supply VKK；Work as negative supply
When VKK is less than preset voltage value, control oscillator 210 adjusts the first clock signal of output, increases negative supply VKK.Such as
Oscillator 210 can be turned off when negative supply VKK is higher than predeterminated voltage, stop the first clock signal of output, make negative supply
VKK decline opens oscillator 210 when negative supply VKK is lower than predeterminated voltage, exports the first clock signal, negative supply
VKK rises.
Memory described in the embodiment of the present disclosure can be DRAM, be also possible in practical applications certainly SRAM or
NAND etc., the embodiment of the present disclosure is not specifically limited in this embodiment.
A kind of power supply adjusting method is also provided in this example embodiment, as shown in figure 3, this method comprises the following steps:
Step S310 exports first control signal according to the Configuration Values at the column address subcommand time interval of memory；
Step S320 exports the clock signal of assigned frequency according to the first control signal；
Step S330 controls charge pump for supply voltage and carries out reduced pressure operation, and output buck by the clock signal
Negative supply afterwards.
The power supply adjusting method that the embodiment of the present disclosure provides passes through the first control of Configuration Values output of the tCCD_L of memory
Signal, clock module export the clock signal of assigned frequency according to first control signal, and it is defeated to control charge pump by clock signal
Negative supply out.Since clock signal is determined according to the Configuration Values of tCCD_L, when the frequency of memory changes,
The Configuration Values of tCCD_L change, and clock module exports the clock signal of respective frequencies, charge according to the Configuration Values of tCCD_L
Pump exports negative supply according to clock signal, realizes the real-time adjusting to negative supply, solves since memory frequency becomes
Change and clock signal frequency it is constant caused by negative supply transient response speed is low and problem that noise is big, improve negative pressure electricity
The transient response speed in source, and reduce the noise of negative supply.
In step s310, first control signal is exported according to the Configuration Values of the tCCD_L of memory.
Wherein, the working frequency of the Configuration Values of tCCD_L and memory corresponds, and frequency determining circuit passes through tCCD_L
Configuration Values determine the frequency of memory, frequency control module 100 obtains the configuration value signal of tCCD_L, judges current tCCD_L
The corresponding memory frequency of Configuration Values, export first control signal.It can be determined and be stored by selection circuit as shown in Figure 2
The frequency of device, multichannel input signal input selection circuit, selection circuit determines the Configuration Values of tCCD_L, and then determines Memory bandwidth
Rate, according to the rate-adaptive pacemaker first control signal of the memory.
In step s 320, the clock signal of assigned frequency can be exported according to the first control signal.
Clock signal is exported by clock module 200, the frequency of clock signal is controlled by first control signal, for example,
The Configuration Values of eight tCCD_L, the corresponding first control signal of the Configuration Values of each tCCD_L are equipped in memory.Each
One control signal can control the clock signal that clock module 200 exports an assigned frequency.
In step S330, charge pump can be controlled by supply voltage and carries out reduced pressure operation by the clock signal, and
Negative supply after output buck.
Wherein, charge pump 300 is controlled by clock signal, exports negative supply VKK, to trigger the pass of the wordline in memory
It is disconnected.
Optionally, as shown in figure 4, before step S310, further includes:
Step S340 obtains the Configuration Values at column address subcommand time interval, column address subcommand time interval
Configuration Values are stored in mode register.
Mode register 500 and frequency control module 100 connect, and obtain in 100 slave pattern register 500 of frequency control module
Take the Configuration Values of tCCD_L.The Configuration Values of tCCD_L are set in advance in mode register 500, and the Configuration Values of tCCD_L can be with
Memory cycle corresponds, and that is to say and corresponds with the frequency of memory.
Further, as shown in figure 5, step S320 may include:
Step S321 generates the first clock signal according to the first control signal；
First clock signal is converted second clock signal by step S322, and the second clock signal is non-friendship
Folded clock signal carries out reduced pressure operation to supply voltage for controlling the charge pump, exports negative supply.
It wherein, can be by oscillator 210, when generating first under the control of first control signal in step S321
The frequency of clock signal, the first clock signal is determined by the frequency of memory, for controlling charge pump output negative supply VKK.
In step S322, second clock signal can be converted for the first clock signal by non-overlapping clock circuit,
Second clock signal is non-overlapping clock signal.Charge pump 300 is controlled by second clock signal and exports negative supply VKK, is protected
The accuracy for having demonstrate,proved 300 turn-on time of charge pump, improves switch performance.
Further, after step S330, can also include:
Step S350, the negative supply and predeterminated voltage, when the negative supply is higher than the predeterminated voltage,
Controlling charge pump reduces the voltage of output negative supply, when the negative supply is lower than the predeterminated voltage, controls charge pump
Increase the voltage of output negative supply.
Wherein it is possible to compare negative supply VKK and preset voltage value by comparator 400, comparator 400 obtains charge pump
The negative supply VKK of 300 outputs, and negative supply VKK and preset voltage value are compared, if negative supply VKK is greater than in advance
If voltage value, control oscillator 210 adjusts the first clock signal of output, reduces negative supply VKK, reduces power consumption；Work as negative pressure
When power supply VKK is less than preset voltage value, control oscillator 210 adjusts the first clock signal of output, increases negative supply VKK.
For example, oscillator 210 can be turned off when negative supply VKK is higher than predeterminated voltage, stops the first clock signal of output, make to bear
Voltage source VKK decline opens oscillator 210 when negative supply VKK is lower than predeterminated voltage, exports the first clock signal, negative pressure
Power supply VKK rises.
It should be noted that although describing each step of method in the disclosure in the accompanying drawings with particular order,
This does not require that or implies must execute these steps in this particular order, or have to carry out step shown in whole
Just it is able to achieve desired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and held by certain steps
Row, and/or a step is decomposed into execution of multiple steps etc..
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (7)
1. a kind of power source regulating circuit characterized by comprising
Frequency control module, the Configuration Values for the column address subcommand time interval according to memory export first control signal；
Clock module is connected with the frequency control module, for according to the first control signal export assigned frequency when
Clock signal；
Charge pump is connected with the clock module, and the clock signal drops supply voltage for controlling the charge pump
Press operation exports the negative supply for turning off wordline.
2. power source regulating circuit as described in claim 1, which is characterized in that the frequency control module includes:
Selection circuit, the selection circuit obtain the Configuration Values at column address subcommand time interval, are ordered according to the column address
It enables the Configuration Values of time interval determine the frequency of the memory, and exports first control signal.
3. power source regulating circuit as described in claim 1, which is characterized in that the power source regulating circuit further include:
Mode register is connected with the frequency control module, for storing the Configuration Values at column address subcommand time interval.
4. power source regulating circuit as described in claim 1, which is characterized in that the power source regulating circuit further include:
Comparator, input terminal are connected with the output end of the charge pump, and output end is connected with the clock module, for than
The negative supply and preset voltage value, and comparison result is fed back into the clock module.
5. power source regulating circuit as described in claim 1, which is characterized in that the clock module includes:
Oscillator is connected with the frequency control module, for generating the first clock signal according to the first control signal；
Non-overlapping clock generation circuit, input terminal are connected with the oscillator, and output end is connected with the charge pump, are used for
Second clock signal is converted by the first clock signal；
Wherein, the second clock signal is non-overlapping clock signal, is dropped for controlling the charge pump to supply voltage
Press operation.
6. power source regulating circuit as claimed in claim 1 to 5, which is characterized in that the memory includes dynamic random
Access memory.
7. a kind of memory, which is characterized in that including the power source regulating circuit as described in claim 1 to 6 is any.
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| CN201821778493.1U CN208834745U (en) | 2018-10-30 | 2018-10-30 | Power source regulating circuit and memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417240A (en) * | 2018-03-05 | 2018-08-17 | 睿力集成电路有限公司 | Control circuit, memory and its control method of memory |
| CN111128257A (en) * | 2018-10-30 | 2020-05-08 | 长鑫存储技术有限公司 | Power supply regulating circuit and method and memory |
-
2018
- 2018-10-30 CN CN201821778493.1U patent/CN208834745U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417240A (en) * | 2018-03-05 | 2018-08-17 | 睿力集成电路有限公司 | Control circuit, memory and its control method of memory |
| CN108417240B (en) * | 2018-03-05 | 2019-10-01 | 长鑫存储技术有限公司 | Control circuit, memory and its control method of memory |
| CN111128257A (en) * | 2018-10-30 | 2020-05-08 | 长鑫存储技术有限公司 | Power supply regulating circuit and method and memory |
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