CN108417240B - Control circuit, memory and its control method of memory - Google Patents
Control circuit, memory and its control method of memory Download PDFInfo
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- CN108417240B CN108417240B CN201810180517.1A CN201810180517A CN108417240B CN 108417240 B CN108417240 B CN 108417240B CN 201810180517 A CN201810180517 A CN 201810180517A CN 108417240 B CN108417240 B CN 108417240B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Abstract
The present invention provides a kind of control circuit of memory, including frequency determinative elements and pattern switching control unit, and the input terminal of frequency determinative elements is connected to the external system of memory, receives the signal of external system and determines the present operating frequency section of external system；The input terminal of pattern switching control unit is connected to frequency determinative elements, receive present operating frequency section, and it controls memory and write operation is executed with operating mode corresponding with present operating frequency section, control circuit of the invention can pass through the present operating frequency section of the external system of determining memory, make memory in low frequency using the operating mode for reducing power consumption, writing rate is improved in high frequency, so that the configuration optimization of memory.In addition, the present invention also provides the control methods of a kind of memory and memory.
Description
Technical field
The present invention relates to semiconductor integrated circuit field more particularly to a kind of control circuit of memory, memory and its
Control method.
Background technique
Dynamic random access memory (Dynamic Random Access Memory, abbreviation DRAM) one kind is common to deposit
Reservoir.In the application of DRAM, the requirement for low-power consumption and speed is higher and higher, when external system enters high-frequency work mode
When, it may require that DRAM processing data at high speed；When external system enters low frequency operating mode, if DRAM is also with high-frequency work
Mode handles data, just will increase power consumption.There are also applications only to pursue low-power consumption simultaneously, or only pursues high speed.How
Design configurations make power consumption and being optimal of speed, to improve DRAM performance, while meeting the needs of different application, are urgently to solve
Certainly the problem of.
Summary of the invention
The embodiment of the present invention provides control circuit, memory and its control method of a kind of memory, to solve or alleviate
One or more technical problems in the prior art.
As the one aspect of the embodiment of the present invention, the embodiment of the present invention provides a kind of control circuit of memory, comprising:
Frequency determinative elements, input terminal are connected to the external system of memory, and the frequency determinative elements receive described outer
The signal of portion's system, and determine the present operating frequency section of the external system of memory；And
Pattern switching control unit, input terminal are connected to the frequency determinative elements, and the pattern switching control unit connects
The present operating frequency section is received, and controls the memory with Working mould corresponding with the present operating frequency section
Formula executes write operation.
In some embodiments, the frequency determinative elements include:
Frequency detecting unit, output end are connected to the pattern switching control unit, and the frequency detecting unit is from described
Memory obtains the first clock signal and obtains second clock signal from the external system, and is believed according to first clock
Number and the second clock signal determine the present operating frequency section；And
Register, output end are connected to the frequency detecting unit, and the register deposits the second clock signal
Parameter, for when the parameter of the second clock signal changes, Xiang Suoshu frequency detecting unit sends enable signal, with
The frequency detecting unit is set to work.
Further, the frequency detecting unit includes:
First counter, input terminal are connected to the register, are used for when the register sends the enable signal,
The first clock signal is received from the memory, to obtain reference clock frequency；
Second counter, input terminal are connected to the register, are used for when the register sends the enable signal,
Second clock signal is received from the external system, to obtain the present operating frequency of the external system；And
Comparator, input terminal are connected to first counter and second counter, and output end is connected to the mould
Formula switch control unit is used for the reference clock frequency and the present operating frequency, with the determination work at present
Frequency separation.
In some embodiments, the frequency determinative elements include:
Register, output end are connected to the pattern switching control unit, and the register deposits the external system
The present operating frequency section, and the present operating frequency section is sent to the pattern switching control unit.
As the other side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of memory, comprising:
Storage array, including multiple storage units, the multiple memory cell array distribution；
A plurality of inputoutput data signal wire, is connected to the multiple storage unit；
First driving unit is connected to the proximal end of the inputoutput data signal wire, is used for from the input and output number
Memory is driven according to the proximal end of signal wire；And
Above-described control circuit, output end is connected to first driving unit, for the outside according to memory
The write operation of memory described in the present operating frequency range restraint of system.
Further, first driving unit include first driving subelement and second driving subelement, described first
The transistor size of subelement is driven to be less than the transistor size of the second driving subelement；And the working frequency section
Including the first working frequency section and the second working frequency section, when the present operating frequency section of the external system exists
When in the range of first working frequency section, the memory enters the first operating mode, the work electricity of the memory
It forces down in normal operational voltage value, and the first driving subelement work；When the present operating frequency section is described
When in the range of the second working frequency section, the memory enters the second operating mode, the operating voltage etc. of the memory
In normal operational voltage value, and the second driving subelement works.
Further, the memory further includes the second driving unit, is connected to the inputoutput data signal wire
Distally, for driving the memory from the distal end of the inputoutput data signal wire；The output end of the control circuit is also
It is connected to second driving unit, column decoding unit and column operation timing control unit；It also wraps in the working frequency section
Third working frequency section is included, when in the range of the present operating frequency section is in the third working frequency section, institute
It states memory and enters third operating mode, the operating voltage of the memory is equal to normal operational voltage value, and described first
Driving unit and second driving unit work.
Further, the working frequency section further includes the 4th working frequency section, when the present operating frequency area
Between in the range of the 4th working frequency section when, the memory enter the 4th operating mode, the work of the memory
Make voltage higher than normal operational voltage value, and first driving unit and second driving unit work.
As the other side of the embodiment of the present invention, the embodiment of the present invention also provides a kind of control method of memory,
Include:
The signal of the external system of memory is received, and determines the present operating frequency section of the external system；And
The operating mode that the memory is controlled to match with the present operating frequency section executes write operation.
In some embodiments, the step of present operating frequency section of the external system of the determining memory includes:
The first clock signal is obtained from the memory and obtains second clock signal from the external system；And
The present operating frequency section is determined according to first clock signal and the second clock signal.
The embodiment of the present invention by adopting the above technical scheme, can optimize the power consumption and speed configuration of memory.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings depict only according to the present invention
Disclosed some embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the circuit diagram of the control circuit of the memory of embodiment one.
Fig. 2 is the circuit diagram of the frequency detecting unit of the control circuit of the memory of embodiment one.
Fig. 3 is the circuit diagram of the memory of embodiment one.
Fig. 4 is the flow chart of the control method of the memory of embodiment one.
Fig. 5 is the circuit diagram of the control circuit of the memory of embodiment two.
Description of symbols:
10: memory；100: control circuit；110: frequency determinative elements；
120: pattern switching control unit；111: frequency detecting unit；112: register；
111A: the first counter；111B: the second counter；111C: comparator；
11: the first driving units；12: the second driving units；13: storage array；
14: inputoutput data signal wire；15: column decoding unit；
16: column operation timing control unit；11A: the first driving subelement；
11B: the second driving subelement；13A: storage unit；
14A: the proximal end of inputoutput data signal wire；14B: the distal end of inputoutput data signal wire.
200: control circuit；210: frequency determinative elements；212: register.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be modified by various different modes.
Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected, can also be communication；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the interaction relationship of the connection or two elements inside two elements.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature "upper" or "lower"
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Right above second feature and oblique upper, or first feature horizontal height is merely representative of higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " include fisrt feature right above second feature and oblique upper, or be merely representative of
One characteristic level height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize different structure of the invention.In order to
Simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.Certainly, they are merely examples, and
And it is not intended to limit the present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, itself not indicate between discussed various embodiments and/or setting
Relationship.
The embodiment of the present invention passes through the present operating frequency section for determining the external system of memory, to control memory
Into the operating mode to match with present operating frequency section, in low frequency using the operating mode for reducing power consumption, in high frequency
Shi Zengjia read or write speed, so that the configuration optimization of memory.
Embodiment one
As shown in Figure 1, the control circuit 100 of the memory of the present embodiment includes frequency determinative elements 110 and pattern switching
Control unit 120, wherein the input terminal of frequency determinative elements 110 is connected to the external system of memory, for receiving external system
The signal of system, and determine the present operating frequency section of the external system of memory；The input terminal of pattern switching control unit 120
Frequency determinative elements 110 are connected to, for receiving present operating frequency section, and memory is controlled and enters and work as with external system
The operating mode that preceding working frequency section matches, i.e., with Working mould corresponding with the present operating frequency section of external system
Formula executes write operation.In the present embodiment, frequency determinative elements 110 include frequency detecting unit 111 and register 112.
The output end of frequency detecting unit 111 is connected to the input terminal of pattern switching control unit 120, is used for from memory
It obtains the first clock signal ClkRef and obtains second clock signal ClkExt from external system, and according to the first clock signal
ClkRef and second clock signal ClkExt determines the present operating frequency section of external system, wherein the first clock signal
ClkRef, that is, memory internal clock signal, from the clock oscillator of memory inside, second clock signal ClkExt
It is the external timing signal of memory, the clock oscillator of the external system applied by the memory.
When memory works on power, power-on reset signal Rst can be sent to frequency detecting unit 111, frequency detecting list
Member 111 empties current data.In the present embodiment, according to the protocol specification of external system, register 112 is for depositing second clock
The parameter of signal ClkExt deposits numerical value relevant to second clock signal ClkExt.When register 112 is arranged in external system
Or when switching register 112, the numerical value that register 112 is deposited will change, register 112 is to frequency detecting unit
111 transmission enable signal EN are effective, so that frequency detecting unit 111 is worked, to determine the present operating frequency section of external system.
Specifically, as shown in Fig. 2, in the present embodiment, frequency detecting unit 111 includes the first counter 111A, the second meter
Number device 111B and comparator 111C.The input terminal of first counter 111A receives the first clock signal ClkRef, passes through the first meter
Number device 111A can obtain reference clock frequency；The input terminal of second counter 111B receives second clock signal ClkExt, with
Obtain the present operating frequency of external system；The input terminal of comparator 111C is connected to the first counter 111A and the second counter
111B, output end are connected to pattern switching control unit 120, benchmark clock frequency and present operating frequency are used for, with true
Determine the present operating frequency section FQ of external system, and the present operating frequency section FQ of external system is sent to pattern switching
Control unit 120 controls memory by pattern switching control unit 120 and enters the work to match with present operating frequency section FQ
Operation mode executes corresponding write operation.
When the numerical value of register 112 changes, illustrate that second clock signal ClkExt changes, i.e. external system
Clock switched, at this moment, register 112 can send enable signal EN to the first counter 111A and the second counter 111B
Effectively, the first counter 111A and the second counter 111B is made to work.In addition, can also send and reply by cable when memory powers on
Position signal Rst give the first counter 111A and the second counter 11AB, keeps the first counter 111A and the second counter 111B clear
Empty current data.
As shown in figure 3, the present embodiment also provides a kind of memory 10, including above-described control circuit 100, and also
When including the first driving unit 11, storage array 13, a plurality of inputoutput data signal wire 14, column decoding unit 15 and column decoding
Sequence control unit 16.Wherein, storage array 13 is made of the storage unit 13A of multiple array distributions, and the control of column operation timing is single
Member 16 and column decoding unit 15 enable corresponding storage unit 13A, and are read by a plurality of inputoutput data signal wire 14
Write operation.The output end of control circuit 100 is connected to the first driving unit 11, column operation timing control unit 16 and column decoding list
Member 15.Other compositions of the memory 10 of the present embodiment, such as secondary data sense amplifier, it is common can be used in this field
Technical staff with the following various technical solutions known, is not detailed herein now.
Wherein, the first driving unit 11 is used to drive memory from the proximal end 14A of a plurality of inputoutput data signal wire 14
10, it is preferable that the first driving unit includes the first driving subelement 11A and the second driving subelement 11B, the first driving subelement
Transistor size of the crystal backbone size of 11A less than the second driving subelement 11B, therefore, the drive of the first driving subelement 11A
Kinetic force and power consumption are both less than the second driving subelement 11B.
Preferably, the memory of the present embodiment further includes the second driving unit 12, for believing from a plurality of inputoutput data
The distal end 14B of number line 14 drives memory 10, and the output end of control circuit 100 is also attached to the second driving unit 12
Below with reference to the above control circuit 100, to how being illustrated by the configuration that frequency segmentation optimizes memory 10,
It is 4 sections: the first working frequency section, the second working frequency section, third by working frequency interval division in the present embodiment
Working frequency section and the 4th working frequency section, it should be noted that be 4 sections by working frequency interval division be only this
One example of embodiment, the present embodiment do not limit the quantity for how dividing working frequency section and division.For example, by base
The quasi- clock cycle is set as 0.5 nanosecond (ns), and corresponding reference clock frequency is 0.5 Gigahertz (GHZ), working frequency section
Divide such as the following table 1:
Table 1
| Second clock signal ClkExt | FQ | |
| First working frequency section | Clock cycle >=1.5ns | 00 |
| Second working frequency section | 1ns≤clock cycle < 1.5ns | 01 |
| Third working frequency section | 0.5ns≤clock cycle < 1ns | 10 |
| 4th working frequency section | Clock cycle < 0.5ns | 11 |
When second clock signal ClkExt changes, the numerical value that register 112 is deposited will change, register
112 is effective to the transmission of frequency detecting unit 111 enable signal EN, and frequency detecting unit 111 is made to work, to determine and export outside
The present operating frequency section FQ of system.
As FQ=00, i.e., when the present operating frequency section of external system is in the range of the first working frequency section,
Memory 10 enters the first operating mode, and in the first operation mode, the operating voltage of memory 10 is lower than normal working voltage
Value, and the first driving subelement 11A work, the time is write in increase, to reduce power consumption.
As FQ=01, i.e., when the present operating frequency section of external system is in the range of the second working frequency section,
Memory 10 enters the second operating mode, and in the second operation mode, the operating voltage of memory 10 is equal to normal working voltage
Value, and the second driving subelement 11B work.
As FQ=10, i.e., when the present operating frequency section of external system is in the range of third working frequency section,
Memory 10 enters third operating mode, and in the third mode of operation, the operating voltage of memory 10 is equal to normal working voltage
Value, and the first driving unit 11 and the work of the second driving unit 12, improve memory 10 by the second driving unit of distal end
Writing rate.
As FQ=11, i.e., when the present operating frequency section of external system is in the range of the 4th working frequency section,
Memory 10 enters the 4th operating mode, under the 4th operating mode, the first driving unit 11 and the work of the second driving unit 12,
The writing rate of memory 10 is improved by the second driving unit of distal end, and the operating voltage of memory 10 is increased to above just
Normal operating voltage value.
The present embodiment also provides a kind of control method of memory 10, as shown in Figure 4, comprising:
S110 determines the present operating frequency section of the external system of memory 10；And
S120 controls memory 10 with the operating mode to match with present operating frequency section and executes write operation.
Specifically, in step s 110, when the numerical value of register 112 changes, frequency detecting unit 111 is from storage
Device 10 obtains the first clock signal ClkRef and obtains second clock signal ClkExt from external system；And according to the first clock
Signal ClkRef and second clock signal ClkExt determine present operating frequency section.
The memory 10 of the present embodiment can be when external clock changes by control circuit 100, initiation culture detection
Circuit 111 to determine the present operating frequency section of external clock, and controls memory by pattern switching control unit 120
10, which enter corresponding operating mode, executes write operation, to distribute rationally.
Embodiment two
As shown in figure 5, the difference with embodiment one is the present embodiment provides a kind of control circuit 200 of memory, this
The frequency determinative elements 210 of embodiment include register 212, and register 212 can be deposited according to the protocol specification of external system
The present operating frequency section of external system, so that the present operating frequency section of external system is directly sent to pattern switching
Control unit 120 controls memory by pattern switching control unit 120 and enters the work to match with present operating frequency section
Mode executes write operation.
Preferably, the frequency determinative elements 210 of the present embodiment can also include frequency detecting unit 111, work as external system
Protocol specification when register 212 being allow to deposit the present operating frequency section of external system, sent out to frequency detecting unit 110
It send enable signal EN invalid, frequency detecting unit 110 is closed, to reduce power consumption；When the protocol specification according to external system makes to post
When storage 212 deposits numerical value relevant to second clock signal ClkExt, register 212 occurs in second clock signal ClkExt
Frequency detecting unit 111 is enabled when change to work.
The present embodiment also provides a kind of memory, and the control circuit 200 of memory, this reality are with the difference of embodiment one
The other structures and working principle for applying the memory of example can be found in embodiment one.
The present embodiment also provides a kind of control method of memory, and the difference with embodiment one is, in step s 110,
Register 212 directly can send present operating frequency section to pattern switching control unit 120.
The control circuit and memory of above embodiments can pass through the work at present frequency of the external system of determining memory
Rate section increases memory, using the operating mode for reducing power consumption, by read or write speed in high frequency, so that memory in low frequency
Configuration optimization.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in its various change or replacement,
These should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
It protects subject to range.
Claims (10)
1. a kind of control circuit of memory, the memory includes storage array, column operation timing control unit and column decoding
Unit, the storage array are made of the storage unit of multiple array distributions, which is characterized in that the control circuit includes:
Frequency determinative elements, input terminal are connected to the external system of memory, and the frequency determinative elements receive the external system
The signal of system, and determine the present operating frequency section of the external system；And
Pattern switching control unit, input terminal are connected to the frequency determinative elements, and the pattern switching control unit receives institute
Present operating frequency section is stated, and controls the memory with operating mode corresponding with the present operating frequency section,
Corresponding storage unit is enabled by the column operation timing control unit and the column decoding unit and executes write operation, when described
When operating mode changes, the read or write speed of the memory changes.
2. control circuit according to claim 1, which is characterized in that the frequency determinative elements include:
Frequency detecting unit, output end are connected to the pattern switching control unit, and the frequency detecting unit is from the storage
Device obtains the first clock signal and obtains second clock signal from the external system, and according to first clock signal and
The second clock signal determines the present operating frequency section；And
Register, output end are connected to the frequency detecting unit, and the register deposits the parameter of the second clock signal,
For when the parameter of the second clock signal changes, Xiang Suoshu frequency detecting unit to send enable signal, so that institute
State frequency detecting unit work.
3. control circuit according to claim 2, which is characterized in that the frequency detecting unit includes:
First counter, input terminal are connected to the register, are used for when the register sends the enable signal, from institute
It states memory and receives the first clock signal, to obtain reference clock frequency；
Second counter, input terminal are connected to the register, are used for when the register sends the enable signal, from institute
It states external system and receives second clock signal, to obtain the present operating frequency of the external system；And
Comparator, input terminal are connected to first counter and second counter, and output end is connected to the mode and cuts
Control unit, the comparator reference clock frequency and the present operating frequency are changed, with the determination current work
Working frequency section.
4. control circuit according to claim 1, which is characterized in that the frequency determinative elements include:
Register, output end are connected to the pattern switching control unit, and the register deposits the described of the external system
Present operating frequency section, and the present operating frequency section is sent to the pattern switching control unit.
5. a kind of memory, which is characterized in that the memory includes:
Storage array, including multiple storage units, the multiple memory cell array distribution；
A plurality of inputoutput data signal wire, is connected to the multiple storage unit；
First driving unit is connected to the proximal end of the inputoutput data signal wire, for believing from the inputoutput data
The proximal end of number line drives memory；And
Such as the described in any item control circuits of Claims 1-4, output end is connected to first driving unit, is used for basis
The write operation of memory described in the present operating frequency range restraint of the external system of memory.
6. memory according to claim 5, which is characterized in that first driving unit includes the first driving subelement
With the second driving subelement, the transistor size of the first driving subelement is less than the transistor of the second driving subelement
Size；And the working frequency section includes the first working frequency section and the second working frequency section, when the external system
When the present operating frequency section of system is in the range of the first working frequency section, the memory enters the first work
Operation mode, the operating voltage of the memory are lower than normal operational voltage value, and the first driving subelement work；Work as institute
When stating present operating frequency section in the range of the second working frequency section, the memory enters the second Working mould
Formula, the operating voltage of the memory are equal to normal operational voltage value, and the second driving subelement work.
7. memory according to claim 6, which is characterized in that the memory further includes the second driving unit, connection
In the distal end of the inputoutput data signal wire, for driving the storage from the distal end of the inputoutput data signal wire
Device, it is single that the output end of the control circuit is also attached to second driving unit, column decoding unit and the control of column operation timing
Member；The working frequency section further includes third working frequency section, when the present operating frequency section is in the third work
When in the range of working frequency section, the memory enters third operating mode, and the operating voltage of the memory is equal to normal
Operating voltage value, and first driving unit and second driving unit work.
8. memory according to claim 7, which is characterized in that the working frequency section further includes the 4th working frequency
Section, when in the range of the present operating frequency section is in the 4th working frequency section, the memory enters the
Four operating modes, the operating voltage of the memory are higher than normal operational voltage value, and first driving unit and described
The work of second driving unit.
9. a kind of control method of memory, the memory includes storage array, column operation timing control unit and column decoding
Unit, the storage array are made of the storage unit of multiple array distributions, which is characterized in that the control method includes:
The signal of the external system of the memory is received, and determines the present operating frequency section of the external system；And
The operating mode that the memory is controlled to match with the present operating frequency section, passes through the column operation timing
Control unit and the column decoding unit enable corresponding storage unit and execute write operation, when the operating mode changes, institute
The read or write speed for stating memory changes.
10. according to the method described in claim 9, it is characterized in that, the present operating frequency of the determination external system
The step of section includes:
The first clock signal is obtained from the memory and obtains second clock signal from the external system；And
The present operating frequency section is determined according to first clock signal and the second clock signal.
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| WO2020098476A1 (en) * | 2018-11-13 | 2020-05-22 | Changxin Memory Technologies, Inc. | Input buffer circuit, intelligent optimization method, and semiconductor memory thereof |
| CN110867203B (en) * | 2019-11-19 | 2021-12-14 | 上海华力微电子有限公司 | Memory read speed regulation circuit |
| CN114388008B (en) * | 2022-01-14 | 2023-08-29 | 长鑫存储技术有限公司 | Power supply control circuit and control method |
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