CN108780658B - Leakage-aware activation control of delay keeper circuits for dynamic read operations in memory bitcells - Google Patents

Abstract

Leakage-aware activation control of a delay keeper circuit for dynamic read operations in a memory bit cell is disclosed. In one aspect, a leakage aware activation control circuit for a dynamic read circuit configured to perform read operations on memory bitcells is provided. To prevent or mitigate contention between the delay keeper circuit and a read port circuit in the dynamic read circuit to pull a dynamic node to an opposite voltage level when initiating a read operation, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delay keeper circuit based on a comparison of N-type field effect transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this way, the leakage-aware activation control circuit is able to adaptively adjust the activation timing of the delay keeper circuit based on the actual relative strengths of NFETs and PFETs.

Description

Leakage-aware activation control of delay keeper circuits for dynamic read operations in memory bitcells

Priority application

Priority is claimed IN U.S. patent application No. 15/085,187 entitled "LEAKAGE-AWARE ACTIVATION CONTROL OF delay keeper CIRCUIT FOR dynamic read OPERATIONs IN MEMORY bitcell" (LEAKAGE-AWARE ACTIVATION CONTROL OF A DELAYED KEEPER CIRCUIT FOR A DYNAMIC READ OPERATION IN a MEMORY BIT CELL), filed on 30/3/2016, which is hereby incorporated by reference IN its entirety.

Technical Field

The technology of the present disclosure relates generally to memory systems that use memory bitcells to store data, and more particularly to dynamic read circuitry for performing dynamic read operations in memory bitcells.

Background

Processor-based systems, including Central Processing Units (CPUs) or other processors, utilize different types of memory for system operations. This memory may be used as system memory for data storage. This memory may also be used to store program code or instructions to be executed by the CPU or processor.

For example, FIG. 1 illustrates a memory system 100 that may be disposed in a processor-based system. Memory system 100 uses memory bitcells 102(1) -102(N) in this particular example to store data, as shown in fig. 1. Each memory bit cell 102 is capable of storing a single bit of information. In FIG. 1, a single column of memory bitcells 104 containing multiple memory bitcells 102(1) through 102(N) is shown, where 'N' may be any number of rows of desired memory bitcells. However, it should be noted that a plurality of memory bitcell columns 104 may be disposed in the memory system 100 to provide a data array of memory bitcells 102(1) through 102 (N). In this example, memory bitcells 102(1) -102(N) are provided in the form of eight (8) transistor (T) (8-T) complementary memory bitcells. Using memory bitcell 102(1) as a reference example, each memory bitcell 102(1) through 102(N) includes two (2) cross-coupled inverters 106(1), 106(2) (i.e., four (4) transistors), and two (2) access transistors 108(1), 108(2) configured to be activated by a row wordline WL (1) of an accessed memory row 1 of memory bitcell 102(1) to perform a write operation, as is well known. Two (2) additional transistors, a pull-down NFET 110(1) and a read port NFET 110(2) are provided for the memory bitcell 102(1) as part of a dynamic read circuit 112 for performing read operations in the memory bitcell 102 (1). The dynamic read circuitry 112 performs a read operation for each of the memory bitcells 102(1) through 102(N) of the memory bitcell column 104. The assertion of a particular word line WL (1) -WL (N) given a respective memory row 1-N controls which memory bit cells 102(1) -102(N) are read by the dynamic read circuitry 112 during a read operation. Providing additional pull-down NFET 110(1) and read port NFET 110(2) in the dynamic read circuit 112 would separate the write performance of the memory bit cell 102(1) from the read performance of the memory bit cell 102 (1).

During a precharge phase of the memory bitcell 102(1), a charge P-type field effect transistor (PFET)116 is activated in response to the read clock signal (read _ clk)118 being a low logic level indicating that a read operation is inactive. This causes the dynamic node 120 in the dynamic read circuit 112 to precharge to the voltage Vdd. Then, during an evaluation phase in response to the read clock signal (read _ clk)118 being a logic high indicating a read operation, PFET 116 is turned off and pull-down NFET 110(1) is activated to be coupled to Ground (GND). If the charge on the complementary node 122C of the selected memory bitcell 102(1) -102(N) is a logic '1' (i.e., voltage Vdd) during a read operation, the pull-down NFET 110(1) is activated to pull the dynamic node 120 down to Ground (GND). Pulling the dynamic node 120 to Ground (GND) will cause the inverter 126 to generate a logic '1' on the sense node 124. However, the keeper circuit 128 is first activated by the complementary node 122C having a logic '1' state during a read operation, which causes the inverter 126 to generate a logic '0' on the sense node 124 and keeps the keeper circuit 128 activated, thereby pulling the dynamic node 120 up to the voltage Vdd in contention with the pull-down NFET 110 (1).

Disclosure of Invention

Aspects of the present disclosure relate to leakage-aware activation control of a delay keeper circuit for dynamic read operations in a memory bit cell. In this regard, in one aspect, a leakage aware activation control circuit for a dynamic read circuit configured to perform read operations on memory bitcells is provided. The dynamic read circuit includes a delay keeper circuit configured to keep a readout value away from a selected memory bit cell asserted on a dynamic node in the dynamic read circuit during an evaluation phase of a dynamic read operation. To prevent or mitigate contention between the delay keeper circuit and a read port circuit in the dynamic read circuit, pulling the dynamic node to an opposite voltage level when initiating a read operation, the delay keeper circuit is selectively deactivated during the evaluation phase. However, because factors such as process variations and technology node scaling can affect the leakage currents and therefore the relative transistor strengths of the transistors in the delay keeper circuit and the read port circuit, aspects disclosed herein include the leakage-aware activation control circuit to control the activation timing of the delay keeper circuit. The leakage-aware activation control circuit is configured to adaptively control the activation timing of the delay keeper circuit based on a comparison of an N-type field effect transistor (NFET) leakage current to a P-type FET (PFET) leakage current. In this manner, if the relative strengths of the NFETs and PFETs in a read port circuit in the delay keeper circuit and the dynamic read circuit are different than a design time assumption, the leakage-aware activation control circuit may adaptively adjust the activation timing of the delay keeper circuit based on the actual relative strengths of the NFETs and PFETs to avoid or reduce contention with the read port circuit in response to the initiation of the evaluation phase of a read operation.

In this regard, in one exemplary aspect, a leakage aware activation control circuit for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bit cell is provided. The leakage-aware activation control circuit includes an NFET leakage circuit configured to provide an NFET leakage indicator indicative of leakage current of at least one NFET in a dynamic read circuit. The leakage-aware activation control circuit also includes a PFET leakage circuit configured to provide a PFET leakage indicator indicative of a leakage current of at least one PFET in a dynamic read circuit. The leakage-aware activation control circuit further includes a comparator circuit. The comparator circuit is configured to receive the NFET leakage indicator and the PFET leakage indicator. The comparator circuit is also configured to compare the NFET leakage indicator with the PFET leakage indicator. The comparator circuit is also configured to generate a FET leakage signal based on a comparison of the NFET leakage indicator and the PFET leakage indicator. The leakage-aware activation control circuit also includes a control signal generator configured to adaptively generate at least one control signal to control activation timing of a delay keeper circuit based on the FET leakage signal.

In another exemplary aspect, a leakage aware activation control circuit for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bitcell is provided. The leakage-aware activation control circuit includes means for providing an NFET leakage indicator indicative of a leakage current of at least one NFET in a dynamic read circuit. The leakage-aware activation control circuit also includes means for providing a PFET leakage indicator indicative of a leakage current of at least one PFET in the dynamic read circuit. The leakage-aware activation control circuit also includes means for receiving the NFET leakage indicator and the PFET leakage indicator. The leakage-aware activation control circuit also includes means for comparing the NFET leakage indicator to the PFET leakage indicator. The leakage-aware activation control circuit also includes means for generating a FET leakage signal based on a comparison of the NFET leakage indicator and the PFET leakage indicator. The leakage-aware activation control circuit also includes means for adaptively generating at least one control signal to control activation timing of a delay keeper circuit based on the FET leakage signal.

In another exemplary aspect, a method for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bitcell is provided. The method includes determining a leakage current of at least one NFET in a dynamic read circuit. The method also includes determining a leakage current of at least one PFET in the dynamic read circuit. The method also includes comparing the determined leakage current of at least one NFET with the determined leakage current of the at least one PFET. The method also includes adaptively generating at least one control signal for a delay keeper circuit based on a comparison of the determined leakage current of at least one NFET and the determined leakage current of the at least one PFET.

In another exemplary aspect, a memory system is provided. The memory system includes a memory bitcell including storage circuitry configured to store complementary voltages and read port circuitry coupled to the storage circuitry. The read port circuit is configured to generate the complementary voltage on a dynamic node in response to a read operation. The memory system also includes a dynamic read circuit. The dynamic read circuit includes the dynamic node and a delay keeper circuit configured to be activated in response to a pulse holding the complementary voltage on the dynamic node outside of an evaluation phase and configured to be deactivated in response to the pulse in response to the evaluation phase of the read operation. The memory system also includes a leakage-aware activation control circuit. The leakage-aware activation control circuit includes a leakage circuit configured to generate a FET leakage signal based on a comparison of a leakage current of at least one NFET and a leakage current of at least one PFET. The leakage-aware activation control circuit also includes a control signal generator configured to adaptively generate at least one control signal to control activation timing of a second delay keeper circuit based on the FET leakage signal. The memory system also includes a pulse generator configured to generate the pulse having a pulse width based on a control activation timing of activation and deactivation of the second delay keeper circuit in response to the at least one control signal.

Drawings

FIG. 1 is a schematic diagram of an exemplary memory system using eight (8) transistor (T) (8-T) memory bitcells and dynamic read circuitry for performing read operations on the memory bitcells;

FIG. 2 is a circuit diagram of an exemplary memory system including a plurality of memory bitcells and a dynamic read circuit using a leakage aware activation control circuit for controlling the activation timing of a delay keeper circuit based on a comparison of N-type field effect transistor (NFET) leakage current to P-type FET (PFET) leakage current in response to a read operation;

FIG. 3A is a timing diagram illustrating the activation of a keeper circuit of the dynamic read circuit of FIG. 2 that is not delayed long enough to thereby push out the pull-down of the dynamic node in the dynamic read circuit and affect read performance;

FIG. 3B is a timing diagram illustrating the activation of the delay keeper circuit of the dynamic read circuit of FIG. 2, which is delayed too long, thereby causing the dynamic node of the dynamic read circuit to drop until ground, causing an erroneous readout value to be generated in response to a read operation;

FIG. 4 is a graph illustrating an exemplary relationship between NFET to PFET leakage current/strength ratio and activation timing of a delay keeper circuit in the dynamic read circuit of FIG. 2;

FIG. 5 is a schematic diagram of an exemplary leakage-aware activation control circuit that may be provided in the dynamic read circuit of FIG. 2 to generate at least one control signal to control the activation timing of pulses provided to the delay keeper circuit to control the activation timing of the delay keeper circuit based on a comparison of NFET leakage current to PFET leakage current;

FIG. 6 is a flow diagram illustrating an exemplary process of controlling activation timing of a delay keeper circuit in the dynamic read circuit in FIG. 5 for a read operation in a memory bit cell;

FIG. 7 is a schematic diagram of another exemplary leakage-aware activation control circuit that may be provided in the dynamic read circuit of FIG. 2 to generate control signals to control the activation timing of pulses provided to the delay keeper circuit to control the activation timing of the delay keeper circuit based on a comparison of NFET leakage current to PFET leakage current;

FIG. 8A is a circuit diagram of an exemplary NFET leakage circuit that may be used in the leakage-aware activation control circuit in the dynamic read circuit in FIG. 2, wherein the NFET leakage circuit is configured to provide an NFET leakage indicator that indicates leakage current of at least one NFET in the dynamic read circuit;

FIG. 8B is a circuit diagram of an exemplary PFET leakage circuit that may be used in the leakage sense activation control circuit in the dynamic read circuit in FIG. 2, wherein the PFET leakage circuit is configured to provide a PFET leakage indicator indicative of leakage current of at least one PFET in the dynamic read circuit;

FIG. 9 is a logic table illustrating exemplary leakage FET leakage control words generated by the leakage aware activation control circuit in FIG. 6 to control the activation timing of the delay keeper circuit based on various NFET leakage indicator to PFET leakage indicator ratios;

FIG. 10 is a listing of exemplary logic statements of the leakage-aware activation control circuit of FIG. 6 for generating a FET leakage control word to control activation timing of a delay keeper circuit according to the logic table of FIG. 9;

FIG. 11 is a circuit diagram of an exemplary pulse generator configured to receive a generated control signal from the leakage-aware activation control circuit in FIG. 7 to control the activation timing of a delay keeper circuit based on a comparison of an NFET leakage indicator and a PFET leakage indicator; and is

FIG. 12 is a block diagram of an exemplary processor-based system that may include a memory system including a dynamic read circuit that uses a leakage-aware activation control circuit to control the activation timing of a delay keeper circuit in response to a read operation and in accordance with any of the aspects disclosed herein.

Detailed Description

Referring now to the drawings, several exemplary aspects of the disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

FIG. 2 illustrates a memory system 200 that may be included in a processor-based system 202. For example, the processor-based system 202 may be disposed in a system-on-a-chip (SoC) 204. Memory system 200 uses a plurality of memory bit cells 204(1) through 204(N) to store data, where 'N' can be any number of rows of desired memory bit cells 204(1) through 204 (N). Each memory bit cell 204(1) through 204(N) is capable of storing a single bit of information. In FIG. 2, a single column 206 of memory bit cells containing multiple memory bit cells 204(1) through 204(N) is shown. However, it should be noted that a plurality of memory bitcell columns 206 may be disposed in memory system 200 to provide a data array of memory bitcells 204(1) through 204 (N). In this example, using memory bitcell 204(1) as a reference example to indicate each memory bitcell 204(1) through 204(N), memory bitcell 204(1) includes two (2) cross-coupled inverters 208(1), 208(2) (i.e., four (4) transistors) to form storage cells 210(1) through 210(N) and two (2) access transistors 212(1), 212(2) in a six (6) transistor (T) (6-T) complementary memory bitcell arrangement. The two (2) access transistors 212(1), 212(2) are configured to be activated by row word lines WL (1), WL (N) of accessed memory row 1 of memory bit-cells 204(1) through 204(N) to perform read and write operations.

With continued reference to FIG. 2, dynamic read circuitry 214 is provided in the memory system 200 to perform read operations on selected memory bitcells 204(1) through 204 (N). The assertion of a particular word line WL (1) to WL (N) for a given memory row 1 to N controls which memory bit cell 204(1) to 204(N) is read by dynamic read circuit 214 during a read operation. With respect to memory bitcell 204(1), as an example, memory bitcell 204(1) is provided with read port circuitry 216(1) as part of dynamic read circuitry 214 for read operations on memory bitcell 204 (1). Read port circuit 216(1) is an NFET based read port circuit containing two (2) transistors, pull-down NFET 218(1) and read port NFET 218(2) in this example to enable provision of memory bitcell 204(1) as an eight (8) transistor (8-T) memory bitcell. Pull-down NFET 218(1) is activated in response to a read clock signal (read _ clk)220 that is responsive to a read operation. Read port NFET 218(2) is activated based on the voltage (i.e., data) on complementary node 222C being a logic high level, which causes dynamic node 224 of dynamic read circuit 214 to be pulled to Ground (GND). Deactivating the read port NFET 218(2) based on the voltage (i.e., data) on the complementary node 222C being a logic low level causes the dynamic node 224 of the dynamic read circuit 214 to hold its charge at the voltage Vdd. In either case, memory bit cell 204(1) is configured to generate a voltage on dynamic node 224 that should be the voltage on complementary node 222C in response to a read operation. Providing additional pull-down NFET 218(1) and read port NFET 218(2) in read port circuit 216(1) would separate the write performance of memory bit cell 204(1) from the read performance of memory bit cell 204 (1).

During the precharge phase of memory bitcell 204(1), precharge PFET 226 in dynamic read circuit 214 is activated in response to read clock signal (read _ clk)220 being a low logic level indicating that a read operation is inactive. This causes the dynamic node 224 in the dynamic read circuit 214 to precharge to the voltage Vdd. Then, during an evaluation phase in response to the read clock signal (read _ clk)220 being above a logic high level indicating that the read operation is active, the precharge PFET 226 is turned off and the pull-down NFET 218(1) is activated to be coupled to Ground (GND). If the charge on complementary node 222C in memory bit cell 204(1) is a logic '1' (i.e., voltage Vdd) during a read operation, read port NFET 218(2) is activated to pull dynamic node 224 down to Ground (GND). Pulling the dynamic node 224 to Ground (GND) will cause the inverter 230 to generate a logic '1' on the sense node 228. However, when a read operation is activated, the delay keeper circuit 232 disposed in the dynamic read circuit 214, which in this example is a PFET-based delay keeper circuit comprised of PFET 233, is turned off. But then turn on the delay keeper circuit 232 after a design amount of time that is not sensitive to PFET and NFET leakage currents. If the delay keeper circuit 232 turns on too early and its leakage is large relative to the pull-down NFET 218(1) and the read port NFET 218(2) when node 222C is at a logic "1," then the dynamic node 224 will be pulled upward toward the voltage Vdd in contention with the pull-down NFET 218(1) in the read port circuit 216 (1).

To avoid or reduce this contention between the delay keeper circuit 232 on the dynamic node 224 in the memory system 200 in fig. 2 and the pull-down NFET 218(1) in the read port circuit 216(1), a pulse generator 234 is provided as shown in fig. 2. The pulse generator 234 is configured to activate and deactivate the delay keeper circuit 232 in response to the read clock signal (read _ clk)220 to avoid or reduce contention between the delay keeper circuit 232 and the pull-down NFET 218(1) in the read port circuit 216 (1). The pulse generator 234 is configured to generate a pulse 236 in response to a read clock signal (read _ clk)220 indicating a read operation. In this example, the pulse 236 is provided to the gate (G) of the delay keeper circuit 232. Thus, first during the evaluation phase of the dynamic read circuit 214, the pulse generator 234 generates a pulse 236 on the output node 237 to first deactivate the delay keeper circuit 232 to avoid contention with the pull-down NFET 218(1) on the dynamic node 224. In this example, the pulse 236 generated by the pulse generator 234 is an active low pulse because the delay keeper circuit 232 is a PFET that is activated by a lower signal level in this example. The pulse width of pulse 236 is controlled by pulse generator 234 to control deactivation of delay keeper circuit 232 for a desired period of time to allow pull-down NFET 218(1) to perform an evaluation phase on dynamic node 224. Thereafter, during a subsequent hold phase of the dynamic read circuit 214, the pulse 236 expires on the output node 237, which activates the delay keeper circuit 232 to hold the read voltage (i.e., data) on the dynamic node 224.

Thus, as discussed above, the timing control of the pulse generator 234 in the memory system 200 to generate the pulse 236 is critical to avoid or reduce contention between the delay keeper circuit 232 and the pull-down NFET 218(1) in the read port circuit 216 (1). Activation timing control can be designed at design time based on the drive strength of the transistors in the pull-down NFET 218(1) in the delay keeper circuit 232 and read port circuit 216 (1). However, the drive strengths of the transistors in the delay keeper circuit 232 and pull-down NFET 218(1) may differ from the design parameters due to factors such as process variations and technology node scaling. Due to these variations in transistor drive strength, the transistor drive strength of the delay keeper circuit 232 may be stronger than the read port circuit 216(1) is expected to be stronger in design. In this scenario, the pulse generator 234 may delay generating the pulse 236 not long enough to avoid or reduce contention between the delay keeper circuit 232 and the pull-down NFET 218(1) in the read port circuit 216 (1). On the other hand, if the transistor drive strength of the read port circuit 216(1) is stronger than the delay keeper circuit 232 is expected in design, the generation of the pulse 236 by the pulse generator 234 may be delayed too long to avoid or reduce contention between the delay keeper circuit 232 and the pull-down NFET 218(1) in the read port circuit 216 (1).

For example, if complementary node 222C in memory bit cell 204(1) in FIG. 2 had a logic '1' state prior to the read operation, and time T₁Generating the pulse 236 to activate the delay keeper circuit 232 is too early or not delayed enough, as shown in FIG. 3A, then at time T₂The pull-down of dynamic node 224 by pull-down NFET 218(1) is pushed out in time. In this way, prematurely activating the delay keeper circuit 232 can delay the readout of the memory bit cell 204(1) and affect read performance. Additionally, if the complementary node 222C in memory bit cell 204(1) in FIG. 2 has a logic '0' state prior to the read operation, and the activation delay of the delay keeper circuit 232 is too long and the leakage current of the delay keeper circuit 232 is strong, as shown in FIG. 3B, then the dynamic node 224 falls to Ground (GND). This may cause the delay keeper circuit 232 to store a logic '0' instead of a logic '1', thereby causing a logic '1' value to be read out at the sense node 228 instead of the correct logic '0' value.

In this example, the relationship of the delay keeper circuit 232 to the transistor leakage current in the read port circuit 216(1) is identified as shown in diagram 400 of FIG. 4. As shown in graph 400 in fig. 4, as the ratio of NFET leakage current (i.e., drive strength) to PFET leakage current (i.e., drive strength) decreases, the pulse width of pulse 236 needs to be increased to avoid pushing out the pull-down of dynamic node 224 and affecting read performance as discussed above with respect to fig. 3A. However, as shown in graph 400 in fig. 4, as the ratio of NFET leakage current (i.e., drive strength) to PFET leakage current (i.e., drive strength) increases, it is desirable to reduce the pulse width of pulse 236 to activate the delay keeper circuit 232 earlier than the dynamic node 224 falls to Ground (GND) and then read out the erroneous data (logic "1" instead of "0"), as discussed above with respect to fig. 3B.

In this regard, the memory system 200 in fig. 2 includes a leakage aware activation control circuit 238. As will be discussed in more detail below, the leakage-aware activation control circuit 238 is configured to adaptively control the activation timing of the delay keeper circuit 232 based on a comparison of NFET leakage current to PFET leakage current. The leakage aware activation control circuit 238 is configured to generate a control signal 240 to control the activation timing of the pulse width of the pulse 236 generated by the pulse generator 234 based on a comparison of the NFET leakage current to the PFET leakage current. As discussed above, the delay keeper circuit 232 in the memory system 200 in fig. 2 includes a PFET. Read port circuits 216(1) through 216(N) include pull-down NFET 218 (1). The PFET leakage current and the NFET leakage current relate to their respective transistor drive strengths. Thus, the leakage-aware activation control circuit 238 is configured to adaptively control the activation timing of the delay keeper circuit 232 based on a comparison of NFET leakage current to PFET leakage current. Accordingly, adjustments to the pulse width of the pulse 236 may be made during operation to account for variations in transistor drive strength due to variations in the design and/or fabrication of NFET and PFET transistors in the memory system 200 to allow the dynamic read circuit 214 to more accurately provide read data from the memory bitcells 204(1) through 204 (N).

In this regard, fig. 5 is a schematic diagram of a leakage-aware activation control circuit 238 disposed in the memory system 200 in fig. 2 to adaptively control the activation timing of the delay keeper circuit 232 based on a comparison of NFET leakage current to PFET leakage current. As shown in fig. 5, the leakage-aware activation control circuit 238 includes a PFET leakage circuit 500 configured to provide a PFET leakage indicator 502 indicative of a leakage current of at least one PFET in the dynamic read circuit 214. For example, the PFET leakage circuit 500 may include one or more PFETs, which in this example are located in the same Integrated Circuit (IC) and/or area of the IC as the delay keeper circuit 232 of the memory system 200, to provide a PFET leakage indicator 502 that provides an indication of PFET leakage current in the delay keeper circuit 232. The PFET leakage circuit 500 may also be configured to provide a PFET leakage indicator 502 during operation of the dynamic read circuit 214 if it is desired to measure a PFET leakage current that the dynamic read circuit 214 may experience during operation. In addition, the leakage-aware activation control circuit 238 also includes an NFET leakage circuit 504 configured to provide an NFET leakage indicator 506 that provides an indication of NFET leakage current of at least one NFET in the dynamic read circuit 214. Also, the NFET leakage circuit 504 may include one or more NFETs, which in this example are located in the same IC and/or region of the IC as the read port circuits 216(1) -216 (N) of the memory system 200, to provide an NFET leakage indicator 506 that provides an indication of NFET leakage current in the read port circuits 216(1) -216 (N). The NFET leakage circuit 504 can also be configured to provide an NFET leakage indicator 506 during operation of the dynamic read circuit 214 if it is desired to measure NFET leakage current that the dynamic read circuit 214 can experience during operation.

With continued reference to fig. 5, the leakage-aware activation control circuit 238 also includes a comparator circuit 508. The comparator circuit 508 is configured to receive the PFET leakage indicator 502 and the NFET leakage indicator 506 and compare the PFET leakage indicator 502 with the NFET leakage indicator 506. The comparator circuit 508 is configured to generate a FET leakage signal 510 based on a comparison of the NFET leakage indicator 502 and the PFET leakage indicator 506. The FET leakage signal 510 is provided to a control signal generator 512 configured to adaptively generate the control signal 240 based on the FET leakage signal 510 to control the activation timing of the delay keeper circuit 232. As discussed above, in this example, the control signal 240 controls the activation timing of the pulse 236 generated by the pulse generator 234, as shown in fig. 5, to control the activation timing of the delay keeper circuit 232 in this example. It should be noted that the pulse generator 234 is not required. The leakage aware activation control circuit 238 may be configured to generate and provide a control signal 240 directly to the delay keeper circuit 232 to control the timing of the activation of the delay keeper circuit 232.

The ratio of leakage currents of NFET to PFET may vary based on design and manufacturing process. Accordingly, it may be desirable to provide a leakage-aware activation control circuit 238 that has the ability to generate control signals based on various operating speed conditions of NFET-to-PFET leakage current. For example, PFETs and/or NFETs may differ from their nominal (expected) behavior and switching speed, and may operate at relatively slower or faster switching speeds depending on manufacturing process variations that affect voltage and temperature variations within the IC (in the case of circuit simulations, the slow corner represents the slowest expected behavior of the device, the nominal corner represents the average expected behavior, and the fast corner represents the fastest expected behavior). Such variations in the fabrication process affect the leakage current of NFETs and PFETs. Furthermore, PFETs may vary in a different manner than NFETs due to the manufacturing process and thus may experience different switching speed variations than NFETs, and vice versa. For example, a fabricated PFET may be a slower device, while a fabricated NFET may be a faster device. Leakage current of PFETs and NFETs is related to switching speed, with faster devices having larger leakage currents. Thus, because of these switching speed differences that can occur in fabricated PFETs and NFETs, the leakage sense activation control circuit 238 may need to take into account the relative switching speeds of the PFETs and NFETs when determining how to control the activation timing of the delay keeper circuit 232.

FIG. 6 is a flow diagram generally illustrating an exemplary process 600 in which the leakage-aware activation control circuit 238 in FIG. 2 controls the activation timing of the delay keeper circuit 232 in the dynamic read circuit 214. As shown therein, the process 600 determines a PFET leakage current of at least one PFET in the dynamic read circuit 214 (block 602). The process 600 also includes determining the NFET leakage current of at least the NFET of the dynamic read circuit 214 (block 604). The determined leakage current of at least one NFET is compared to the determined leakage current of at least one PFET (block 606). At least one control signal 240 for the delay keeper circuit 232 is adaptively generated based on a comparison of the determined leakage current of the at least one NFET and the determined leakage current of the at least one PFET (block 608). The process 600 may also include controlling activation timing of the delay keeper circuit 232 in the dynamic read circuit 214 for the memory bit cells 204(1) -204 (N) based on the at least one control signal 240 (block 610).

FIG. 7 is a schematic diagram of another exemplary leakage-aware activation control circuit 700 that may be disposed in the dynamic read circuit 214 in FIG. 2. As discussed below, the leakage-aware activation control circuit 700 is configured to generate a control signal 240(1) that may be used to control the timing at which the pulse generator 234 generates the pulse 236 to the activation timing of the delay keeper circuit 232 in fig. 2 based on a comparison of NFET leakage current to PFET leakage current. In this regard, a PFET leakage circuit 702 and an NFET leakage circuit 704 are provided to determine PFET and NFET leakage currents, respectively. In this example, the PFET leakage circuit 702 includes a PFET leakage sensor 706 configured to sense a leakage current of the PFET. Similarly, the NFET leakage circuit 704 includes an NFET leakage sensor 708 configured to sense leakage current of the NFET. As discussed above, the PFET leakage sensor 706 and/or the NFET leakage sensor 708 may be disposed in the same circuit or region of the IC containing the dynamic read circuit 214 in fig. 2 such that the determined leakage current of the PFET and/or NFET is indicative of the leakage current of the PFET and/or NFET in the dynamic read circuit 214.

With continued reference to fig. 7, the PFET leakage circuit 702 and the NFET leakage circuit 704 also contain a PFET leakage frequency counter 710 and an NFET leakage frequency counter 712, respectively. The PFET leakage frequency counter 710 and the NFET leakage frequency counter 712 are configured to store a PFET leakage frequency count 714 and an NFET leakage frequency count 716 that indicate leakage currents of the PFET and NFET, respectively. The PFET leakage sensor 706 and the NFET leakage sensor 708 are configured to update a PFET leakage frequency count 714 and an NFET leakage frequency count 716 in respective PFET leakage frequency counters 710 and NFET leakage frequency counters 712 as a function of the determined leakage currents of the PFET and NFET, respectively. For example, an example of the PFET leakage circuit 702 in fig. 7 is provided as PFET leakage circuit 702(1) in fig. 8A. As illustrated therein, a PFET leakage sensor 706(1) is provided that is comprised of a PFET 800. The gate (G) of the PFET 800 is tied to cause the PFET 800 to be turned off or deactivated. Thus, any PFET leakage current I_PPFET leakage frequency counter 710(1) is provided as from PFETLeakage current of 800. PFET leakage current I_PA series of gates (G) coupled to NFETs 802(1) to 802(P) in a PFET ring oscillator circuit 804 in a PFET leakage circuit 702 (1). NFETs 802(1) -802 (P) are each configured to control activation of a respective buffer circuit 806(1) -806 (P) configured in a tank 808 in PFET ring oscillator circuit 804. Thus, PFET leakage current I_PControls the on-strength of NFETs 802(1) through 802(P) in PFET ring oscillator circuit 804, which in turn controls the speed or oscillation of buffer circuits 806(1) through 806(P) to provide an indication of PFET leakage current. For example, if provided, each iteration of the tank 808 may be used to increment a PFET leakage frequency count, such as PFET leakage frequency count 714 in fig. 7.

Similarly, an example of the NFET leakage circuit 704 in fig. 7 is provided as the NFET leakage circuit 704(1) in fig. 8B. As illustrated therein, an NFET leakage sensor 708(1) is provided that is comprised of an NFET 810 and a PFET current mirror 811. The gate (G) of NFET 810 is tied to Ground (GND) so that NFET 810 is turned off or deactivated. Thus, any NFET leakage current is provided to NFET leakage frequency counter 712(1) as leakage current from NFET 810. NFET leakage Current I_NA series of gates (G) coupled to NFETs 812(1) through 812(Q) in NFET ring oscillator circuit 814 in NFET leakage circuit 704 (1). NFETs 812(1) -812 (Q) are each configured to control activation of a respective buffer circuit 816(1) -816 (Q) configured in tank 818. Thus, NFET leakage Current I_NControls the turn-on strength of NFETs 812(1) through 812(Q) in NFET ring oscillator circuit 814, which in turn controls the speed or oscillation of buffer circuits 816(1) through 816(Q) to provide an indication of NFET leakage current. For example, provided that each iteration of tank 818 may be used to increment an NFET leakage frequency count, such as NFET leakage frequency count 716 in fig. 7.

Referring back to the leakage-aware activation control circuit 700 in fig. 7, a comparator circuit 718 configured to compare PFET leakage current to NFET leakage current is provided. In this example, the comparator circuit 718 receives a PFET leakage frequency count 714 and an NFET leakage frequency count 716 from the respective PFET leakage circuit 702 and NFET leakage circuit 704, respectively, as indications of PFET to NFET leakage current. The comparator circuit 718 is composed of a plurality of comparators 720(1) to 720 (C). Each comparator 720(1) -720 (C) is configured to make certain comparisons based on PFET leakage current and/or NFET leakage current to generate respective FET leakage signals 722(1) -722 (C) to provide FET leakage control signals 724 that indicate ratios of PFET leakage current and/or NFET leakage current. As discussed below, by providing a plurality of comparators 720(1) -720 (C), the comparators 720(1) -720 (C) may each be configured to determine whether PFET leakage current and/or NFET leakage current indicate slow, nominal (typical), or fast leakage current in a different manner. In this manner, the FET leakage signals 722(1) -722 (C) may combine to form a FET leakage control signal 724 to enable more precise control of a delay keeper circuit, such as the delay keeper circuit 232 in fig. 2, based on relative PFET and NFET leakage currents and the speed of the PFET and NFET devices.

In this regard, in this example, the comparator circuit 718 in the leakage sensing activation control circuit 700 in fig. 7 includes six (6) comparators 720(1) through 720 (6). Comparator 720(3) is configured as a PFET nominal leakage comparator circuit configured to compare a PFET leakage frequency count 714 with an NFET leakage frequency count 716 to indicate whether the PFET has a greater leakage current than the NFET. If so, comparator 720(3) generates FET leakage signal 722(3) with this indication. Similarly, comparator 720(4) is configured as an NFET nominal leakage comparator circuit configured to compare NFET leakage frequency count 716 to PFET leakage frequency count 714 to indicate whether the NFET has a larger leakage current than the PFET. If so, comparator 720(4) generates FET leakage signal 722(4) with this indication.

In addition, comparator 720(1) is configured as a PFET slow leakage comparator circuit configured to compare the PFET leakage frequency count 714 with a predefined slow leakage indicator 726 (or limit). The comparator 720(2) is configured as an NFET slow leakage comparator circuit configured to compare the NFET leakage frequency count 716 with a predefined slow leakage indicator 726 (or limit). In this manner, the comparators 720(1), 720(2) may provide FET leakage signals 722(1), 722(2), respectively, indicating whether the determined leakage currents of the PFET and NFET, respectively, indicate slow devices. In addition, comparator 720(5) is configured as a PFET fast leakage comparator circuit configured to compare the PFET leakage frequency count 714 with a predefined fast leakage indicator 728 (or limit). The comparator 720(6) is configured as an NFET fast leakage comparator circuit configured to compare the NFET leakage frequency count 716 with a predefined fast leakage indicator 728 (or limit). In this manner, the comparators 720(5), 720(6) may provide FET leakage signals 722(5), 722(6), respectively, indicating whether the determined leakage currents of the PFET and NFET, respectively, are indicative of a fast device.

Thus, through FET leakage signals 722(1) through 722(6), comparator circuit 718 provides an indication of PFET leakage current to NFET leakage current, and whether the PFET and NFET are slow, nominal, or fast switching speed devices. The FET leakage signals 722(1) -722 (6) form a FET leakage control signal 724. Decoder circuit 730 is provided in leakage-aware activation control circuit 700 to decode FET leakage control signal 724 into FET leakage control word 732 as a control signal, which in this example is eight (8) bits (<7:0>), as will be explained below. The FET leakage control word 732 may be provided to the pulse generator 234 to control the timing of the generation of the pulse 236 and the delay keeper circuit 232 in the dynamic read circuit 214 in fig. 2, as previously discussed above.

Fig. 9 is a logic table 900 illustrating an exemplary leakage FET leakage control word generated by the leakage sense activation control circuit 700 in fig. 7 to control the activation timing of the delay keeper circuit 232 based on the FET leakage signals 722(1) -722 (6) provided by the comparator circuit 718. The process column 902 shows various possible combinations of fast, slow, and nominal PFET and NFET devices in this example. Prog <0> to Prog <7> columns 904 illustrate the value of a bit in FET leakage control word 732 based on the combination of fast, slow, and nominal PFET and NFET devices. Pulse width column 906 illustrates the pulse width setting of pulse 236 generated by pulse generator 234 in response to FET leakage control word 732. For example, a fast NFET leakage current (i.e., above a predefined fast leakage indicator) and a slow PFET leakage current (i.e., below a predefined slow leakage indicator) are shown as "minimum" pulse width settings indicative of the pulse 236 used for activation timing control of the delay keeper circuit 232. The slow NFET leakage current (i.e., above the predefined fast leakage indicator) and the slow PFET leakage current (i.e., below the predefined slow leakage indicator) are shown to indicate the "maximum" pulse width setting of the pulse 236 for activation timing control of the delay keeper circuit 232. Fig. 10 is a diagram 1000 of exemplary equations for Prog <0> to Prog <7> bits of FET leakage control word 732 generated by decoder circuit 730 of comparator circuit 718 in fig. 7 and as shown in logic table 900 in fig. 9.

Fig. 11 is a circuit diagram of an exemplary pulse generator 234(1) that may be used as the pulse generator 234 in fig. 7 to receive a FET leakage control word 732 from the leakage-aware activation control circuit 700 to control the activation timing of the delay keeper circuit 232 based on a comparison of an NFET leakage indicator and a PFET leakage indicator. As shown in fig. 11, pulse generator 234(1) contains a multiplexer circuit 1100. FET leakage control word 732 selects signal paths 1104(0) through 1104(7) provided by multiplexer circuit 1100 to output 1102 for use by enable pulse generator 234 to generate pulse 236(1) to be provided to delay keeper circuit 232. Each signal path 1104(1) -1104 (7) contains a different number of buffer circuits 1106 configured to delay the received read clock signal (read _ clk)220 based on the number of buffer circuits 1106 disposed in the respective signal path 1104(0) -1104 (7). Signal path 1104(0) is directly coupled to sense node 228. The delayed read clock signal (read _ clk)220D, which is dependent on the signal path 1104(0) selected by the FET leakage control word 732 and 1104(7), is provided to an and gate 1108 gated and anded by the undelayed read clock signal (read _ clk)220 to generate a pulse 236(1) to control the activation timing of the delay keeper circuit 232.

It should be noted that while aspects herein are described with reference to a circuit that uses a pre-charge and then a discharge evaluation mode, a circuit that uses a pre-discharge and then a discharge evaluation is within the scope of the present disclosure. For example, referring to memory system 200 in FIG. 2 as an example, if the delay keeper circuit 232 uses an NFET and the read port circuit 216(1) uses a PFET for the evaluation phase of the dynamic read circuit 214, one of ordinary skill in the art will readily understand how to adjust the concepts herein to apply to such a circuit. In this example, the pulse generator 234 may be configured to generate an active low pulse from the output node 237 to control activation and deactivation of the delay keeper circuit 232.

The leakage aware activation control circuit disclosed herein to prevent or mitigate read port circuitry in the delay keeper circuit and dynamic read circuit from performing read operations in memory bit cells according to aspects disclosed herein may be provided in or integrated into a memory in any processor-based device. Examples include, but are not limited to, set top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile phones, cellular phones, smart phones, tablets, phablets, servers, computers, portable computers, desktop computers, Personal Digital Assistants (PDAs), monitors, computer displays, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, Digital Video Disc (DVD) players, portable digital video players, and automobiles.

In this regard, fig. 12 illustrates an example of a processor-based system 1200. Any component or circuit of the processor-based system 1200 may perform a read operation in a memory bitcell according to aspects disclosed herein using a leakage aware activation control circuit to prevent or mitigate contention between a delayer circuit and a read port circuit in a dynamic read circuit. In this example, the processor-based system 1200 includes one or more Central Processing Units (CPUs) 1202 that each include one or more processors 1204. The CPU 1202 may have a cache 1206 coupled to the processor 1204 for fast access to temporarily stored data. As an example, the cache 1206 may use any of the leakage-aware activation control circuits 1208 disclosed herein, including the leakage-aware activation control circuit 238 in fig. 2 and the leakage-aware activation control circuit 700 in fig. 7.

With continued reference to FIG. 12, 1202 is coupled to a system bus 1210 and may couple master and slave devices included in the processor-based system 1200 to each other. As is well known, the CPU 1202 communicates with these other devices by exchanging address, control, and data information over the system bus 1210. For example, as an example of a slave device, the CPU 1202 may communicate a bus transaction request to a memory controller 1212 in the memory system 1214. Although not illustrated in fig. 12, a plurality of system buses 1210 may be provided, wherein each system bus 1210 constitutes a different fabric. In this example, the memory controller 1212 is configured to provide memory access requests to a memory array 1216 in the memory system 1214. As an example, the memory array 1216 may use any of the leakage aware activation control circuits 1208 disclosed herein, including the leakage aware activation control circuit 238 in fig. 2 and the leakage aware activation control circuit 700 in fig. 7.

Other devices may be connected to the system bus 1210. As illustrated in fig. 12, these devices can include a memory system 1214, one or more input devices 1220, one or more output devices 1222, one or more network interface devices 1224, and one or more display controllers 1226, as examples. Input device 1220 may include any type of input device including, but not limited to, input keys, switches, a speech processor, etc. The output devices 1222 may include any type of output device including, but not limited to, audio, video, other visual indicators, and the like. Network interface device 1224 may be any device configured to allow data to be exchanged to and from network 1228. Network 1228 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a Local Area Network (LAN), a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), BLUETOOTH, a wireless LAN, a wireless network, a wireless LAN, a wireless network, a^TMNetworks and the internet. The network interface device 1224 may be configured to support any type of communications protocol desired.

The CPU 1202 also may be configured to access a display controller 1226 over the system bus 1210 to control information sent to one or more displays 1230. The display controller 1226 sends information to the display 1230 for display by one or more video processors 1232, which process the information to be displayed in a format suitable for the display 1230. Display 1230 may include any type of display including, but not limited to, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), a plasma display, and the like.

It should be noted that the use of PFETs and NFETs in the present disclosure may include PMOSFETs and NMOSFETs that are Metal Oxide Semiconductor (MOS) devices. PFETs and NFETs discussed herein may include other types of oxide layers in addition to metals.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or combinations of both. As an example, the master and slave devices described herein may be used in any circuit, hardware component, Integrated Circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information as desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design options, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with: a Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in a number of different sequences other than the illustrated sequences. Further, operations described in a single operational step may actually be performed in many different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow diagrams may be subject to a number of different modifications, as will be readily apparent to those skilled in the art. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (30)

1. A leakage-aware activation control circuit for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bit cell, comprising:

an NFET leakage circuit configured to provide an NFET leakage indicator indicative of leakage current of at least one NFET in a dynamic read circuit;

a PFET leakage circuit configured to provide a PFET leakage indicator indicative of a leakage current of at least one PFET in the dynamic read circuit;

a comparator circuit configured to:

receiving the NFET leakage indicator and the PFET leakage indicator;

comparing the NFET leakage indicator to the PFET leakage indicator; and

generating a FET leakage signal based on a comparison of the NFET leakage indicator and the PFET leakage indicator; and

a control signal generator configured to adaptively generate at least one control signal to control activation timing of a delay keeper circuit based on the FET leakage signal.

2. The leakage aware activation control circuit of claim 1, wherein:

the NFET leakage circuit is configured to dynamically provide the NFET leakage indicator indicative of the leakage current of the at least one NFET in the dynamic read circuit during operation of the dynamic read circuit; and is

The PFET leakage circuit is configured to dynamically provide the PFET leakage indicator indicative of the leakage current of the at least one PFET in the dynamic read circuit during operation of the dynamic read circuit.

3. The leakage aware activation control circuit of claim 1, wherein:

the NFET leakage circuit comprises an NFET leakage sensor configured to determine NFET leakage;

the NFET leakage sensor is configured to provide the NFET leakage indicator indicative of the leakage current of the at least one NFET based on the determined NFET leakage in the dynamic read circuit; and the PFET leakage circuit comprises a PFET leakage sensor configured to determine PFET leakage;

the PFET leakage sensor is configured to provide the PFET leakage indicator indicative of the leakage current of the at least one PFET based on the determined PFET leakage in the dynamic read circuit.

4. The leakage aware activation control circuit of claim 3, wherein:

the NFET leakage sensor is comprised of at least one deactivated NFET configured to provide an NFET leakage current indicative of the leakage current of the at least one NFET; and is

The PFET leakage sensor is comprised of at least one deactivated NFET configured to provide a PFET leakage current indicative of the leakage current of the at least one PFET.

5. The leakage aware activation control circuit of claim 4, wherein:

the NFET leakage sensor is further comprised of an NFET ring oscillator circuit comprising a plurality of first buffer circuits coupled together in a ring oscillator, each of the plurality of first buffer circuits configured to be activated by the NFET leakage current from the at least one deactivated NFET indicative of the leakage current of the at least one NFET, the NFET ring oscillator circuit configured to update the NFET leakage indicator based on the provided NFET leakage current; and is

The PFET leakage sensor further consists of a PFET ring oscillator circuit comprising a plurality of second buffer circuits coupled together in a ring oscillator, each of the plurality of second buffer circuits configured to be activated by the PFET leakage current from the at least one deactivated PFET indicative of the leakage current of the at least one PFET, the PFET ring oscillator circuit configured to update the PFET leakage indicator based on the provided PFET leakage current.

6. The leakage aware activation control circuit of claim 1, wherein:

the NFET leakage circuit further comprises an NFET leakage frequency counter configured to store an NFET leakage frequency count;

the NFET leakage circuit is configured to control the NFET leakage frequency counter to update the NFET leakage frequency count as a function of the determined leakage current of the at least one NFET; and is

The PFET leakage circuit further comprises a PFET leakage frequency counter configured to store a PFET leakage frequency count;

the PFET leakage circuit is configured to control the PFET leakage frequency counter to update the PFET leakage frequency count as a function of the determined leakage current of the at least one PFET.

7. The leakage aware activation control circuit of claim 1, wherein:

the comparator circuit is configured to generate the FET leakage signal comprising a FET leakage control signal based on a comparison of the NFET leakage indicator and the PFET leakage indicator; and is

The control signal generator is configured to adaptively generate the at least one control signal comprising a FET leakage control word to control the activation timing of the delay keeper circuit based on the FET leakage control signal.

8. The leakage aware activation control circuit of claim 7, wherein the comparator circuit comprises:

at least one PFET leakage comparator circuit configured to:

receiving the NFET leakage indicator and the PFET leakage indicator;

comparing the NFET leakage indicator to the PFET leakage indicator; and

controlling the FET leakage control signal to indicate whether the leakage current of the at least one PFET exceeds the leakage current of the at least one NFET based on a comparison of the NFET leakage indicator and the PFET leakage indicator; and

at least one NFET leakage comparator circuit configured to:

receiving the NFET leakage indicator and the PFET leakage indicator;

comparing the NFET leakage indicator to the PFET leakage indicator; and

controlling the FET leakage control signal to indicate whether the leakage current of the at least one NFET exceeds the leakage current of the at least one PFET based on a comparison of the NFET leakage indicator and the PFET leakage indicator.

9. The leakage aware activation control circuit of claim 8, wherein the comparator circuit further comprises:

at least one PFET slow leakage comparator circuit configured to:

receiving the PFET leakage indicator;

receiving a predefined PFET slow leakage indicator indicating a PFET slow leakage limit;

comparing the predefined PFET leakage indicator to the predefined PFET slow leakage indicator; and

controlling the FET leakage control signal to indicate a PFET slow leakage current if the leakage current of the at least one PFET is less than the PFET slow leakage limit based on a comparison of the PFET leakage indicator to the predefined PFET slow leakage indicator; and

at least one NFET slow leakage comparator circuit configured to:

receiving the NFET leakage indicator;

receiving a predefined NFET slow leakage indicator indicative of an NFET slow leakage limit;

comparing the predefined NFET leakage indicator to the predefined NFET slow leakage indicator; and

based on a comparison of the NFET leakage indicator and the predefined NFET slow leakage indicator, controlling the FET leakage control signal to indicate NFET slow leakage current if the leakage current of the at least one NFET is less than the NFET slow leakage limit.

10. The leakage aware activation control circuit of claim 8, wherein the comparator circuit further comprises:

at least one fast PFET leakage comparator circuit configured to:

receiving the PFET leakage indicator;

receiving a predefined PFET fast leakage indicator indicating a PFET fast leakage limit;

comparing the predefined PFET leakage indicator to the predefined PFET fast leakage indicator; and

controlling the FET leakage control signal to indicate a PFET fast leakage current if the leakage current of the at least one PFET is greater than the PFET fast leakage limit based on a comparison of the PFET leakage indicator to the predefined PFET fast leakage indicator; and

at least one NFET fast leakage comparator circuit configured to:

receiving the NFET leakage indicator;

receiving a predefined NFET fast leakage indicator indicative of an NFET fast leakage limit;

comparing the predefined NFET leakage indicator to the predefined NFET fast leakage indicator; and

based on a comparison of the NFET leakage indicator and the predefined NFET fast leakage indicator, controlling the FET leakage control signal to indicate NFET fast leakage current if the leakage current of the at least one NFET is greater than the NFET fast leakage limit.

11. The leakage aware activation control circuit of claim 7, wherein the control signal generator comprises a decoder circuit configured to decode the FET leakage control signal into the FET leakage control word to control the activation timing of the delay keeper circuit.

12. The leakage aware activation control circuit of claim 1, wherein the control signal generator is configured to adaptively generate the at least one control signal based on a control timing of a pulse width of a pulse generated by a pulse generator configured to control the activation timing of the delay keeper circuit based on a comparison of the NFET leakage indicator and the PFET leakage indicator.

13. The leakage aware activation control circuit of claim 1, integrated into a system on a chip (SoC).

14. The leakage aware activation control circuit of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular telephone; a smart phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a desktop computer; a Personal Digital Assistant (PDA); a monitor; a computer display; a television set; a tuner; a radio; a satellite radio; a digital music player; a portable music player; a digital video player; a video player; a Digital Video Disc (DVD) player; a portable digital video player; and automobiles.

15. A leakage-aware activation control circuit for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bit cell, comprising:

means for providing an NFET leakage indicator indicative of leakage current of at least one N-type field effect transistor (NFET) in a dynamic read circuit;

means for providing a PFET leakage indicator indicative of a leakage current of at least one P-type FET PFET in the dynamic read circuit;

means for receiving the NFET leakage indicator and the PFET leakage indicator;

means for comparing the NFET leakage indicator to the PFET leakage indicator;

means for generating a FET leakage signal based on a comparison of the NFET leakage indicator and the PFET leakage indicator; and

means for adaptively generating at least one control signal to control activation timing of a delay keeper circuit based on the FET leakage signal.

16. A method for controlling activation of a delay keeper circuit in a dynamic read circuit for a memory bit cell, comprising:

determining a leakage current of at least one NFET in a dynamic read circuit;

determining a leakage current of at least one P-type FET PFET in the dynamic read circuit;

comparing the determined leakage current of at least one NFET with the determined leakage current of the at least one PFET;

adaptively generating at least one control signal for a delay keeper circuit based on a comparison of the determined leakage current of at least one NFET and the determined leakage current of the at least one PFET.

17. The method of claim 16, further comprising controlling activation timing of the delay keeper circuit in a dynamic read circuit for a memory bit cell based on the at least one control signal.

18. The method of claim 16, wherein:

determining the leakage current of the at least one NFET in the dynamic read circuit comprises: dynamically determining the leakage current of the at least one NFET in the dynamic read circuit during operation of the dynamic read circuit; and is

Determining the leakage current of the at least one PFET in the dynamic read circuit comprises: dynamically determining the leakage current of the at least one PFET in the dynamic read circuit during operation of the dynamic read circuit.

19. The method of claim 16, wherein:

determining the leakage current of the at least one NFET in the dynamic read circuit comprises determining a leakage current through at least one deactivated NFET; and is

Determining the leakage current of the at least one NFET in the dynamic read circuit comprises determining a leakage current through at least one deactivated NFET.

20. The method of claim 16, wherein:

determining the leakage current of the at least one NFET in the dynamic read circuit comprises: generating an NFET leakage frequency count indicative of the leakage current of the at least one NFET in the dynamic read circuit; and is

Determining the leakage current of the at least one PFET in the dynamic read circuit comprises: generating a PFET leakage frequency count indicative of the leakage current of the at least one PFET in the dynamic read circuit.

21. The method of claim 16, wherein:

generating a FET leakage signal comprises generating a FET leakage control signal based on a comparison of the determined leakage current of the at least one NFET and the determined leakage current of the at least one PFET; and is

Adaptively generating the at least one control signal comprises adaptively generating a FET leakage control word based on the FET leakage control signal.

22. The method of claim 21, wherein adaptively generating the at least one control signal comprises adaptively generating the at least one control signal based on whether the determined leakage current of the at least one PFET exceeds the determined leakage current of the at least one NFET.

23. The method of claim 22, further comprising:

comparing the determined leakage current of the at least one PFET to a predefined PFET slow leakage indicator;

adaptively generating the at least one control signal to indicate a PFET slow leakage current if the leakage current of the at least one PFET is less than a PFET slow leakage limit;

comparing the determined leakage current of the at least one NFET to a predefined NFET slow leakage indicator;

and

adaptively generating the at least one control signal to indicate NFET slow leakage current if the leakage current of the at least one NFET is less than an NFET slow leakage limit.

24. The method of claim 22, further comprising:

comparing the determined leakage current of the at least one PFET to a predefined PFET fast leakage indicator;

adaptively generating the at least one control signal to indicate a PFET fast leakage current if the leakage current of the at least one PFET is greater than a PFET fast leakage limit;

comparing the determined leakage current of the at least one NFET to a predefined NFET fast leakage indicator;

and

adaptively generating the at least one control signal to indicate an NFET fast leakage current if the leakage current of the at least one NFET is greater than an NFET fast leakage limit.

25. The method of claim 21, further comprising decoding the FET leakage control signal into the FET leakage control word, and comprising:

controlling activation timing of the delay keeper circuit in the dynamic read circuit for the memory bit cell based on the FET leakage control word.

26. The method of claim 16, comprising adaptively generating the at least one control signal based on a control timing of a pulse width of a pulse generated by a pulse generator configured to control an activation timing of the delay keeper circuit based on a comparison of the determined leakage current of the at least one NFET and the determined leakage current of the at least one PFET.

27. A memory system, comprising:

a memory bitcell, comprising:

a storage circuit configured to store complementary voltages; and

a read port circuit coupled to the storage circuit, the read port circuit configured to generate the complementary voltage on a dynamic node in response to a read operation;

a dynamic read circuit, comprising:

the dynamic node;

a delay keeper circuit configured to be activated in response to a pulse holding the complementary voltage on the dynamic node outside of an evaluation phase and configured to be deactivated in response to the pulse in response to the evaluation phase of the read operation;

a leakage aware activation control circuit, comprising:

a leakage circuit configured to generate a FET leakage signal based on a comparison of a leakage current of at least one N-type FET NFET and a leakage current of at least one P-type FET PFET; and

a control signal generator configured to adaptively generate at least one control signal to control activation timing of a second delay keeper circuit based on the FET leakage signal; and

a pulse generator configured to generate the pulse having a pulse width based on a control activation timing for activation and deactivation of the second delay keeper circuit in response to the at least one control signal.

28. The memory system of claim 27, wherein the read port circuit is comprised of an NFET based read port circuit and the delay keeper circuit is comprised of a PFET based delay keeper circuit.

29. The memory system of claim 27, wherein the read port circuit is comprised of a PFET-based read port circuit and the delay keeper circuit is comprised of an NFET-based delay keeper circuit.

30. The memory system of claim 27, wherein:

the control signal generator is configured to adaptively generate the at least one control signal comprising a FET leakage control word based on the FET leakage signal to control the activation timing of the second delay keeper circuit; and is

The pulse generator includes:

a plurality of delay circuits, each configured to receive a read clock signal in response to a read operation, each delay circuit among the plurality of delay circuits corresponding to a leakage control setting of the FET leakage control word; and

a selector circuit configured to select a delay circuit that controls a pulse width of a generated pulse from among the plurality of delay circuits based on the leakage control setting of the FET leakage control word.

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