CN208819882U - Array of capacitors and semiconductor devices - Google Patents
Array of capacitors and semiconductor devices Download PDFInfo
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- CN208819882U CN208819882U CN201821602797.2U CN201821602797U CN208819882U CN 208819882 U CN208819882 U CN 208819882U CN 201821602797 U CN201821602797 U CN 201821602797U CN 208819882 U CN208819882 U CN 208819882U
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Abstract
The utility model provides a kind of array of capacitors and semiconductor devices; under being formed in substrate devices area after electrode, supporting layer and top electrode; by forming an oxide layer in top electrode; to form a flat capacitor array boundary in device area edge; and increase protective layer on capacitor array boundary; the short circuit problem that crack in turn results in is formed when effectively having evaded subsequent deposition packing material due to the out-of-flatness of capacitor array boundary, improves the reliability of capacitor element.
Description
Technical field
The utility model relates to technical field of semiconductors, in particular to a kind of array of capacitors and a kind of semiconductor devices.
Background technique
With the continuous development of semiconductor technology, also increasingly to the performance requirement of capacitor in semiconductor integrated circuit
Height, for example, it is desirable to which bigger capacitor can be had by being formed by capacitor in limited area.A solution is to lead to
The height for increasing the lower electrode in capacitor is crossed, to increase lower contact area between electrode and capacitor dielectric layer, to make institute
The capacitor of formation has biggish capacitor.
However, so that the depth-width ratio of lower electrode also increases accordingly, and then easily causing with the increase of lower electrode height
The problem of lower electrode bending deforms or collapses, impacts array region reliability.Connected at present by adding the transverse direction of electrode
Continuous supporting layer increases stability, but such continuous supporting layer will form the capacitor array boundary of out-of-flatness, and subsequent deposition is filled out
It is easy to form crack in capacitor array boundary when filling material, causes plug and the short circuit of capacitor array boundary.Therefore, to capacitor battle array
Column boundary carries out protection and is necessary.
Utility model content
The purpose of this utility model is to provide a kind of array of capacitors and semiconductor devices, avoid in depositing filler material
When capacitor array boundary formed crack and caused by short circuit problem, and then improve capacitor reliability.
In order to solve the above technical problems,
The utility model provides a kind of array of capacitors, comprising:
One substrate, the device region for being used to form capacitor with one in the substrate；
Electrode once is arranged in the substrate devices area, and the lower electrode has multiple tubular structures；
One supporting layer, the supporting layer connect the outer wall of the lower electrode tubular structure and along being parallel to substrate surface
Direction extends；
One capacitor dielectric layer, the capacitor dielectric layer are set to the surfaces externally and internally and the supporting layer of the lower electrode
Surface；
One top electrode, the top electrode are set to the surfaces externally and internally of the capacitor dielectric layer, wherein in device region margin location
It sets, the top electrode is corresponded to the part of the supporting layer and protruded with the direction far from the lower electrode, and device region margin location is made
The lateral surface for the capacitor set has concave-convex side structure；
One oxide layer, is set to the outer surface of the top electrode, and the oxide layer fills the bumps of the capacitor
Gap in side structure, the section of the side of the oxide layer, the section of the top electrode and the capacitor dielectric layer is one
In plane, a flat capacitor array boundary is constituted in the device region marginal position；And
One protective layer, the protective layer are set to the capacitor array boundary.
Preferably, the base that the protective layer also covers the upper surface of the oxide layer and do not covered by the oxide layer
Bottom.
Preferably, also there is the external zones positioned at the device region periphery, the protective layer is located at described in the substrate
In device region.
Preferably, the supporting layer includes a top support layer and an at least middle support layer, wherein the top layer support
Layer is set to the mouth periphery of the lower electrode, and the middle support layer is set to the intermediate position of the lower electrode.
Preferably, top electrode filled layer and top electrode articulamentum are additionally provided between the top electrode and the oxide layer,
The top electrode filled layer covers the outer surface of the top electrode and fills the gap between the top electrode；
The top electrode articulamentum covers the outer surface of the top electrode filled layer, and the oxide layer covers the top electrode
The outer surface of articulamentum；
Wherein, the top electrode filled layer and the top electrode articulamentum all have concave-convex side structure, the bumps side
Face structure corresponds to the supporting layer outside the lower electrode tubular structure cylinder.
Preferably, be set to the oxide layer side the protective layer and the top electrode articulamentum be parallel to it is described
The shortest distance on substrate direction is 180-300nm.
Preferably, the array of capacitors further includes multiple node contacts, is located in the substrate, the lower electrode is in institute
The bottom for stating tubular structure is connected with the node contact.
Preferably, the material of the supporting layer includes silicon nitride.
Further, the utility model also provides a kind of semiconductor devices, including above-mentioned array of capacitors.
Preferably, the semiconductor device application is in dynamic RAM.
In conclusion the utility model provides electrode under a kind of array of capacitors is formed in substrate devices area, support
After layer and top electrode, by forming an oxide layer in top electrode, to form a flat capacitor array side in device area edge
Boundary, and increase protective layer on capacitor array boundary, when effectively having evaded subsequent deposition packing material not due to capacitor array boundary
It is smooth and form the short circuit problem that crack in turn results in, improve the reliability of capacitor element.
Detailed description of the invention
Fig. 1 is diagrammatic cross-section of the capacitor in its preparation process in the prior art；
Fig. 2 is the flow diagram of the forming method of array of capacitors provided by the utility model embodiment one；
Fig. 3 a is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S01 mistake
Top view after forming the sacrificial layer being alternately superimposed on and layer of support material in journey；
Fig. 3 b is that the forming method of array of capacitors provided by the utility model embodiment one shown in Fig. 3 a is held at it
Row step S01 forms the diagrammatic cross-section after the sacrificial layer being alternately superimposed on and layer of support material on the direction AA ' in the process；
Fig. 4 a is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S02 mistake
The top view after through-hole is formed in journey；
Fig. 4 b is that the forming method of array of capacitors provided by the utility model embodiment one shown in Fig. 4 a is held at it
The diagrammatic cross-section after through-hole on the direction AA ' is formed during row step S02；
Fig. 5 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S03 mistake
Diagrammatic cross-section after forming lower electrode in journey；
Fig. 6 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S04 mistake
The diagrammatic cross-section after supporting layer is formed in journey；
Fig. 7 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S05 mistake
The diagrammatic cross-section after capacitor dielectric layer is formed in journey；
Fig. 8 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S05 mistake
The diagrammatic cross-section after top electrode is formed in journey；
Fig. 9 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S05 mistake
The diagrammatic cross-section after top electrode filled layer is formed in journey；
Figure 10 is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S05 mistake
The diagrammatic cross-section after top electrode articulamentum is formed in journey；
Figure 11 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S06 process
Diagrammatic cross-section after middle formation layer of oxidized material；
Figure 12 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S06 process
Top view after middle formation oxide layer；
Figure 13 a is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S07 mistake
The top view after protective layer is formed in journey；
Figure 13 b is that the forming method of the array of capacitors in the utility model embodiment one shown in Figure 13 a is executing step
The diagrammatic cross-section after protective layer on the direction AA' is formed during rapid S07；
Figure 14 a is that the forming method of array of capacitors provided by the utility model embodiment two is executing step S07 mistake
The top view after protective layer is formed in journey；
Figure 14 b is that the forming method of the array of capacitors in the utility model embodiment two shown in Figure 14 a is executing step
The diagrammatic cross-section after protective layer on the direction AA' is formed during rapid S07.
Wherein, appended drawing reference is as follows:
Substrate；10A/100A- device region；
10B/100B- external zones；The crack 11-；
12- plug；The contact of 101- contact；
111- separation layer；The first layer of support material of 112'-；
The second layer of support material of 113'-；The first sacrificial layer of 121-；
The second sacrificial layer of 122-；110- through-hole；
Electrode under 120-；130- capacitor dielectric layer；
112- intermediate supports material layer；113- top layer layer of support material；
140- top electrode；150- top electrode filled layer；
160- top electrode articulamentum；170'- layer of oxidized material；
170- oxide layer；180- protective layer.
Specific embodiment
Fig. 1 is diagrammatic cross-section of the capacitor in its preparation process in the prior art, as shown in Figure 1, existing electricity
In container forming process, the depositing filler material layer after the technique for completing device region (Array area) 10A capacitor element, by
In the capacitor array boundary out-of-flatness for being located at device region 10A, so the place (shown in circle) in out-of-flatness is easy to happen crack
11 (Crack), in subsequent formation plug 12 (CT) technique, the dry etching and wet-cleaning of plug hole can all aggravate crack
Gap, later fill metal when, metal can also be crept into gap, so that plug and capacitor array boundary or plug and plug
Short circuit directly occurs, the reliability of capacitor element is impacted.
The core concept of the utility model is, a kind of array of capacitors and semiconductor devices is provided, in substrate devices area
Under upper formation after electrode, supporting layer and top electrode, by forming an oxide layer in top electrode, to form one in device area edge
Flat capacitor array boundary, and when capacitor array boundary increases protective layer, avoids subsequent deposition packing material due to capacitor
Out-of-flatness at array boundary and form crack, and then avoid the short circuit problem between plug caused by crack and capacitor array boundary,
Improve the reliability of capacitor element.
Below in conjunction with the drawings and specific embodiments to the utility model proposes array of capacitors and forming method thereof, partly lead
Body device is described in further detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted
It is that attached drawing is all made of very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating this reality
With the purpose of new embodiment.
Embodiment one
Fig. 2 is the flow diagram of the forming method of the array of capacitors of the utility model embodiment one kind, such as Fig. 2 institute
Show, the forming method of array of capacitors provided by the utility model includes:
S01: a substrate is provided, there is a device region for being used to form capacitor, on the substrate shape in the substrate
At the sacrificial layer and layer of support material being alternately superimposed on；
S02: forming multiple through-holes in the device region, and the through-hole sequentially passes through the layer of support material and institute
Sacrificial layer is stated to expose the substrate；
S03: forming electrode, in the through hole, the lower electrode covers side wall and the bottom of the through-hole, with shape
At multiple tubular structures；
S04: removing the sacrificial layer and forms supporting layer, and the supporting layer connects the outer wall of the lower electrode tubular structure
And extend along the direction for being parallel to substrate surface；
S05: a capacitor dielectric layer and a top electrode are sequentially formed in the surfaces externally and internally of the lower electrode, to constitute capacitor
Device, wherein on device region marginal position, the top electrode corresponds to the part of the supporting layer with the side far from the lower electrode
To protrusion, make the lateral surface of the capacitor on device region marginal position that there is concave-convex side structure；
S06: an oxide layer is formed in the outer surface of the top electrode, the oxide layer fills the described recessed of the capacitor
Gap in convex side structure, and in the device region marginal position, the section of the side of the oxide layer and the top electrode
And the section of the capacitor dielectric layer forms a flat capacitor array boundary in a plane；And
S07: a protective layer is formed in the capacitor array boundary.
Below with reference to the corresponding structural schematic diagram of each step, array of capacitors in the present embodiment is further explained
Forming method.
Fig. 3 a is the forming method of array of capacitors provided by the utility model embodiment one in its execution step S01 mistake
Top view in journey；Fig. 3 b is that the forming method of array of capacitors provided by the utility model embodiment one shown in Fig. 3 a exists
It executes diagrammatic cross-section of the step S01 in the process on the direction AA '.
It in step S01, please refers to shown in Fig. 3 b, a substrate 100 is provided, the substrate 100 includes to be used to form capacitor
The device region 100A of device and positioned at the external zones 100B, the device region 100A of the periphery device region 100A and described outer
Area 100B is enclosed to be isolated by groove isolation construction.In the schematic diagram of the section structure of array of capacitors below, illustrate only
The capacitor devices area part 100A.
The layer of support material being alternately superimposed on and sacrificial layer are formed in the substrate 100.The material of the substrate 100 can
Think monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc. or those skilled in the art
Known other materials is also formed with multiple node contacts 101, the node contact 101 and subsequent institute in the substrate 100
The lower electrode of the capacitor of formation is electrically connected.Certainly, other devices such as isolation structure can also be formed in the substrate 100
Structure, the utility model do not limit this.
The supporting layer is respectively the first layer of support material 112' and the second layer of support material 113', the sacrificial layer difference
For the first sacrificial layer 121 and the second sacrificial layer 122.The first sacrificial layer 121, first is successively formed in the substrate 100
Support layer 112', the second sacrificial layer 122 and the second supporting layer 113'.The first supporting layer 112' is subsequent to be used as capacitor battle array
The middle support layer of column, the second supporting layer 113' are subsequently formed the top support layer of array of capacitors.The substrate 100 with
A separation layer 111 is also formed between the sacrificial layer 121, for the capacitor of memory transistor and top in substrate 100 to be isolated
Device.
The material of the supporting layer is including but not limited to silicon nitride, and the material of the sacrificial layer is including but not limited to oxidation
Silicon, the supporting layer can be used depositing operation with the sacrificial layer and formed, formed for example, by using chemical vapor deposition process.Institute
The thickness definition for stating the first sacrificial layer 121 goes out the subsequent height for being formed by the first layer of support material 112', therefore, described first
The thickness of sacrificial layer 121 can be adjusted according to the height and position of the first layer of support material 112' of required formation.Described
In the case that the thickness of one sacrificial layer 121 and the first layer of support material 112' determine, thickness circle of second sacrificial layer 122
The subsequent height for being formed by the second layer of support material 113' is made, therefore, the thickness of second sacrificial layer 122 can basis
The height and position of second layer of support material 113' of required formation is adjusted.
Fig. 4 a is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S02 process
In top view；Fig. 4 b is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S02
When diagrammatic cross-section on the direction AA '.
In step S02, please refers to shown in Fig. 4 a and Fig. 4 b, form multiple through-holes 110 in the device region 100A, and
And the through-hole 110 sequentially passes through the layer of support material and the sacrificial layer to expose the substrate 100.
Specifically, forming a mask layer on the second layer of support material 113', the mask layer is patterned,
The predetermined region for forming through-hole is exposed, is then exposure mask successively to second layer of support material using patterned mask layer
113', the second sacrificial layer 122, the first layer of support material 112', the first sacrificial layer 121 and separation layer 111 perform etching, and are formed
Then multiple through-holes 110 remove the patterned mask layer.The through-hole 110 exposes the node contact 101, optional
, the through-hole 130 is arranged in six sides.
It further include removing the external zones 100B and the side device region 100A during forming through-hole 110 in the present embodiment
The layer of support material and sacrificial layer on edge.It is understood that by the layer of support material being alternately superimposed on and sacrificial
The through-hole 110 is formed in domestic animal layer, so as in the case where the bottom and side wall of the through-hole 110 forms and has a tubular structure
Electrode, therefore, the total height for being formed with the lamination of the through-hole 110 can define tubular structure in the lower electrode being subsequently formed
Height, so as to by the thickness for increasing by first sacrificial layer 121 and the second sacrificial layer 122, to increase subsequent formed
The height of capacitor so once, that is, the capacitor of the formation can be improved so as to increase the electrode surface area of capacitor
Capacitance.
Fig. 5 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S03 process
In diagrammatic cross-section.It in step S03, please refers to shown in Fig. 5, it is described in the through-hole 110 to form electrode 120
Lower electrode 120 covers side wall and the bottom of the through-hole 110, to form multiple tubular structures.
The lower electrode 120 is located at the part in the through-hole 110, the consistent appearance of pattern and the through-hole 110,
So that the part being located in the through-hole 110 in the lower electrode 120 constitutes a tubular structure.Further, under described
Electrode 120 can be polysilicon electrode, or metal electrode.Instantly it when electrode 120 is metal electrode, such as can use
Titanium nitride (TiN) formation.
Specifically, the lower electrode 120 can be formed on the basis of depositing operation in conjunction with flatening process, for example, firstly,
An electrode material layer is formed in the substrate 100, the electrode material layer covers the bottom and side wall of the through-hole 110, with
And covering the second layer of support material 113'；Then, flatening process (for example, chemical mechanical milling tech) is executed, removal
It is located at the part above the second layer of support material 113' in electrode material layer, so that remaining electrode material layer be made only to be formed
In the through-hole 110, to constitute the lower electrode of a tubular structure.
In addition, in the present embodiment, the node contact 101 is exposed by the through-hole 110, so that being formed
The bottom of tubular structure of lower electrode 120 can be electrically connected with the node contact 101.
Fig. 6 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S04 process
In diagrammatic cross-section.It in step S04, please refers to shown in Fig. 6, remove sacrificial layer and forms supporting layer, the supporting layer is horizontal
Extend to the outer wall for connecting lower 120 tubular structure of electrode and along the direction for being parallel to substrate surface, in tubular structure
Side wall on lower electrode 120 is supported.Specifically, the top support layer 113 is located at multiple cylinders of the lower electrode 120
The periphery top of shape structure, the middle support layer 112 are located at the intermediate position of multiple tubular structures of the lower electrode 120.
It is understood that being simply formed with one layer of middle support layer 112 in the present embodiment, in other embodiments, can be formed two layers
Or more layer middle support layer, can be by controlling the number of plies of layer of support material that formed in substrate 100 in step S01
To control.
Wherein, step S04 includes: and to form first to be opened on the second layer of support material 113' and expose described second
Sacrificial layer 122；Etching removes second sacrificial layer 122；Second is formed to be opened on the first supporting layer 112' and expose
First sacrificial layer 121；Etching removes first sacrificial layer 121；Wherein, first opening is only and described in one
Through-hole 110 is overlapping or first opening is overlapping with multiple through-holes 110 simultaneously；One second opening is only
It is overlapped with a through-hole 110 or second opening is overlapping with multiple through-holes 110 simultaneously.
Fig. 7-Figure 10 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S05
Diagrammatic cross-section in the process.In step S05, firstly, please referring to shown in Fig. 7, a capacitor dielectric layer 130 is formed under described
The surface that the surfaces externally and internally of electrode 120 and the supporting layer expose.The capacitor dielectric layer 130 covers the lower electrode
The inner surface of 120 tubular structure being located inside cylinder and the outer surface outside cylinder, to make full use of the two of lower electrode 120
A apparent surface constitutes the integrated-circuit capacitor with larger electrode surface area.Specifically, gas-phase deposition can be used
Form the capacitor dielectric layer 130.
The capacitor dielectric layer 130 has concave-convex side structure, and the bumps side structure corresponds in the lower electrode
The supporting layer outside 120 tubular structure cylinder.Preferably, the capacitor dielectric layer 130 can be high-K dielectric layer.Into one
Step, the capacitor dielectric layer 130 is multilayered structure, for example, silicon dioxide layer/silicon nitride layer double-layer structure, is forming institute
When stating capacitor dielectric layer 130, it can successively be respectively formed the silicon dioxide layer and the silicon nitride layer.
In addition, in the present embodiment, bottom outside the cylinder of the tubular structure of the lower electrode 120 and it is formed in the substrate
Node contact 101 in 100 connects, and the side wall and two layers of supporting layer of the cylinder periphery of the tubular structure of the lower electrode 120
One separation layer 111 is connected, and therefore, the capacitor dielectric layer 130 does not cover outside the cylinder of the tubular structure of the lower electrode 120
Bottom part, and do not cover the lower electrode 120 tubular structure cylinder outside side wall connection supporting layer part.
Then, it please refers to shown in Fig. 8, forms a top electrode 140 in the inner surface and appearance of the capacitor dielectric layer 130
Face.The top electrode 140 can be with the capacitor in the inside of the correspondence tubular structure and the outside of the tubular structure
Dielectric layer 130 and the lower electrode 120 constitute capacitor.Wherein, on device region 100A marginal position, the top electrode 140
The part of the corresponding supporting layer is protruded with the direction far from the lower electrode 120, makes the electricity on device region 100A marginal position
The lateral surface of container has concave-convex side structure.It is described bumps side structure pattern be located at the lower 120 tubular knot of electrode
The supporting layer outside structure cylinder is corresponding.The top electrode 140 can may be multilayered structure for single layer structure, when described
When top electrode 140 is single layer structure, for example, polysilicon electrode, or metal electrode, when top electrode 140 is metal electrode
When, such as can be formed using titanium nitride (TiN).
Then, it please refers to shown in Fig. 9 and Figure 10, is also formed with electrode between the top electrode 140 and the oxide layer and fills out
Fill layer 150 and connection electrode layer 160.First a top electrode filled layer 150, the top electrode are formed on 140 surface of top electrode
Filled layer 150 covers the top electrode 140, and fills the gap between the top electrode 140.The i.e. described top electrode filled layer
150 fill the gap between the tubular structure of full phase neighbours and cover the structure of above-mentioned formation.Preferably, the top electrode filled layer
150 material includes boron doped polysilicon.Later, top electrode articulamentum 160 is formed on the top electrode filled layer 150,
The top electrode articulamentum 160 covers the outer surface of the top electrode filled layer 150.Preferably, the top electrode articulamentum 160
Material including but not limited to tungsten, the material of the oxide layer 170 is including but not limited to silica.
Equally, the top electrode filled layer 150 and the top electrode articulamentum 160 all have concave-convex side structure, described
Concave-convex side structure corresponds to the supporting layer outside the lower 120 tubular structure cylinder of electrode
Above-mentioned capacitance structure increases stability, but such continuous support by adding the laterally consecutive supporting layer of electrode
Layer will form the capacitor array boundary of out-of-flatness, i.e., described 140 side of top electrode is in concave-convex pattern, in subsequent deposition packing material
Shi Rongyi the out-of-flatness of capacitor array boundary at (concave-convex side) formed crack, cause plug and capacitor array boundary short circuit,
Influence the stability of capacitor element.To avoid the plug as caused by the out-of-flatness of capacitor array boundary and the short circuit of capacitor array boundary
The problem of, the present embodiment follows the steps below:
Figure 11-Figure 12 is that the forming method of array of capacitors provided by the utility model embodiment one is executing step
Diagrammatic cross-section during S06.In step S06, an oxide layer 170 is formed in 160 outer surface of top electrode articulamentum,
The oxide layer 170 fills the gap in the concave-convex side structure of the capacitor, and at the edge the device region 100A
Position, the side of the oxide layer 170 and the top electrode 140 (including the capacitor dielectric layer 130, the top electrode are filled
Layer 150 and top electrode articulamentum 160) section in a plane, formed a flat capacitor array boundary.
Specifically, layer of oxidized material 170' is formed on the top electrode articulamentum 160 firstly, please refer to shown in Figure 11,
As shown in figure 11, in the marginal position close to the device region 100A, the top electrode articulamentum 160, top electrode filled layer
150, the pattern of top electrode 140 and capacitor dielectric layer 130 on the supporting layer outside the cylinder of the tubular structure of the lower electrode 120
With the consistent appearance of the supporting layer, be out-of-flatness concaveconvex structure, and the layer of oxidized material 170' be completely covered it is described under
Supporting layer outside the cylinder of the tubular structure of electrode 120, i.e., the described oxide layer 170 fill the recessed of the top electrode articulamentum 160
Convex side, and basad 100 external zones 100B extends.
Then, a mask layer is formed on the layer of oxidized material 170', the mask layer is patterned, to be formed
Patterned mask layer, the patterned mask layer covering concave-convex side structure；Then, it is with patterned mask layer
The exposure mask successively top electrode to the layer of oxidized material 170' and positioned at lower 120 bottom part of tubular structure of the electrode periphery
Articulamentum 160, top electrode filled layer 150, top electrode 140 and capacitor dielectric layer 130 are performed etching to exposing the separation layer
111, oxide layer 170 is formed, as shown in figure 11, forms a flat capacitor array boundary at the edge device region 100A.
The array boundary can be arranged in parallel with the tubular structure of the lower electrode 120 in vertical direction, can also be with
The gradient setting of substrate 100 at an angle.Preferably, the present embodiment is by suitably increasing the layer of oxidized material 170' in institute
The thickness of top electrode articulamentum 160 is stated, etching forms the oxide layer 170, forms one and the capacitor of substrate 100 at an angle
Array boundary.Wherein, the material of the oxide layer 170 includes but is not limited to silica.
Figure 13 a is that the forming method of array of capacitors provided by the utility model embodiment one is executing step S07 mistake
Top view in journey；Figure 13 b is that the forming method of the array of capacitors in the utility model embodiment one shown in Figure 13 a is being held
Diagrammatic cross-section during row step S07 on the direction AA'.In step S07, please refer to shown in Figure 13 a and Figure 13 b,
A protective layer 180 is formed on the capacitor array boundary.The protective layer 180 covers 170 upper surface of oxide layer and (is located at institute
State lower 120 tubular structure top of electrode), capacitor array boundary (side of the oxide layer 170, the top electrode articulamentum 160
Side, the side of top electrode filled layer 150, the side of top electrode 140 and capacitor dielectric layer 130 side) and be located at substrate
The separation layer 111 on 100.The material of the protective layer 180 may include silicon nitride, silicon carbide, one in silicon oxynitride
Kind, it is also possible to selected from by silicon nitride, silicon carbide, one of constituted group of silicon oxynitride.
Increase a protective layer 180 on the capacitor element array boundary, further strengthens the lateral surface to capacitor
Concave-convex side structure protection, reduce subsequent deposition packing material when due to capacitor array boundary formed crack possibility
Property, and then the short circuit problem between plug caused by crack and capacitor array boundary is avoided, improve the reliability of capacitor element.
Between the protective layer 180 and the top electrode articulamentum 160 on 170 side of oxide layer most
Short distance is 180-300nm, i.e., the described protective layer 180 is being parallel to 100 side of substrate with the top electrode articulamentum 160
The upward shortest distance is 180-300nm, such as can be 200nm, 240nm, 280nm etc..It is understood that when described
Capacitor array boundary is arranged at an angle with substrate 100, and the shortest distance refers to the protective layer 180 and is located at described
The distance between the top electrode articulamentum 160 on the tubular structure top of lower electrode 120.Control is located at 170 side of oxide layer
On the oxide layer 180 and the distance between the top electrode articulamentum 160, guaranteeing that the protective layer 180 reduces capacitor
While a possibility that forming crack at array boundary, generated stress is to electricity during avoiding the formation of the protective layer 180
Hold the influence of array boundary.
In the forming method for the array of capacitors that the utility model embodiment one provides, under being formed in substrate devices area
After electrode, supporting layer and top electrode, by forming an oxide layer in top electrode, to form a flat electricity in device area edge
Hold array boundary, and increase protective layer on capacitor array boundary, due to capacitor battle array when effectively having evaded subsequent deposition packing material
It arranges boundary out-of-flatness and forms the short circuit problem that crack in turn results in, improve the reliability of capacitor element.
Embodiment two
The present embodiment provides a kind of forming methods of capacitor array.Figure 14 a is provided by the utility model embodiment two
Top view of the forming method of array of capacitors during executing step S07；Figure 13 b is the utility model shown in Figure 14 a
Diagrammatic cross-section of the forming method of array of capacitors in embodiment one during executing step S07 on the direction AA'.Such as
Shown in Figure 14 b, the forming method of capacitor array provided in this embodiment is the formation side of the capacitor array provided in embodiment one
On the basis of method, the protective layer 180 is performed etching, etching removal is located at 170 upper surface of oxide layer and is located at substrate
The protective layer 180 of the separation layer 111 on 100 retains the protective layer 180 for being located at the capacitor array boundary.The present embodiment
The forming method of the capacitor array of offer can be relieved 180 bring stress of protective layer in embodiment one to a certain extent.
Embodiment three
The utility model provides a kind of array of capacitors, please refers to shown in Figure 12, and the array of capacitors includes: a substrate
100, the lower electrode 120 in the substrate 100, capacitor dielectric layer 130, top electrode 140, oxide layer 170, protective layer 180
And it is used to support the supporting layer of the lower electrode 120.
Specifically, the lower electrode 120 is arranged in the substrate 100, and the lower electrode 120 has multiple tubulars
Structure；The supporting layer connects the outer wall of 120 tubular structure of lower electrode and prolongs along the direction for being parallel to 100 surface of substrate
It stretches；The capacitor dielectric layer 130 is set to the surfaces externally and internally of the lower electrode 1020 and the surface of the supporting layer；On described
Electrode 120 is set to the surfaces externally and internally of the capacitor dielectric layer 130, wherein on device region 100A marginal position, it is described to power on
The part of the corresponding supporting layer in pole 120 is protruded with the direction far from the lower electrode 120, makes device region 100A marginal position
On the lateral surface of capacitor there is concave-convex side structure；The oxide layer 170 is set to the outer surface of the top electrode, described
Oxide layer 180 fills the gap in the concave-convex side structure of the capacitor, the side of the oxide layer 180, it is described on
The section of electrode 120 and the section of the capacitor dielectric layer 130 are constituted in a plane in the device region 100A marginal position
One flat capacitor array boundary；And the protective layer 180 is set to the capacitor array boundary.
Preferably, also there is the external zones 100B positioned at the periphery device region 100A, the guarantor in the substrate 100
Sheath 180 is located in the device region 100A.
Preferably, a separation layer 111 is also formed in the substrate 100, the separation layer 111 is set to the lower electrode
120 bottom part of tubular structure periphery, for the capacitor element of memory transistor and top in substrate 100 to be isolated.
Preferably, the array of capacitors further includes multiple node contacts 101, and the node contact 101 is located at the base
In bottom 100, the lower electrode 120 is electrically connected in the bottom of the tubular structure and the node contact 101.
Preferably, the supporting layer includes a top support layer 113 and an at least middle support layer 112.The top layer branch
Support layer 113 is located at the periphery top of multiple tubular structures of the lower electrode 120, and the middle support layer 112 is under described
The intermediate position of multiple tubular structures of electrode 120.One layer of middle support layer 112 is only set in the present embodiment, in other implementations
In example, the middle support layer of two or more layers can be set,
Preferably, the material of the supporting layer and the separation layer includes silicon nitride.
Preferably, a top electrode filled layer 150 and one is additionally provided between the top electrode 140 and the oxide layer 170
Connection electrode layer 160, the top electrode filled layer 150 cover the top electrode 140, and fill between the top electrode 140
Gap.The i.e. described top electrode filled layer 150 fills the gap between the tubular structure of full phase neighbour and covers the structure of above-mentioned formation.
The top electrode articulamentum 160 covers the outer surface of the top electrode filled layer 150, and the oxide layer 170 covers described power on
The outer surface of pole articulamentum 160.Wherein, the top electrode filled layer 150 and the top electrode articulamentum 160 all have bumps
Side structure, the bumps side structure correspond to the supporting layer outside the lower 120 tubular structure cylinder of electrode.
Preferably, the material of the top electrode filled layer 150 includes boron doped polysilicon, the top electrode articulamentum
160 material includes tungsten.
Preferably, the capacitor array boundary can be set with the tubular structure of the lower electrode 120 vertical direction is parallel
It sets, can also be arranged with the gradient of substrate 100 at an angle.
Preferably, the protective layer 180 also covers the upper surface of the oxide layer 170 and is not covered by the oxide layer 170
The substrate 100 of lid, i.e., the described protective layer 180 cover 170 upper surface of oxide layer and (are located at lower 120 tubular of electrode
Structure top end), capacitor array boundary (side of the oxide layer 170, the side of the top electrode articulamentum 160, top electrode
The side of the side of filled layer 150, the side of top electrode 140 and capacitor dielectric layer 130) and in substrate 100 described in every
Absciss layer 111.The material of the protective layer 180 may include silicon nitride, silicon carbide, and one of silicon oxynitride is also possible to select
From in by silicon nitride, silicon carbide, one of constituted group of silicon oxynitride.Increase on the capacitor element array boundary
A protective layer 180 further strengthens the protection to the concave-convex side structure of the lateral surface of capacitor, reduces subsequent deposition filling
A possibility that forming crack due to capacitor array boundary when material, and then avoid plug caused by crack and capacitor array boundary
Between short circuit problem, improve the reliability of capacitor element.
Preferably, the protective layer 180 and the top electrode articulamentum 160 being set on 170 side of oxide layer
Between the shortest distance be 180-300nm, i.e. the protective layer 180 is being parallel to the base with the top electrode articulamentum 160
The shortest distance on 100 direction of bottom is 180-300nm, such as can be 200nm, 240nm, 280nm etc..It is understood that
It is arranged at an angle when the capacitor array boundary with substrate 100, the shortest distance refers to the protective layer 180 and is located at
The distance between the top electrode articulamentum 160 on the tubular structure top of the lower electrode 120.Control is located at oxide layer 170
The distance between described oxide layer 180 and the top electrode articulamentum 160 on side are guaranteeing the reduction of protective layer 180
While capacitor array boundary forms a possibility that crack, generated stress during the protective layer 180 is avoided the formation of
Influence to capacitor array boundary.
Further, as shown in fig. 14b, the protective layer 180 can be provided only on the capacitor array boundary, i.e., the described guarantor
Sheath 180 only covers the side of the oxide layer 170, the side of the top electrode articulamentum 160, top electrode filled layer 150
The side of side, the side of top electrode 140 and capacitor dielectric layer 130.Only in capacitor array boundary setting protective layer one
Determine to can be relieved in degree to form the protective layer 180 generated influence of the stress to capacitor array boundary in the process.
In array of capacitors provided by the utility model, electrode, supporting layer, capacitor are situated between under being arranged in substrate devices area
After matter layer and top electrode constitute capacitor, by the way that an oxide layer is arranged in top electrode, it is flat that one is formed in device area edge
Capacitor array boundary, and increase protective layer on capacitor array boundary, due to capacitor when effectively having evaded subsequent deposition packing material
Array boundary out-of-flatness and form the short circuit problem that crack in turn results in, improve the reliability of capacitor element.
Correspondingly, the utility model also provides a kind of semiconductor devices, it include capacitor array as described above.It is described partly to lead
Body device is applied to dynamic RAM.
In conclusion being formed in substrate devices area in array of capacitors provided by the utility model and semiconductor devices
It is flat to form one in device area edge by forming an oxide layer in top electrode after lower electrode, supporting layer and top electrode
Capacitor array boundary, and increase protective layer on capacitor array boundary, due to capacitor when effectively having evaded subsequent deposition packing material
Array boundary out-of-flatness and form the short circuit problem that crack in turn results in, improve the reliability of capacitor element.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (9)
1. a kind of array of capacitors characterized by comprising
One substrate, the device region for being used to form capacitor with one in the substrate；
Electrode once is arranged on the device region of the substrate, and the lower electrode has multiple tubular structures；
One supporting layer, the supporting layer connect the outer wall of the lower electrode tubular structure and along the directions for being parallel to substrate surface
Extend；
One capacitor dielectric layer, the capacitor dielectric layer are set to the surfaces externally and internally of the lower electrode and the table of the supporting layer
Face；
One top electrode, the top electrode are set to the surfaces externally and internally of the capacitor dielectric layer, wherein on device region marginal position,
The top electrode is corresponded to the part of the supporting layer and is protruded with the direction far from the lower electrode, is made on device region marginal position
The lateral surface of capacitor has concave-convex side structure；
One oxide layer, is set to the outer surface of the top electrode, and the oxide layer fills the concave-convex side of the capacitor
Gap in structure, the section of the side of the oxide layer, the section of the top electrode and the capacitor dielectric layer is in a plane
It is interior, a flat capacitor array boundary is constituted in the device region marginal position；And
One protective layer, the protective layer are set to the capacitor array boundary.
2. array of capacitors as described in claim 1, which is characterized in that the protective layer is also covered in the upper of the oxide layer
Surface and the substrate not covered by the oxide layer.
3. array of capacitors as described in claim 1, which is characterized in that also have in the substrate and be located at outside the device region
The external zones enclosed, the protective layer are located in the device region.
4. array of capacitors as described in claim 1, which is characterized in that the supporting layer is including a top support layer and at least
One middle support layer, wherein the top support layer is set to the mouth periphery of the lower electrode, the middle support layer setting
In the intermediate position of the lower electrode.
5. array of capacitors as described in claim 1, which is characterized in that also set up between the top electrode and the oxide layer
There are top electrode filled layer and top electrode articulamentum,
The top electrode filled layer is covered in the outer surface of the top electrode and fills the gap between the top electrode；
The top electrode articulamentum is covered in the outer surface of the top electrode filled layer, and the oxide layer is covered in the top electrode
The outer surface of articulamentum；
Wherein, the top electrode filled layer and the top electrode articulamentum all have concave-convex side structure, bumps side knot
Structure corresponds to the supporting layer outside the lower electrode tubular structure cylinder.
6. array of capacitors as claimed in claim 5, which is characterized in that be set to the protective layer of the oxide layer side
With the top electrode articulamentum the shortest distance being parallel on the substrate direction be 180-300nm.
7. array of capacitors as described in claim 1, which is characterized in that the array of capacitors further includes that multiple nodes connect
Touching is located in the substrate, and the lower electrode is connected in the bottom of the tubular structure with the node contact.
8. array of capacitors as described in claim 1, which is characterized in that the material of the supporting layer includes silicon nitride.
9. a kind of semiconductor devices, which is characterized in that including such as described in any item array of capacitors of claim 1-8.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970460A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Capacitor array, forming method thereof and semiconductor device |
| US20220037325A1 (en) * | 2020-07-30 | 2022-02-03 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US11456270B2 (en) | 2021-02-25 | 2022-09-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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2018
- 2018-09-29 CN CN201821602797.2U patent/CN208819882U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970460A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Capacitor array, forming method thereof and semiconductor device |
| US20220037325A1 (en) * | 2020-07-30 | 2022-02-03 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US11812601B2 (en) * | 2020-07-30 | 2023-11-07 | Samsung Electronics Co., Ltd. | Semiconductor device including an interface film |
| US11456270B2 (en) | 2021-02-25 | 2022-09-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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