CN208521929U - capacitor device of semiconductor integrated circuit - Google Patents
capacitor device of semiconductor integrated circuit Download PDFInfo
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- CN208521929U CN208521929U CN201820876700.0U CN201820876700U CN208521929U CN 208521929 U CN208521929 U CN 208521929U CN 201820876700 U CN201820876700 U CN 201820876700U CN 208521929 U CN208521929 U CN 208521929U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 129
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 41
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 8
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 8
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 7
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 6
- 229910000410 antimony oxide Inorganic materials 0.000 claims description 5
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 claims description 5
- ZARVOZCHNMQIBL-UHFFFAOYSA-N oxygen(2-) titanium(4+) zirconium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4] ZARVOZCHNMQIBL-UHFFFAOYSA-N 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 238000000034 method Methods 0.000 description 36
- 230000004888 barrier function Effects 0.000 description 27
- 230000007797 corrosion Effects 0.000 description 13
- 238000005260 corrosion Methods 0.000 description 13
- 238000000151 deposition Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000010276 construction Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910018316 SbOx Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
The utility model provides a semiconductor integrated circuit's electric capacity device adopts the laminated structure of three-layer sacrificial layer and three-layer supporting layer, through removing the back at the sacrificial layer, the first top of deposit supports auxiliary layer and second top support auxiliary layer before the opening of supporting layer is opened to the sculpture to increase the sculpture and block, improve the surplus thickness of supporting layer. The utility model discloses can effectively improve the height in electric capacity hole to improve the height of perpendicular condenser in order to increase the plate electrode surface area, can obtain higher capacitance value in the same unit area. The utility model discloses can obtain the supporting layer that surplus thickness is between 10~50nm for perpendicular capacitor structure is more firm, greatly reduced has had the risk that the electric capacity of great height collapsed.
Description
Technical field
The utility model belongs to semiconductor device design and manufacturing field, more particularly to a kind of semiconductor collection
At the capacitive means and preparation method thereof of circuit.
Background technique
Capacitor has voltage adjustment, filtering etc. as one of the necessary component in semiconductor integrated circuit in circuit
Function, thus be widely used in integrated circuit, for example, capacitor is dynamic RAM (DRAM), static random storage
The necessary component of device (SRAM) and some microprocessors.
Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer
Semiconductor storage unit, be made of many duplicate storage units.Each storage unit generally includes capacitor 10 and crystal
Pipe 11；The grid of transistor 11 is connected with wordline 13, the drain/source of transistor 11 is connected with bit line 12, the source of transistor 11
Pole/drain electrode is connected with capacitor 10；Voltage signal in wordline 13 can control opening or closing for transistor 11, and then pass through
Bit line 12 reads the data information being stored in capacitor 10, or data information is written in capacitor 10 by bit line 12
It is stored, as shown in Figure 1.
As dimensions of semiconductor devices is miniature, the horizontal area of capacitor on substrate is gradually reduced.Vertical capacitor is
Deep trouth is formed in the substrate, provides the main polar plate area of capacitor using the side wall of deep trouth, capacitor is reduced in chip with this
The occupied horizontal area in surface, while still can obtain biggish capacitor.
However, although the capacitor of capacitor can greatly be improved by improving capacitor plate height, higher capacitor
There are higher requirement of mechanical strength for device height, and there is the capacitor compared with big height to be easy to face the risk collapsed.
Based on the above, providing one kind can effectively improve capacitor height, and be avoided that capacitor collapsed partly leads
The capacitive means and preparation method thereof of body integrated circuit are necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor integrated circuit
Capacitive means and preparation method thereof, for solving that there is the capacitor compared with big height to be easy to face risk of collapsing in the prior art
The problem of.
In order to achieve the above objects and other related objects, the utility model provides a kind of capacitor dress of semiconductor integrated circuit
The production method set, which is characterized in that for the production method comprising steps of 1) providing a substrate, the substrate has multiple electricity
Hold contact, in forming etching stop layer in the substrate；2) laminated construction is formed on the etching stop layer, the lamination knot
Structure includes the first sacrificial layer stacked gradually, the first supporting layer, the second sacrificial layer, the second supporting layer, 3rd sacrifice layer and
Three supporting layers；3) capacitor hole is etched in the laminated construction, and the capacitor hole appears the capacitor contact；4) first is formed
Bottom and side wall of the conductive layer in the capacitor hole；5) it is formed and covers the third supporting layer and capacitor hole top opening
Barrier layer, and form mask graph on the barrier layer, etch first based on the mask graph and be opened on the resistance
Then barrier and the third supporting layer remove the mask pattern to appear the 3rd sacrifice layer, retain the blocking
Layer；6) 3rd sacrifice layer is removed using wet corrosion technique, to appear second supporting layer；7) the first top branch is formed
Auxiliary layer is supportted on the barrier layer, is with the first top braces auxiliary layer, the barrier layer and the third supporting layer
First exposure mask etches second and is opened in second supporting layer, and in the etching process, first top braces are auxiliary
Layer and the barrier layer is helped to provide the etch stopper of the third supporting layer, to improve the first remaining wall of the third supporting layer
Degree；8) second sacrificial layer is removed using wet corrosion technique, to appear first supporting layer；9) the second top branch is formed
Auxiliary layer is supportted on the third supporting layer, is covered with the second top braces auxiliary layer and the third supporting layer for second
Film etches third and is opened in first supporting layer, and in the etching process, the second top braces auxiliary layer is mentioned
For the etch stopper of the third supporting layer, to improve the second residual thickness of the third supporting layer；10) wet etching is used
Technique removes first sacrificial layer；And 11) inner surface and outer surface of the capacitor dielectric layer in first conductive layer are formed,
It include first conductive layer, the capacitor dielectric layer and institute to be formed in forming the second conductive layer on the capacitor dielectric layer
State the double sided capacitor of the second conductive layer.
Preferably, after the completion of step 9), second residual thickness of the third supporting layer is not less than the third branch
Layer is supportted in the half of the original depth of step 2), to guarantee that the third supporting layer stablizes branch to the double sided capacitor
Support.
Preferably, after the completion of step 9), second residual thickness and the third supporting layer of the third supporting layer
It is generally in equal in the original depth of step 2).
Preferably, the thickness range of the third supporting layer between 10nm~50nm, complete by step 9)
Afterwards, second residual thickness of the third supporting layer is between 10nm~50nm, the material packet of the etching stop layer
Silicon nitride is included, the thickness range of the etching stop layer is between 5nm~60nm.
Preferably, the thickness of first sacrificial layer is less than the thickness of second sacrificial layer, and first sacrificial layer
Thickness be less than the 3rd sacrifice layer thickness, with reduce step 10) using wet corrosion technique removal it is described first sacrifice
The removal difficulty of layer simultaneously improves removal rate.
Preferably, the thickness range of first sacrificial layer is between 100nm~400nm, second sacrificial layer
Thickness range is between 100nm~800nm, and the thickness range of the 3rd sacrifice layer is between 100nm~800nm, institute
The thickness range of the first supporting layer is stated between 10nm~100nm, the thickness range of second supporting layer between 10nm~
Between 100nm, the thickness range on the barrier layer is between 10nm~200nm.
Preferably, the material of first sacrificial layer, second sacrificial layer and the 3rd sacrifice layer includes silica,
The material of first supporting layer, second supporting layer and the third supporting layer includes silicon nitride, first conductive layer
Material include one of metal nitride and metal silicide；The material of the capacitor dielectric layer includes zirconium oxide, oxidation
One of hafnium, titanium oxide zirconium, ruthenium-oxide, antimony oxide, the formed group of aluminium oxide；The material of second conductive layer includes nitrogen
One of compound and metal silicide.
Preferably, the substrate also has the periphery circuit region positioned at the periphery of the multiple capacitor contact, in which: step
1) in, the etching stop layer is also formed on the periphery circuit region；In step 2), the laminated construction is also formed into described
On the etching stop layer of periphery circuit region；In step 5), the barrier layer also forms the lamination knot of periphery circuit region
On structure, while being opened in the third supporting layer based on the mask graph etches described first, it will be located at described
The third supporting layer on periphery circuit region all removes；In step 6), it is sacrificial that the third is removed using wet corrosion technique
While domestic animal layer, the 3rd sacrifice layer on the periphery circuit region will be located at and all removed；In step 7), second is etched
While being opened in second supporting layer, second supporting layer on the periphery circuit region will be located at and all removed；
In step 8), while removing second sacrificial layer using wet corrosion technique, the institute on the periphery circuit region will be located at
The second sacrificial layer is stated all to remove；In step 9), while etching third and be opened in first supporting layer, institute will be located at
First supporting layer stated on periphery circuit region all removes；And in step 10), removed using wet corrosion technique described in
While first sacrificial layer, first sacrificial layer on the periphery circuit region will be located at and all removed, to appear the quarter
Lose stop-layer.
Preferably, in step 7), by controlling the deposition thickness of the first top braces auxiliary layer, to control described the
First residual thickness of three supporting layers.
Preferably, the thickness range of the first top braces auxiliary layer is between 10nm~50nm, meanwhile, described
The thickness range of one top braces auxiliary layer is to guarantee that the first top braces auxiliary layer is only deposited on the barrier layer
Surface, without second support layer surface inserted in the capacitor hole and appeared.
Further, the material of the first top Auxiliary support layer is identical as the material of the third supporting layer, to mention
The depositing selective of the high first top Auxiliary support layer.
Preferably, in step 9), by controlling the deposition thickness of the second top braces auxiliary layer, to control described the
Second residual thickness of three supporting layers, the thickness range of the second top braces auxiliary layer between 10nm~50nm it
Between, meanwhile, the thickness range of the second top braces auxiliary layer is to guarantee that the second top braces auxiliary layer only sinks
Product is in the third support layer surface, without first support layer surface inserted in the capacitor hole and appeared.
Further, the material of the second top Auxiliary support layer is identical as the material of the third supporting layer, to mention
The depositing selective of the high second top Auxiliary support layer.
The utility model also provides a kind of capacitive means of semiconductor integrated circuit, comprising: substrate, the substrate have more
A capacitor contact；Double sided capacitor, comprising: be connected to the first conductive layer of the capacitor contact, it is conductive to be covered in described first
The inner surface of layer and the capacitor dielectric layer of outer surface, and it is covered in the second conductive layer of capacitor dielectric layer outer surface；The
One supporting layer is connected to the lower sides of first conductive layer, is located on the substrate and has first with the substrate
Spacing, first supporting layer have the first opening；Second supporting layer is connected to the middle part of sliding channel of first conductive layer, position
There is the second spacing on first supporting layer and with first supporting layer, second supporting layer has second to open
Mouthful；And third supporting layer, be connected to the top sidewall of first conductive layer, be located at second supporting layer on and with institute
The second supporting layer is stated with third spacing, the third supporting layer is open with third, wherein the thickness of the third supporting layer
Not less than minimum thickness needed for stablizing the support double sided capacitor.
Preferably, it is described it is stable support the double sided capacitor needed for the minimum thickness of the third supporting layer be greater than etc.
In the thickness half of first supporting layer and the second supporting layer any layer.
Preferably, the thickness range of first supporting layer is between 10nm~100nm, the thickness of second supporting layer
Range is spent between 10nm~100nm, and the thickness of the third supporting layer is between 10nm~50nm.
Preferably, first spacing is less than second spacing, and first spacing is less than the third spacing.
Preferably, between range 100nm~400nm of first spacing, the range of second spacing is between 100nm
Between~800nm, the range of the third spacing is between 100nm~800nm.
Preferably, the substrate surface is also covered with etching stop layer, the thickness range of the etching stop layer between
Between 10nm~60nm, the material of the etching stop layer includes silicon nitride, and the substrate also has positioned at the multiple capacitor
The periphery circuit region of the periphery of contact.
Preferably, the material of first supporting layer, second supporting layer and the third supporting layer includes silicon nitride,
The material of first conductive layer includes one of metal nitride and metal silicide；The material packet of the capacitor dielectric layer
Include one of zirconium oxide, hafnium oxide, titanium oxide zirconium, ruthenium-oxide, antimony oxide, the formed group of aluminium oxide；Described second is conductive
The material of layer includes one of nitride and metal silicide.
Preferably, the capacitive means further include top braces auxiliary layer, and the top braces auxiliary layer is stacked and placed on described
The upper surface of third supporting layer, to improve the enabling capabilities of the third supporting layer.
Further, the material of the top Auxiliary support layer is identical as the material of the third supporting layer, to improve
The bond strength of top Auxiliary support layer and the third supporting layer is stated, and reduces the stress of the top Auxiliary support layer.
As described above, the capacitive means of semiconductor integrated circuit and preparation method thereof of the utility model, have with following
Beneficial effect:
1) the utility model uses the laminated construction of three layers of sacrificial layer and three layers of supporting layer to improve the height in capacitor hole, from
And the height of vertical capacitor is improved to increase electrode plate surface product, higher capacitor can be obtained in identical unit area
Value.
2) the utility model is by depositing the first top braces before the opening of etching opening supporting layer after sacrificial layer removes
Auxiliary layer and the second top braces auxiliary layer improve the residual thickness of supporting layer to increase etch stopper, so that vertical capacitor
Structure is more firm.
3) the utility model can obtain residual thickness between the supporting layer of 10~50nm, greatly reduce with larger height
The risk that the capacitor of degree collapses.
4) the utility model simple process, and existing capacitor fabrication technique compatibility with higher, in semiconductor
Memory device manufacturing field is with a wide range of applications.
Detailed description of the invention
Fig. 1 is shown as the structural schematic diagram of dynamic RAM.
Fig. 2~Figure 17 is shown as each step institute of production method of the capacitive means of the semiconductor integrated circuit of the utility model
The structural schematic diagram of presentation, wherein Figure 17 is shown as a kind of knot of the capacitive means of semiconductor integrated circuit of the utility model
Structure schematic diagram.
Figure 18 is shown as the structural schematic diagram of the capacitive means of another semiconductor integrated circuit of the utility model.
Component label instructions
101 substrates
102 capacitor contacts
103 etching stop layers
104 first sacrificial layers
105 first supporting layers
106 second sacrificial layers
107 second supporting layers
108 3rd sacrifice layers
109 third supporting layers
110 capacitor holes
111 first conductive layers
112 barrier layers
113 hard mask layers
114 anti-reflecting layers
115 photoetching offset plate figures
116 capacitor dielectric layers
117 openings
118 first top braces auxiliary layers
119 openings
120 second top braces auxiliary layers
121 openings
122 second conductive layers
123 top electrodes
124 walls
125 top braces auxiliary layers
A capacitor regions
The periphery circuit region B
The thickness of the first supporting layer of D1
The thickness of the second supporting layer of D2
The original thickness of D3 third supporting layer
The thickness of D4 etching stop layer
D5 the first top braces auxiliary layer thickness
First residual thickness of D6 third supporting layer
The thickness of D7 the second top braces auxiliary layer
Second residual thickness of D8 third supporting layer
The thickness on the barrier layer D9
The thickness of the first sacrificial layer of H1
The thickness of the second sacrificial layer of H2
The thickness of H3 3rd sacrifice layer
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig. 2~Figure 17.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in diagram then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 2~Figure 17, the present embodiment provides a kind of production method of the capacitive means of semiconductor integrated circuit, institutes
State production method comprising steps of
As shown in Figure 2 to 3, step 1) is carried out first, a substrate 101 is provided, and the substrate 101, which has, includes multiple electricity
Hold the capacitor regions A of contact 102, the substrate 101 also has the periphery circuit region B positioned at the capacitor regions periphery, in institute
State formation etching stop layer 103 in substrate 101.
The substrate 101 includes silicon substrate, germanium substrate, germanium silicon substrate, silicon carbide substrates etc., in the present embodiment, described
Substrate 101 can be silicon substrate.For example, the substrate 101 is also if the capacitive means are applied to dynamic RAM
The includable transistor character line (Word line) and bit line (Bitline) deposited in array, the capacitor contact 102
It is electrically connected the transistor character line (Word line) source electrode.The capacitor contact 102 can arrange in six square arrays, with
The arrangement of the double sided capacitor of subsequent production is corresponding.It is isolated between the capacitor contact 102 by wall 124, institute
The material for stating wall 124 can be silicon nitride (SiN), silica (SiO2), aluminium oxide (Al2O3) in any one or appoint
It anticipates two or more combinations.
Using techniques such as chemical vapour deposition techniques (CVD) in the substrate 101 (including on the periphery circuit region)
Etching stop layer 103 is formed, to provide etch-stop or other function, the material of the etching stop layer 103 can be nitridation
The thickness D4 range of silicon, the etching stop layer 103 can be between 5nm~60nm.
As shown in figure 4, then carry out step 2), laminated construction is formed on the etching stop layer 103, the lamination knot
Structure includes the first sacrificial layer 104 stacked gradually, the first supporting layer 105, the second sacrificial layer 106, the second supporting layer 107, third
Sacrificial layer 108 and third supporting layer 109.
For example, techniques such as chemical vapor deposition (PECVD) can be enhanced with using plasma, in the etching stop layer
The first sacrificial layer 104, the first supporting layer are sequentially formed on 103 (etching stop layers 103 including the periphery circuit region)
105, the second sacrificial layer 106, the second supporting layer 107,3rd sacrifice layer 108 and third supporting layer 109.
The material of first sacrificial layer 104, second sacrificial layer 106 and the 3rd sacrifice layer 108 can be selected
Material for silica, first supporting layer 105, second supporting layer 107 and the third supporting layer 109 can be selected
For silicon nitride, so that etching selection ratio with higher between each supporting layer and each sacrificial layer, guarantees that each sacrificial layer is complete
Retain each supporting layer of larger thickness while removal.
It needs to remove first sacrificial layer 104 for being located at bottom due to subsequent, when removal needs to pass through depth-to-width ratio
Biggish deep hole pours into corrosive liquid to the surface or inside of first sacrificial layer 104, and the first thicker sacrificial layer 104 can increase
It is added to remove difficulty and reduce its removal rate, accordingly, the thickness design of first sacrificial layer 104 can be by the present embodiment
Less than the thickness of second sacrificial layer 106, and the thickness of first sacrificial layer 104 is less than the 3rd sacrifice layer 108
Thickness subsequent remove the removal difficulty of first sacrificial layer 104 using wet corrosion technique and improves removal rate to reduce.
For example, the thickness H1 range of first sacrificial layer 104 can be between 100nm~400nm, the thickness of second sacrificial layer
Spend H2 range can between 100nm~800nm, the thickness H3 range of the 3rd sacrifice layer can between 100nm~
Between 800nm, higher capacitor can get so as to subsequent.
The thickness D1 range of first supporting layer 105 can be between 10nm~100nm, second supporting layer
107 thickness D2 range can provide relatively stable support for capacitor between 10nm~100nm so as to subsequent.
The original thickness D3 range of the third supporting layer 109 can be between 10nm~50nm, to guarantee that it has foot
Enough original thicknesses provide stablizing for capacitor in subsequent technique and support.
As shown in figure 5, then carrying out step 3), capacitor hole 110 is etched in the laminated construction, the capacitor hole
110 appear the capacitor contact 102.
For example, can be using photoetching process and plasma dry etch process or other deep-hole etching process in described folded
Capacitor hole 110 is etched in layer structure, the surface shape in the capacitor hole 110 is generally rounded.
As shown in fig. 6, then carrying out step 4), the first conductive layer 111 is formed in the bottom and side in the capacitor hole 110
Wall.
For example, the first conductive layer can be formed in the bottom in the capacitor hole 110 and side wall using chemical vapour deposition technique
111, first conductive layer 111 can be covered in 109 surface of third supporting layer simultaneously.The material of first conductive layer 111
Material includes that one or both of metal nitride and metal silicide are formed by compound, in the present embodiment, described the
The material of one conductive layer 111 can be titanium nitride (TiN).
As shown in Figures 7 and 8, step 5) is then carried out, is formed and covers the third supporting layer 109 and the capacitor hole
110 open-topped barrier layers 112, and mask graph is formed on the barrier layer 112, it is etched based on the mask graph
Then opening 117 removes institute in the barrier layer 112 and the third supporting layer 109 to appear the 3rd sacrifice layer 108
Mask pattern is stated, the barrier layer 112 is retained.
It is possible, firstly, to which the techniques such as using plasma enhancing chemical vapor deposition (PECVD) form and cover the third branch
Support layer 109 and the open-topped barrier layer 112 in the capacitor hole 110, the thickness range on the barrier layer 112 between 10nm~
Between 200nm, the material on the barrier layer 112 can be silica or silicon nitride etc..
Then, in sequentially forming mask pattern on the barrier layer 112, the mask pattern may include hard mask layer
113, anti-reflecting layer 114 and photoetching offset plate figure 115.
Then, etching technics can be first passed through and form groove, by capacitor regions and periphery circuit region domain separation.
Finally, opening 117 is etched in the barrier layer 112 and the third supporting layer 109 based on the mask graph,
To appear the 3rd sacrifice layer 108, the mask pattern is then removed, retains the barrier layer 112.
Wherein, the barrier layer 112 is also formed on the laminated construction of periphery circuit region, is carved based on the mask graph
While losing the opening 117 out in the third supporting layer 109, the third on the periphery circuit region will be located at
The all removals of supporting layer 109.
As shown in figure 9, then carrying out step 6), based on the opening 117, the third is removed using wet corrosion technique
Sacrificial layer 108, to appear second supporting layer 107.
Wherein, while removing 3rd sacrifice layer 108 using wet corrosion technique, the periphery circuit region will be located at
On all removals of the 3rd sacrifice layer 108.
As shown in Figures 10 and 11, step 7) is then carried out, forms the first top Auxiliary support layer 118 in the barrier layer
112 surfaces are covered with the first top Auxiliary support layer 118, the barrier layer 112 and the third supporting layer 109 for first
Film etches opening 119 in second supporting layer 107, the first top Auxiliary support layer 118 and the barrier layer
112 can be removed substantially in the etching process, described in the etching process to appear the third supporting layer 109
First top Auxiliary support layer 118 and the barrier layer 112 provide the etch stopper of the third supporting layer 109, to improve
State the first residual thickness of third supporting layer 109.
It in this step, can be by controlling the 118 thickness D5 of the first top Auxiliary support layer, to control the third
The first residual thickness D6 of supporting layer 109.Preferably, the thickness range of the first top Auxiliary support layer 118 can be with
Between 10nm~50nm, the material of the first top Auxiliary support layer 118 can be with the third support layer material phase
Together, such as silicon nitride, to improve its depositing selective, and the deposition quality of the first top Auxiliary support layer 118 is improved.
It should be noted that the thickness D5 of the first top Auxiliary support layer 118 needs to control for cannot be excessive, example
Such as, it sets the thickness D5 of the first top Auxiliary support layer 118 between 10nm~50nm, it is ensured that it can be only
It is deposited on 112 surface of barrier layer, without second supporting layer inserted in the capacitor hole 110 and appeared
107 surfaces, in order to avoid increase removal difficulty.
In this step, while etching opening 119 in second supporting layer 107, the periphery electricity will be located at
The all removals of second supporting layer 107 in the area of road.
As shown in figure 12, step 8) is then carried out, based on the opening 119, using wet corrosion technique removal described the
Two sacrificial layers 106, to appear first supporting layer 105.
Wherein, while removing the second sacrificial layer 106 using wet corrosion technique, the periphery circuit region will be located at
On all removals of second sacrificial layer 106
As shown in FIG. 13 and 14, step 9) is then carried out, forms the second top Auxiliary support layer 120 in the third branch
109 surface of layer is supportted, with the second top Auxiliary support layer 120 and the third supporting layer 109 for the second exposure mask, is etched out
Mouth 121 is in first supporting layer 105, and in the etching process, the second top Auxiliary support layer 120 provides described
The etch stopper of third supporting layer 109, to improve the second residual thickness of the third supporting layer 109.
It in this step, can be by controlling the thickness D7 of the second top Auxiliary support layer 120, to control described the
The second residual thickness D8 of three supporting layers 109.Preferably, the thickness range of the second top Auxiliary support layer 120 is situated between
Between 10nm~50nm.After the completion of step 9), second residual thickness of the third supporting layer 109 is not less than described the
The half of the original depth of three supporting layers 109, to guarantee the third supporting layer 109 to the stabilization of the double sided capacitor
Support, for example, the thickness range of the third supporting layer 109 is between 10nm~50nm, after the completion of step 9),
Second residual thickness of the third supporting layer 109 is between 10nm~50nm.More preferably, pass through control described second
The deposition thickness of top Auxiliary support layer 120, so that etching opening 121 during the first supporting layer 105,
Only the second top Auxiliary support layer 120 is etched removal, and second residual thickness of the third supporting layer 109 with
The original depth of the third supporting layer 109 be generally in it is equal, to further increase the stability of strutting system of the capacitor.
It should be noted that the thickness of the second top Auxiliary support layer 120 needs to control for cannot be excessive, for example,
It sets the thickness of the second top Auxiliary support layer 120 between 10nm~50nm, it is ensured that it can only be deposited
In 109 surface of third supporting layer, without the third supporting layer inserted in the capacitor hole 110 and appeared
109 surfaces, in order to avoid increase removal difficulty, the material and the third support layer material of the second top Auxiliary support layer 120
It is identical, such as silicon nitride, to improve its depositing selective, and improve the deposition quality of the second top Auxiliary support layer 120.
In this step, while etching opening 121 in first supporting layer 105, the periphery electricity will be located at
The all removals of first supporting layer 105 in the area of road.
As shown in figure 15, step 10) is then carried out, based on the opening 121, using wet corrosion technique removal described the
One sacrificial layer 104.
Wherein, while removing the first sacrificial layer 104 using wet corrosion technique, the periphery circuit region will be located at
On all removals of first sacrificial layer 104, to appear the etching stop layer 103.
As shown in FIG. 16 and 17, step 11) is finally carried out, forms capacitor dielectric layer 116 in first conductive layer 111
Inner surface and outer surface led comprising described first with being formed in forming the second conductive layer 122 on the capacitor dielectric layer 116
The double sided capacitor of electric layer 111, the capacitor dielectric layer 116 and second conductive layer 122.
For example, forming electricity in the inner surface of first conductive layer 111 and outer surface using the methods of chemical vapor deposition
Hold dielectric layer 116, the material of the capacitor dielectric layer 116 includes zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide zirconium
(ZrTiOx), one of ruthenium-oxide (RuOx), antimony oxide (SbOx), aluminium oxide (AlOx) formed group.Then useization
The methods of vapor deposition is learned, in forming the second conductive layer 122, the material of second conductive layer 122 on the capacitor dielectric layer 116
Matter includes one of nitride and metal silicide.
Finally, further including the steps that the top electrode 123 also covers in depositing top electrode 123 on the double sided capacitor
In on the periphery circuit region, the material of the top electrode 123 can be selected as polysilicon etc..
The utility model uses the laminated construction of three layers of sacrificial layer and three layers of supporting layer to improve the height in capacitor hole 110,
To improve the height of vertical capacitor to increase electrode plate surface product, higher capacitor can be obtained in identical unit area
Value, and by depositing the first top Auxiliary support layer 118 and second before the opening of etching opening supporting layer after sacrificial layer removes
Top Auxiliary support layer 120 improves the residual thickness of supporting layer to increase etch stopper, can obtain residual thickness between 10
The supporting layer of~50nm greatly reduces the wind to collapse with the capacitor compared with big height so that vertical capacitor structure is more firm
Danger.
As shown in figure 17, the present embodiment also provides a kind of capacitive means of semiconductor integrated circuit, comprising: substrate 101, double
Face capacitor, the first supporting layer 105, the second supporting layer 107 and third supporting layer 109.
As shown in figure 17, the substrate 101 has the capacitor regions A comprising multiple capacitor contacts 102, the substrate 101
Also there is the periphery circuit region B positioned at the capacitor regions periphery.The substrate 101 includes silicon substrate, germanium substrate, germanium silicon lining
Bottom, silicon carbide substrates etc., in the present embodiment, the substrate 101 can be silicon substrate.For example, if the capacitive means are answered
For dynamic RAM, then the substrate 101 can also include the transistor character line (Word in memory array
Line) and bit line (Bitline), the capacitor contact 102 are electrically connected the transistor character line (Word line) source electrode.
The capacitor contact 102 can arrange in six square arrays, corresponding with the arrangement of the double sided capacitor of subsequent production.The capacitor
It is isolated between contact 102 by wall 124, the material of the wall 124 can be silicon nitride (SiN), silica
(SiO2), aluminium oxide (Al2O3) in any one or any two or more combinations.
Etching stop layer 103 is formed in the substrate 101, the material of the etching stop layer 103 can be silicon nitride,
The thickness range of the etching stop layer 103 can be between 5nm~60nm.
As shown in figure 17, the double sided capacitor includes the first conductive layer 111 for being connected to the capacitor contact 102, is covered
It is placed on the inner surface of first conductive layer 111 and the capacitor dielectric layer 116 of outer surface, and is covered in the capacitor dielectric layer
Second conductive layer 122 of 116 outer surfaces.
The material of first conductive layer 111 includes that one or both of metal nitride and metal silicide are formed
Compound, in the present embodiment, the material of first conductive layer 111 can be titanium nitride (TiN).
The material of the capacitor dielectric layer 116 can be selected as high K dielectric, including zirconium oxide (ZrOx), hafnium oxide
(HfOx), titanium oxide zirconium (ZrTiOx), ruthenium-oxide (RuOx), antimony oxide (SbOx), in aluminium oxide (AlOx) formed group
It is a kind of.In the present embodiment, the material of the capacitor dielectric layer 116 can be selected as zirconium oxide.
The material of second conductive layer 122 includes being formed by of one or both of nitride and metal silicide
Object is closed, in the present embodiment, the material of second conductive layer 122 can be titanium nitride (TiN).
As shown in figure 17, top electrode 123 is also covered on the double sided capacitor, and the top electrode 123 is also covered in
On the periphery circuit region, the material of the top electrode 123 can be selected as polysilicon etc..
As shown in figure 17, first supporting layer 105 is connected to the lower sides of first conductive layer 111, is located at institute
Stating on substrate 101 and with the substrate 101 has the first spacing, and first supporting layer 105 has opening 121.
The material of first supporting layer 105 can be silicon nitride, and the thickness range of first supporting layer 105 can be situated between
Between 10nm~100nm, to provide relatively stable support for the double sided capacitor.
As shown in figure 17, second supporting layer 107 is connected to the middle part of sliding channel of first conductive layer 111, is located at institute
Stating on the first supporting layer 105 and with first supporting layer 105 has the second spacing, and second supporting layer 107, which has, to be opened
Mouth 119.
The material of second supporting layer 107 can be silicon nitride, and the thickness range of second supporting layer 107 can be situated between
Between 10nm~100nm, to provide relatively stable support for the double sided capacitor.
As shown in figure 17, the third supporting layer 109 is connected to the top sidewall of first conductive layer 111, is located at institute
Stating on the second supporting layer 107 and with second supporting layer 107 has third spacing, and the third supporting layer 109, which has, to be opened
Mouth 119, wherein minimum thickness needed for the thickness of the third supporting layer 109 is not less than the stable support double sided capacitor,
Wherein, the minimum thickness of the third supporting layer 109 needed for the stable support double sided capacitor is more than or equal to described
The thickness half of first supporting layer 105 and 107 any layer of the second supporting layer.
The material of the third supporting layer 109 can be silicon nitride, the thickness of the third supporting layer 109 between 10nm~
Between 50nm, which both can guarantee the stability of the double sided capacitor support, avoid double sided capacitor from collapsing, and energy
Guarantee in technical process, reduces the difficulty of etching.
As an example, first spacing is less than second spacing, and first spacing is less than the third spacing.
For example, between range 100nm~400nm of first spacing, the range of second spacing between 100nm~800nm it
Between, between 100nm~800nm, above-mentioned spacing can reduce the capacitor and collapse risk the range of the third spacing,
The biggish double sided capacitor of height can be obtained again, improve the capacitance of double sided capacitor unit horizontal area.
Figure 18 is shown as the structural schematic diagram of the capacitive means of the semiconductor integrated circuit of another embodiment of the utility model,
Wherein, the capacitive means further include top braces auxiliary layer 125, and the top braces auxiliary layer 125 is stacked and placed on the third
The upper surface of supporting layer 109, to improve the enabling capabilities of the third supporting layer 109.The thickness of the top braces auxiliary layer 125
Degree may range between 5nm~10nm, and material is preferably identical as the material of the third supporting layer, for example, nitrogenize
Silicon, to improve the bond strength of the top Auxiliary support layer 125 and the third supporting layer 109, and it is auxiliary to reduce the top
Help the stress of supporting layer 125.
As described above, the capacitive means of semiconductor integrated circuit and preparation method thereof of the utility model, have with following
Beneficial effect:
1) the utility model uses the laminated construction of three layers of sacrificial layer and three layers of supporting layer to improve the height in capacitor hole, from
And the height of vertical capacitor is improved to increase electrode plate surface product, higher capacitor can be obtained in identical unit area
Value.
2) the utility model is by depositing the first top braces before the opening of etching opening supporting layer after sacrificial layer removes
Auxiliary layer and the second top braces auxiliary layer improve the residual thickness of supporting layer to increase etch stopper, so that vertical capacitor
Structure is more firm.
3) the utility model can obtain residual thickness between the supporting layer of 10~50nm, greatly reduce with larger height
The risk that the capacitor of degree collapses.
4) the utility model simple process, and existing capacitor fabrication technique compatibility with higher, in semiconductor
Memory device manufacturing field is with a wide range of applications.
So the utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (9)
1. a kind of capacitive means of semiconductor integrated circuit characterized by comprising
Substrate, the substrate have multiple capacitor contacts；
Double sided capacitor, comprising: be connected to the first conductive layer of the capacitor contact, be covered in the interior table of first conductive layer
The capacitor dielectric layer in face and outer surface, and it is covered in the second conductive layer of capacitor dielectric layer outer surface；
First supporting layer is connected to the lower sides of first conductive layer, is located on the substrate and has with the substrate
There is the first spacing, first supporting layer has the first opening；
Second supporting layer is connected to the middle part of sliding channel of first conductive layer, be located at first supporting layer on and with it is described
First supporting layer has the second spacing, and second supporting layer has the second opening；And
Third supporting layer is connected to the top sidewall of first conductive layer, be located at second supporting layer on and with it is described
Second supporting layer has third spacing, and the third supporting layer is open with third, wherein the thickness of the third supporting layer is not
Less than minimum thickness needed for stablizing the support double sided capacitor.
2. capacitive means according to claim 1, it is characterised in that: needed for the stable support double sided capacitor
The minimum thickness of the third supporting layer is more than or equal to the thickness two of first supporting layer and the second supporting layer any layer
/ mono-.
3. capacitive means according to claim 1, it is characterised in that: the thickness range of first supporting layer is between 10nm
Between~100nm, the thickness range of second supporting layer is between 10nm~100nm, the thickness of the third supporting layer
Between 10nm~50nm.
4. capacitive means according to claim 3, it is characterised in that: first spacing is less than second spacing, and
First spacing is less than the third spacing.
5. capacitive means according to claim 4, it is characterised in that: range 100nm~400nm of first spacing it
Between, the range of second spacing is between 100nm~800nm, and the range of the third spacing is between 100nm~800nm
Between.
6. capacitive means according to claim 1, it is characterised in that: the substrate surface is also covered with etching stop layer,
For the thickness range of the etching stop layer between 10nm~60nm, the material of the etching stop layer includes silicon nitride, institute
Stating substrate also has the periphery circuit region positioned at the periphery of the multiple capacitor contact.
7. capacitive means according to claim 1, it is characterised in that: first supporting layer, second supporting layer and
The material of the third supporting layer includes silicon nitride, and the material of first conductive layer includes metal nitride and metal silicide
One of；The material of the capacitor dielectric layer includes zirconium oxide, hafnium oxide, titanium oxide zirconium, ruthenium-oxide, antimony oxide, aluminium oxide
One of formed group；The material of second conductive layer includes one of nitride and metal silicide.
8. described in any item capacitive means according to claim 1~7, it is characterised in that: the capacitive means further include top
Auxiliary layer is supported, the top braces auxiliary layer is stacked and placed on the upper surface of the third supporting layer, to improve the third support
The enabling capabilities of layer.
9. capacitive means according to claim 8, it is characterised in that: the material of the top Auxiliary support layer and described the
The material of three supporting layers is identical, to improve the bond strength of the top Auxiliary support layer Yu the third supporting layer, and reduces
The stress of the top Auxiliary support layer.
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| CN201820876700.0U CN208521929U (en) | 2018-06-07 | 2018-06-07 | capacitor device of semiconductor integrated circuit |
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| CN201820876700.0U CN208521929U (en) | 2018-06-07 | 2018-06-07 | capacitor device of semiconductor integrated circuit |
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| CN108550569A (en) * | 2018-06-07 | 2018-09-18 | 睿力集成电路有限公司 | Capacitive means of semiconductor integrated circuit and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550569A (en) * | 2018-06-07 | 2018-09-18 | 睿力集成电路有限公司 | Capacitive means of semiconductor integrated circuit and preparation method thereof |
| CN112397509A (en) * | 2019-08-16 | 2021-02-23 | 长鑫存储技术有限公司 | Capacitor array structure, forming method thereof and semiconductor memory |
| CN112563206A (en) * | 2019-09-25 | 2021-03-26 | 长鑫存储技术有限公司 | Method for manufacturing capacitor of memory |
| CN112563206B (en) * | 2019-09-25 | 2022-06-07 | 长鑫存储技术有限公司 | Method for manufacturing capacitor of memory |
| CN113497037A (en) * | 2020-03-20 | 2021-10-12 | 长鑫存储技术有限公司 | Double-sided capacitor structure and forming method thereof |
| CN113497037B (en) * | 2020-03-20 | 2023-07-04 | 长鑫存储技术有限公司 | Double-sided capacitor structure and forming method thereof |
| EP4002504A4 (en) * | 2020-05-12 | 2023-03-01 | Changxin Memory Technologies, Inc. | Method for forming capacitor opening hole, and method for forming memory capacitor |
| US11901405B2 (en) | 2020-09-11 | 2024-02-13 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing semiconductor structure |
| US11955511B2 (en) | 2020-09-11 | 2024-04-09 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing semiconductor structure |
| US11996440B2 (en) | 2021-03-17 | 2024-05-28 | Changxin Memory Technologies, Inc. | Capacitor array, method for manufacturing the same and memory |
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