CN208819878U - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- CN208819878U CN208819878U CN201821492474.2U CN201821492474U CN208819878U CN 208819878 U CN208819878 U CN 208819878U CN 201821492474 U CN201821492474 U CN 201821492474U CN 208819878 U CN208819878 U CN 208819878U
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Abstract
The utility model provides a kind of semiconductor devices, gate structure there are two being formed in the substrate, ion implanting is carried out in the substrate below drain region using ion injection method, to form adjusting thresholds area between two gate structures, the threshold voltage of transistor can be changed by adjusting the doping concentration in adjusting thresholds area while not influencing performance of semiconductor device, and the adjusting thresholds area is only formed below drain region can also be to avoid interacting between adjacent active regions.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor devices.
Background technique
Dynamic RAM (DRAM) generallys use the transistor of buried grid structure, in the manufacturing process of DRAM, crystal
What the threshold voltage of pipe was usually fixed, it can not arbitrarily adjust or very complicated making technology is needed just to be adjustable, this is just
Limit the possibility that back end of line changes the threshold voltage of transistor.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor devices, can easily and effectively adjust DRAM transistor
Threshold voltage.
In order to achieve the above object, the utility model provides a kind of semiconductor devices, comprising:
Substrate, forms that there are two source region and the drain regions between two source regions in the substrate；
Two gate structures are formed in the substrate between the source region and the drain region to constitute two transistors；With
And
Adjusting thresholds area, in the substrate below the drain region, by adjusting the doping concentration in the adjusting thresholds area
To change the threshold voltage of the transistor.
Optionally, groove isolation construction is also formed in the substrate, the groove isolation construction defines multiple active
Area, forms that there are two the source region and a drain regions in each active area.
Optionally, the drain region and the source region extend to the first depth position in the substrate from the surface of the substrate
It sets, the gate structure extends to the second depth location in the substrate, second depth position from the surface of the substrate
Set and be more sunken to first depth location down so that along the side wall and bottom wall of gate structure from the source region to the drain region it
Between region constitute the channel region of the transistor, the adjusting thresholds area is located at the first depth location and of the substrate
Between two depth locations, to adjust the concentration of the substrate between first depth location and second depth location.
Optionally, the lateral boundaries in the adjusting thresholds area all extend to the side wall of the gate structure.
Optionally, well region is also formed in the substrate, the adjusting thresholds area is located in the well region.
Optionally, when the transistor is N-type transistor, the adjusting thresholds area is n-type doping so that the transistor
Threshold voltage negative drift.
Optionally, the conductive ion of the adjusting thresholds area doping includes boron ion.
Optionally, the size of the threshold voltage of the doping concentration and transistor in the adjusting thresholds area is positively correlated.
Optionally, the concentration of the conductive ion of the adjusting thresholds area doping is between 5E13 atoms/cm2~1E14
atoms/cm2。
In semiconductor devices provided by the utility model, there are two gate structures for formation in the substrate, are infused using ion
Enter method and carries out ion implanting in the substrate below drain region, to form adjusting thresholds area between two gate structures,
The threshold of transistor can be changed by adjusting the doping concentration in adjusting thresholds area while not influencing performance of semiconductor device
Threshold voltage, and the adjusting thresholds area is only formed below drain region can also be to avoid interacting between adjacent active regions.
Detailed description of the invention
Fig. 1 is the flow chart of the forming method of semiconductor devices provided by the embodiment of the utility model；
Fig. 2-Fig. 4 is the semiconductor junction that the forming method provided by the embodiment of the utility model using semiconductor devices is formed
The diagrammatic cross-section of structure；
In figure, appended drawing reference are as follows:
1- substrate；11- well region；12- deep N-well；111- source region；The drain region 112-；113- adjusting thresholds area；
2- gate structure；
3- mask layer；31- opening；
4- bit line contact.
Specific embodiment
Inventors have found that the threshold voltage of transistor is closely bound up with the doping concentration of substrate, it is possible to pass through
The doping concentration of substrate is adjusted to change the threshold voltage of transistor.Through further research, it has been found that having for same active area
There are two the semiconductor devices for the transistor for sharing drain region, the source region of two transistors abuts groove isolation construction, if in source region
Ion implanting is carried out in the substrate of bottom, is equivalent to the resistance for reducing substrate, and the electronics between an active area is possible to meeting
Into in adjacent active area, so that two adjacent active areas is influenced each other, the overall performance of semiconductor devices is caused to decline.
Based on this, the utility model provides a kind of semiconductor devices, is formed in the substrate there are two gate structure, is used
Ion injection method carries out ion implanting in the substrate below drain region, to form adjusting thresholds area in two gate structures
Between, transistor can be changed while not influencing performance of semiconductor device by adjusting the doping concentration in adjusting thresholds area
Threshold voltage, and the adjusting thresholds area is only formed below drain region can also be to avoid the mutual shadow between adjacent active regions
It rings.
Specific embodiment of the present utility model is described in more detail below in conjunction with schematic diagram.It is retouched according to following
It states and claims, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing is all made of very simplification
Form and use non-accurate ratio, only to it is convenient, lucidly aid in illustrating the purpose of the utility model embodiment.
Fig. 4 is the schematic diagram of semiconductor devices provided in this embodiment, as shown in figure 4, the semiconductor devices includes: lining
Bottom 1, forms that there are two source region 111 and the drain regions 112 between two source regions 111 in the substrate 1；Two grid knots
Structure 2 is formed in the substrate 1 between the source region 111 and the drain region 112 to constitute two transistors；And adjusting thresholds
Area 113, in the substrate 1 of 112 lower section of the drain region, by adjusting the adjusting thresholds area 113 doping concentration to change
The threshold voltage of the transistor.
Specifically, being formed with groove isolation construction and several active areas, the ditch in the substrate 1 please continue to refer to Fig. 4
The adjacent active area is isolated in recess isolating structure, and each active area includes two source regions 111 and a drain region 112, described
It is formed in the substrate 1 of active area there are two gate trench, the gate trench is formed in the substrate 1 and is located at the source region
Between 111 and the drain region 112, the gate structure 2 is formed in a gate trench, wherein the grid
Structure 2 includes gate dielectric layer and grid conducting layer, and the gate dielectric layer covers the bottom wall and side wall of the gate trench, institute
Grid conducting layer is stated to be filled in the gate trench.
Further, the gate structure 2 is respectively positioned between the source region 111 and the drain region 112 to constitute transistor, can
With understanding, two transistors in same active area use the one adjacent thereto source region 111 respectively, and share described
Drain region 112.The drain region 112 and the source region 111 respectively from the surface of the substrate 1 to the internal stretch of the substrate 1 to
First depth location, the gate structure is from the surface of the substrate to the internal stretch of the substrate 1 to the second depth location.
Optionally, the adjusting thresholds area 113 is located at the lower section in the drain region 112, and is located between two gate structures 2.
Also, second depth location is more sunken to down first depth location, so that the bottom of the gate structure 2 is more sunken to down
The source region 111 and the drain region 112, to constitute the channel region of the transistor, i.e., along the trenched side-wall of gate trench
And groove bottom wall is from source region 111 to the region between the drain region 112.The adjusting thresholds area 113 is by adjusting described in two
The doping concentration of the section substrate in the first depth location to the second depth location between gate structure 2, or can also be with this
Understand, the adjusting thresholds area 113 changes the doping concentration of part channel region, so as to change the threshold value of transistor
Voltage.But the adjusting thresholds area 113 is because be only located at the lower section in the drain region 112, apart from the groove isolation construction compared with
Far, the blanketing effect of the groove isolation construction will not be influenced.
Optionally, the lateral boundaries in the adjusting thresholds area 113 all extend to the side wall of the gate structure 2, the threshold value
Adjust area 113 surface and bottom surface can be respectively in first depth location and second depth location, can also be equal
Between first depth location and second depth location, or as described in Figure 4, the adjusting thresholds area 113
Surface be located at first depth location, bottom surface between first depth location and second depth location, this
Utility model is no longer illustrated one by one.
Further, it is also formed with a well region 11 in the substrate 1, in the present embodiment, the well region 11 is p-well, the threshold
Value adjustment area 113 is formed in the well region 11, and the ion doping concentration in the well region 11 is lower than the source region 111 and described
Ion doping concentration in drain region 112.Further, the doping type of the well region 11 can be according to the class for being formed by transistor
Type determines, for example, then the well region 11 can adulterate phosphonium ion (P) accordingly when the transistor is P-type transistor；When described
Transistor is N-type transistor, then the well region 11 can adulterate boron ion (B) accordingly.One is also formed in the substrate 1 to be used for
The deep-well region of isolation, in the present embodiment, the deep-well region is deep N-well 12, and the deep N-well 12 is formed under the well region 11
Side, the transistor is isolated, prevents external factor from interfering to the transistor, or prevents different active areas
Between interfere with each other, while being also prevented from the transistor and interfering other external devices.
Optionally, in the present embodiment, the transistor is N-type transistor, then the adjusting thresholds area 113 is n-type doping,
The conductive ion adulterated in the i.e. described adjusting thresholds area 113 be N-type ion (such as phosphonium ion) so that the transistor threshold value
Voltage positive drift.Also, the size positive of the threshold voltage of the doping concentration in the adjusting thresholds area 113 and the transistor
It closes, i.e., when the doping concentration in the described adjusting thresholds area 113 increases, the threshold voltage of the transistor also increases, conversely, the threshold
When the doping concentration in value adjustment area 113 reduces, the threshold voltage of the transistor also reduces, in the present embodiment, the threshold value tune
The concentration of the conductive ion of doping in main plot 113 is between 5E13atoms/cm2~1E14atoms/cm2.
Based on this, as shown in Figure 1, the utility model additionally provides a kind of forming method of semiconductor devices, comprising:
S1: substrate is provided, there are two source region and the drain regions between two source regions for formation in the substrate；
S2: two gate structures are formed in the substrate between the source region and the drain region to constitute two transistors；
And
S3: executing the first ion implantation technology, to carry out ion implanting in the substrate below the drain region to form threshold
Value adjustment area, changes the threshold voltage of the transistor by adjusting the doping concentration in the adjusting thresholds area.
Specifically, being formed with several active areas, the active area in the substrate 1 referring to Fig. 2, provide the substrate 1
Including two source regions 111 and a drain region 112, the drain region 112 is located between two source regions 111, is subsequently formed shape respectively
At two gate structures 2 in the substrate 1 between each source region 111 and the drain region 112, to constitute two crystal
Pipe.
Then as shown in Fig. 2, the surface of the substrate 1 is formed with a mask layer 3, the mask layer 3 covers the substrate
1, and the opening 31 in the corresponding drain region 112 is formed in the mask layer 3, i.e., described 31 lower section of opening is the drain region 112.
Optionally, the material of mask layer 3 described in the present embodiment is photoresist.
Next, the second ion implantation technology is executed, in the leakage referring to Fig. 3, be exposure mask with the mask layer 3
Conductive ion identical with its conduction type is injected in area 112, to increase the doping concentration in the drain region 112, to reduce
The contact resistance on 112 surface of drain region, improves the ducting capacity of the semiconductor devices.Further, second ion
The ion implantation energy of injection technology between 10keV~15keV, and the ion implantation concentration of second ion implanting between
3E13atoms/cm2~6E13atoms/cm2.
Further, then with the mask layer 3 it is exposure mask, the first ion implantation technology is executed, below the drain region 112
Substrate 1 in carry out ion implanting to form the adjusting thresholds area 113, the adjusting thresholds area 113 is in the substrate 1
Position depends on the ion implantation energy of first ion implantation technology, if the ion implanting of first ion implantation technology
Energy is higher, and the adjusting thresholds area 113 is deeper, conversely, if the ion implantation energy of first ion implantation technology is lower,
Then the adjusting thresholds area 113 is more shallow.It is also, since the opening 31 of the mask layer 3 only corresponds to the drain region 112, then described
Adjusting thresholds area 113 is located between two gate structures 2.It is understood that since the adjusting thresholds area 113 is formed
In the lower section in the drain region 112, then the ion implantation energy of first ion implantation technology second ion implanting
Ion implantation energy is bigger, in the present embodiment, the ion implantation energy of first ion implantation technology between 20keV~
50keV, and the concentration of the conductive ion of the adjusting thresholds area 113 doping is between 5E13atoms/cm2~1E14atoms/cm2。
Next Fig. 3-Fig. 4 is please referred to, after forming the adjusting thresholds area 113, can be formed in the opening 31 again
Bit line contact 4, specific technique are as follows: form the polysilicon layer of doping on the substrate 1, the polysilicon layer of the doping covers
The substrate 1 simultaneously fills the opening 31, grinds to remove the polysilicon layer of the doping on 1 surface of substrate, retains institute
The polysilicon layer for stating the doping in opening 31 forms institute's bitline contact 4 on the substrate 1.Institute's bitline contact 4 is used
It is connect in bit line, i.e., the described mask layer 3 is the mask layer for being directly used to form bit line contact, does not need additional increase
New mask layer, has saved light shield.
To sum up, it in semiconductor devices provided by the embodiment of the utility model, is formed in the substrate there are two gate structure,
Ion implanting is carried out in the substrate below drain region using ion injection method, to form adjusting thresholds area in two grids
Between structure, crystalline substance can be changed while not influencing performance of semiconductor device by adjusting the doping concentration in adjusting thresholds area
The threshold voltage of body pipe, and the adjusting thresholds area is only formed below drain region can also be to avoid mutual between adjacent active regions
Mutually influence.
The preferred embodiment that above are only the utility model, does not play the role of any restrictions to the utility model.
Any person of ordinary skill in the field, in the range of not departing from the technical solution of the utility model, to the utility model
The technical solution and technology contents of exposure make the variation such as any type of equivalent replacement or modification, belong to without departing from the utility model
Technical solution content, still fall within the protection scope of the utility model.
Claims (9)
1. a kind of semiconductor devices characterized by comprising
Substrate, forms that there are two source region and the drain regions between two source regions in the substrate；
Two gate structures are formed in the substrate between the source region and the drain region to constitute two transistors；And
Adjusting thresholds area, in the substrate below the drain region, by adjusting the adjusting thresholds area doping concentration to change
Become the threshold voltage of the transistor.
2. semiconductor devices as described in claim 1, which is characterized in that it is also formed with groove isolation construction in the substrate,
The groove isolation construction defines multiple active areas, and there are two described in the source region and one for formation in each active area
Drain region.
3. semiconductor devices as described in claim 1, which is characterized in that the table of the drain region and the source region from the substrate
Face extends to the first depth location in the substrate, and the gate structure extends in the substrate from the surface of the substrate
The second depth location, second depth location is more sunken to down first depth location, so that along the side of gate structure
Wall and bottom wall constitute the channel region of the transistor, the adjusting thresholds area from the source region to the region between the drain region
Between the first depth location and the second depth location of the substrate, to adjust first depth location and described second
The concentration of substrate between depth location.
4. semiconductor devices as claimed in claim 3, which is characterized in that the lateral boundaries in the adjusting thresholds area all extend to institute
State the side wall of gate structure.
5. semiconductor devices as claimed in claim 3, which is characterized in that be also formed with well region, the threshold value in the substrate
Adjustment area is located in the well region.
6. semiconductor devices as described in claim 1, which is characterized in that when the transistor is N-type transistor, the threshold value
Adjusting area is that p-type adulterates the threshold voltage positive drift so that the transistor.
7. semiconductor devices as claimed in claim 6, which is characterized in that the conductive ion of adjusting thresholds area doping includes
Boron ion.
8. semiconductor devices as claimed in claim 6, which is characterized in that the doping concentration in the adjusting thresholds area and the crystalline substance
The size of the threshold voltage of body pipe is positively correlated.
9. semiconductor devices as claimed in claim 8, which is characterized in that the conductive ion of adjusting thresholds area doping it is dense
Degree is between 5E13atoms/cm2~1E14atoms/cm2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821492474.2U CN208819878U (en) | 2018-09-11 | 2018-09-11 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821492474.2U CN208819878U (en) | 2018-09-11 | 2018-09-11 | Semiconductor devices |
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| Publication Number | Publication Date |
|---|---|
| CN208819878U true CN208819878U (en) | 2019-05-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112242304A (en) * | 2020-10-27 | 2021-01-19 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method of forming the same |
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2018
- 2018-09-11 CN CN201821492474.2U patent/CN208819878U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112242304A (en) * | 2020-10-27 | 2021-01-19 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method of forming the same |
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