CN208818756U - A kind of circuit improving STEP-DOWN load current detection precision - Google Patents
A kind of circuit improving STEP-DOWN load current detection precision Download PDFInfo
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- CN208818756U CN208818756U CN201821391725.8U CN201821391725U CN208818756U CN 208818756 U CN208818756 U CN 208818756U CN 201821391725 U CN201821391725 U CN 201821391725U CN 208818756 U CN208818756 U CN 208818756U
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Abstract
A kind of circuit improving STEP-DOWN load current detection precision, including current detecting main body circuit, output circuit, wave filtering circuit, sample rate current applicating example and peripheral applications circuit part；The wave filtering circuit includes buffer input signal amplifier, sampling resistor, sampling capacitance, filter capacitor, filter resistance, third switch, the 4th switch and current source；4th switch and current source are used to improve the precision of load detecting electric current, in parallel with the sampling capacitance；The filter capacitor and filter resistance constitute low-pass filter.The utility model introduces a constant current source in load current detection circuit, the current signal (maximum value of inductive current) kept during flash PMOS tube ends low side NMOS transistor conduction to sampling discharges, simulate actual inductive current, the load current for detecting current detection circuit is closer to actual load current, to eliminate existing load current detection technology bring error.
Description
Technical field
The utility model relates to a kind of integrated circuits, especially provide a kind of raising STEP-DOWN load current detection precision
Circuit.
Background technique
For STEP-DOWN topological structure, when needing to detect load current, the scheme of the prior art is using one
Mirror-image structure is formed with the proportional PMOS tube of flash PMOS tube, which is known as detection pipe.The program is in flash
It can be with accurate detection load current in PMOS tube turn-on cycle；But it is led in the cut-off of flash PMOS tube, low side NMOS tube continued flow tube
In the logical period, since the current signal that sampling hold circuit is kept is the cut-off of flash PMOS tube, low side NMOS tube continued flow tube does not have also
There is a peak point current of the flash PMOS tube of turn-on instant, rather than the real-time current of inductance (load), during will cause this
The electric current inaccuracy of detection.If with this inaccuracy current signal control follow-up system operation, may make entirely be
System generates malfunction.For example when the electric current detected is bigger than normal than actual value, then whole system can be made to enter limited current state in advance,
If the electric current detected is less than normal than actual loading electric current, system can be made to enter interrupter duty mould by continuous operation mode in advance
Formula work, influences the efficiency of system, will lead to system cisco unity malfunction when serious.
Utility model content
To solve the above-mentioned problems, the purpose of the utility model is to provide a kind of inspections of raising STEP-DOWN load current
Survey the circuit of precision.
In order to achieve the above objectives, the technical solution of the utility model is as follows: a kind of raising STEP-DOWN load current detection
The circuit of precision, including current detecting main body circuit, output circuit, wave filtering circuit and sample rate current applicating example part and
Peripheral applications circuit；
The current detecting main body circuit includes detection pipe (Qsen), first switch (SW1), second switch (SW2), PMOS
Manage (Q1) and error amplifier (OP)；The grounded-grid current potential of the detection pipe (Qsen), source electrode connect external input voltage
(VIN), the source electrode of drain electrode connection PMOS tube (Q1), the output of grid connection error amplifier (OP) of the PMOS tube (Q1)
End, the non-inverting input terminal of the error amplifier (OP) are connected between detection pipe (Qsen) and PMOS tube (Q1), anti-phase input
End connection first switch (SW1) and second switch (SW2)；The second switch (SW2) connects external input voltage (VIN)；
The output circuit includes flash PMOS tube (QP) and low side NMOS tube (QN)；The source of the flash PMOS tube (QP)
Pole connects external input voltage (VIN), and drain electrode and the drain electrode of low side NMOS tube (QN) link together and be followed by the current detecting master
First switch (SW1) in body circuit；The source electrode earthing potential of the low side NMOS tube (QN)；
The peripheral applications circuit includes external inductors (L) and load capacitance (Cload)；Described external inductors (L) one end
It is connected between flash PMOS tube (QP) and low side NMOS tube (QN), another termination output voltage (VOUT)；The load capacitance
(Cload) it is connected across between external inductors (L) and ground；
The wave filtering circuit includes buffer input signal amplifier (buf), sampling resistor (Rsen), sampling capacitance
(Csample), filter capacitor (Clpf), filter resistance (Rlpf), third switch (SW3), the 4th switch (SW4) and current source
(Iref)；The drain electrode of sampling resistor one end (Rsen) connection PMOS tube (Q1), another terminal ground potential；The third switch
(SW3) end is connected between sampling resistor (Rsen) and PMOS tube (Q1), the 4th switch (SW4) of other end series winding and current source
(Iref) ground potential is connected afterwards；4th switch (SW4) and current source (Iref) are used to improve the precision of load detecting electric current,
It is in parallel with the sampling capacitance (Csample)；The signal buffer amplifier (buf), filter capacitor (Clpf) and filter resistance
(Rlpf) both ends sampling capacitance (Csample) are connected in parallel on after connecting；The filter capacitor (Clpf) and filter resistance (Rlpf) structure
At low-pass filter, low-pass filtering treatment, the voltage signal sampled (Vsen_FB), the letter are carried out to the signal of detection
It number can be used for the processing of subsequent conditioning circuit；
Sample rate current applicating example part includes CC error amplifier and DMD comparator；The CC error amplifier
And the non-inverting input terminal of DMD comparator is both connected between filter capacitor (Clpf) and filter resistance (Rlpf).
Further, the first switch (SW1), third switch (SW3) and flash PMOS tube (QP) gate voltage signal
It (GP) is signal in the same direction, the gate voltage signal (GN) of second switch (SW2), the 4th switch (SW4) and low side NMOS tube (QN)
It is signal in the same direction, the gate voltage signal (GP) of the flash PMOS tube (QP) and the gate voltage signal of low side NMOS tube (QN)
(GN) it is signal in the same direction, in order to avoid flash PMOS tube (QP) and low side NMOS tube (QN) simultaneously turn on, is equipped with one therebetween
The fixed time difference.
The beneficial effects of the utility model are: a constant current source is introduced in load current detection circuit, in height
The current signal (maximum value of inductive current) kept during NMOS transistor conduction to sampling when PMOS tube ends low discharges,
To simulate actual inductive current, the load current for detecting current detection circuit closer to actual load current,
To eliminate existing load current detection technology bring error.
Detailed description of the invention
Fig. 1 is the principles of the present invention figure；Fig. 2 is the waveform timing diagram of the utility model.
Specific embodiment
Specific embodiment of the present utility model is described in detail with reference to the accompanying drawing.
As shown in Figure 1, detection pipe (Qsen) breadth length ratio is that (i.e. conducting resistance is flash for 1/K times of flash PMOS tube (QP)
K times of PMOS tube), error amplifier OP is used to guarantee during flash PMOS tube (QP) is connected, flash PMOS tube (QP) and inspection
The drain terminal voltage of test tube (Qsen) is equal, eliminates the influence of channel-length modulation.Sampling resistor (Rsen) is what is detected
Load current (Isen) is converted into voltage signal.Third switch (SW3), sampling capacitance (Csample) and buffer input signal are put
Big device (buf) constitutes sampling hold circuit.Filter capacitor (Clpf) and filter resistance (Rlpf) constitute low-pass filter, to detection
Signal carry out low-pass filtering treatment, the voltage signal sampled (Vsen_FB), which can be used for subsequent conditioning circuit
Processing, such as the constant current output to realize STEP_DOWN converter, it is necessary to which signal (Vsen_F) B sampled is fed back
Current constant control is carried out to CC error amplifier input terminal；If there have continuous operation mode to enter for STEP_DOWN converter to be disconnected
The discernible signal of continuous operating mode just needs the input terminal that the signal of sampling is input to DMD comparator to be compared control.The
Four switches (SW4) and current source (Iref) are used to improve the precision of load detecting electric current, end at flash PMOS tube (QP), low side
It during NMOS tube (QN) is connected, discharges the sampling capacitance (Csample) in sampling hold circuit, simulates external electrical electrification
The case where flowing ramp down, keeps the load current detected more acurrate.
A kind of circuit operation principle for improving STEP-DOWN load current detection precision is said below with reference to schematic diagram
It is bright, according to the conducting situation of flash PMOS tube (QP) and low side NMOS tube (QN), it is divided to two duty cycles to carry out working principle
Explanation.
First duty cycle (Phase 1): within the first duty cycle, flash PMOS tube (QP) conducting, low side NMOS tube
(QN) end, first switch (SW1) is closed, and second switch (SW2) disconnects, and error amplifier (OP) works normally, detection pipe
(Qsen) grid perseverance earthing potential, perseverance conducting.Since error amplifier (OP) two input terminal voltages are equal, then flash PMOS tube
(QP) drain voltage is equal with the drain voltage of detection pipe (Qsen), and the source of flash PMOS tube (QP) and detection pipe (Qsen)
It is extremely uniformly connected to external input voltage (VIN), error amplifier (OP) ensure that flash PMOS tube (QP) and detection pipe
(Qsen) drain voltage is equal, eliminates channel-length modulation, so the electric current sampled in the first duty cycle
Isen=(1/K) * IL, sample rate current Isen flow through sampling resistor (Rsen) and generate pressure drop, are sampled voltage.Since third is opened
(SW3) conducting is closed, the voltage sampled is remained on sampling capacitance (Csample) by sampling hold circuit.Remain to sampling
The low-pass filter shape that sampled voltage on capacitor (Csample) is formed by filter capacitor (Clpf) and filter resistance (Rlpf)
At final sampled voltage, subsequent conditioning circuit determines next working condition according to the value of the sampled voltage, such as to realize
The constant current output of STEP_DOWN converter, it is necessary to voltage signal (Vsen_FB) feedback sampled to CC error amplifier
Input terminal carries out current constant control；If thering is continuous operation mode to enter distinguishing for discontinuous operating mode for STEP_DOWN converter
Level signal just needs the input terminal for the voltage signal sampled being input to DMD comparator to be compared.In the first duty cycle
Interior 4th switch (SW4) disconnects, and current source (Iref) does not influence load current detection circuit.Due to can within the period 1
It is identical as existing load current detection method directly to be sampled to inductive current, it can accurately detect load electricity
Flow situation.
The voltage of VS point is VIN-IL*Ron within the first duty cycle；The inductive current slope liter within the first duty cycle
Height, raised slope are (VIN-VOUT)/L.
Second duty cycle (Phase 2): within the second duty cycle, flash PMOS tube (QP) cut-off, low side NMOS tube
(QN) it is connected, first switch (SW1) disconnects, and second switch (SW2) is closed, and error amplifier (OP) is used as comparator work at this time
Make, the output of error amplifier (OP) is high level, acts on the grid of PMOS tube (Q1), then PMOS tube (Q1) is ended, detection
(Qsen) cut-off is managed, no electric current flows through.End at flash PMOS tube (QP), low side NMOS tube (QN) turn-on instant, sampling is protected
It holds third switch (SW3) to disconnect, what is kept on sampling capacitance (Csample) at this time is the maximum current value of inductive current, and real
Under the working condition of border within second round inductive current ramp down, if take no action to will to cause load detecting electric current with
There are errors between actual load current.The 4th switch (SW4) and electric current are introduced within the second duty cycle in this patent
The ramp down behavior of inductive current is simulated in source (Iref), to more accurately detect load current.In the second work
The 4th switch (SW4) is closed in period, is introduced current source (Iref) and is discharged sampling capacitance (Csample), simulaed inductance
The state of current ramp decline.Subsequent conditioning circuit buffer input signal amplifier (buf), low-pass filter, CC error amplifier and
The working condition of DMD comparator, the second duty cycle are identical with the first duty cycle.
Inductive current descending slope is VOUT/L within the second duty cycle.It can be according to the descending slope meter of inductive current
The size of current source (Iref) is calculated, once current source (Iref) determines, load electricity can be accurately detected in whole cycle
Stream, avoids error existing for existing scheme.
Fig. 2 is the timing waveform of each point of this patent scheme, and wherein the dash area in figure is existing load current inspection
Error brought by survey scheme, and this patent then effectively prevents the error makes the load current detected closer to actual
Load current.Flash PMOS tube (QP) is ended, low side NMOS tube (QN) turn-on instant, sampling capacitance (Csample) sampling
To be external inductors (L) peak point current, the voltage change of the capacitor is:
--- --- --- --- --- --- --- --- --- --- --- --- --- ----formula 1
ILmax is the peak point current of external inductors L in formula.Then compensating current element (Iref) should meet the following conditions i.e.:
--- --- --- --- --- --- --- --- --- --- formula 2
T is whole cycle, the sum of period 1 and second round in formula；D is the duty ratio of period 1.According to 1 He of formula
The size of sampling capacitance (Csample) discharge current within the second duty cycle can be set in formula 2.
It is to be illustrated to the preferable implementation of the utility model, but the invention is not limited to the reality above
Example is applied, those skilled in the art can also make various equivalent variations without departing from the spirit of the present invention
Or replacement, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (2)
1. a kind of circuit for improving STEP-DOWN load current detection precision, it is characterised in that: including current detecting main body electricity
Road, output circuit, wave filtering circuit, sample rate current applicating example part and peripheral applications circuit；
The current detecting main body circuit includes detection pipe (Qsen), first switch (SW1), second switch (SW2), PMOS tube
(Q1) and error amplifier (OP)；The grounded-grid current potential of the detection pipe (Qsen), source electrode connect external input voltage
(VIN), the source electrode of drain electrode connection PMOS tube (Q1), the output of grid connection error amplifier (OP) of the PMOS tube (Q1)
End, the non-inverting input terminal of the error amplifier (OP) are connected between detection pipe (Qsen) and PMOS tube (Q1), anti-phase input
End connection first switch (SW1) and second switch (SW2)；The second switch (SW2) connects external input voltage (VIN)；
The output circuit includes flash PMOS tube (QP) and low side NMOS tube (QN)；The source electrode of the flash PMOS tube (QP) connects
The drain electrode of external input voltage (VIN), drain electrode and low side NMOS tube (QN), which links together, is followed by the current detecting main body electricity
First switch (SW1) in road；The source electrode earthing potential of the low side NMOS tube (QN)；
The peripheral applications circuit includes external inductors (L) and load capacitance (Cload)；External inductors (L) end is connected to
Between flash PMOS tube (QP) and low side NMOS tube (QN), another termination output voltage (VOUT)；The load capacitance (Cload)
It is connected across between external inductors (L) and ground；
The wave filtering circuit includes buffer input signal amplifier (buf), sampling resistor (Rsen), sampling capacitance
(Csample), filter capacitor (Clpf), filter resistance (Rlpf), third switch (SW3), the 4th switch (SW4) and current source
(Iref)；The drain electrode of sampling resistor one end (Rsen) connection PMOS tube (Q1), another terminal ground potential；The third switch
(SW3) end is connected between sampling resistor (Rsen) and PMOS tube (Q1), the 4th switch (SW4) of other end series winding and current source
(Iref) ground potential is connected afterwards；4th switch (SW4) and current source (Iref) are used to improve the precision of load detecting electric current,
It is in parallel with the sampling capacitance (Csample)；The signal buffer amplifier (buf), filter capacitor (Clpf) and filter resistance
(Rlpf) both ends sampling capacitance (Csample) are connected in parallel on after connecting；The filter capacitor (Clpf) and filter resistance (Rlpf) structure
At low-pass filter, low-pass filtering treatment, the voltage signal sampled (Vsen_FB), the letter are carried out to the signal of detection
It number can be used for the processing of subsequent conditioning circuit；
Sample rate current applicating example part includes CC error amplifier and DMD comparator；The CC error amplifier and DMD
The non-inverting input terminal of comparator is both connected between filter capacitor (Clpf) and filter resistance (Rlpf).
2. a kind of circuit for improving STEP-DOWN load current detection precision according to claim 1, it is characterised in that:
The gate voltage signal (GP) of the first switch (SW1), third switch (SW3) and flash PMOS tube (QP) is signal in the same direction,
The gate voltage signal (GN) of second switch (SW2), the 4th switch (SW4) and low side NMOS tube (QN) is signal in the same direction, described
The gate voltage signal (GP) of flash PMOS tube (QP) and the gate voltage signal (GN) of low side NMOS tube (QN) are signals in the same direction,
In order to avoid flash PMOS tube (QP) and low side NMOS tube (QN) simultaneously turn on, it is poor that it is equipped with the regular hour therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821391725.8U CN208818756U (en) | 2018-08-28 | 2018-08-28 | A kind of circuit improving STEP-DOWN load current detection precision |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821391725.8U CN208818756U (en) | 2018-08-28 | 2018-08-28 | A kind of circuit improving STEP-DOWN load current detection precision |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111416519A (en) * | 2020-05-07 | 2020-07-14 | 矽力杰半导体技术(杭州)有限公司 | Inductive current reconstruction circuit, reconstruction method and power converter applying inductive current reconstruction circuit and reconstruction method |
| CN116505475A (en) * | 2023-06-27 | 2023-07-28 | 艾科微电子(深圳)有限公司 | Current detection circuit and method of DC-DC converter, power conversion system and power supply |
| CN117783643A (en) * | 2024-02-27 | 2024-03-29 | 无锡力芯微电子股份有限公司 | Load current detection system |
-
2018
- 2018-08-28 CN CN201821391725.8U patent/CN208818756U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111416519A (en) * | 2020-05-07 | 2020-07-14 | 矽力杰半导体技术(杭州)有限公司 | Inductive current reconstruction circuit, reconstruction method and power converter applying inductive current reconstruction circuit and reconstruction method |
| CN116505475A (en) * | 2023-06-27 | 2023-07-28 | 艾科微电子(深圳)有限公司 | Current detection circuit and method of DC-DC converter, power conversion system and power supply |
| CN116505475B (en) * | 2023-06-27 | 2023-09-12 | 艾科微电子(深圳)有限公司 | Current detection circuit and method of DC-DC converter, power conversion system and power supply |
| CN117783643A (en) * | 2024-02-27 | 2024-03-29 | 无锡力芯微电子股份有限公司 | Load current detection system |
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| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220609 Address after: 361011 units 704, 705 and 706, 7th floor, Wanxiang international business center 2 South Building, No. 1694, Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen, Fujian Patentee after: XIAMEN XINYIDAI INTEGRATED CIRCUIT Co.,Ltd. Address before: Unit 305, integrated circuit industrial base, No. 1702, Gangzhong Road, Huli District, Xiamen, Fujian 361011 Patentee before: XIAMEN ASTSEMI TECHNOLOGY CO.,LTD. |
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| TR01 | Transfer of patent right |