CN208796672U - Memory word-line driver structure with symmetric path - Google Patents
Memory word-line driver structure with symmetric path Download PDFInfo
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- CN208796672U CN208796672U CN201821503911.6U CN201821503911U CN208796672U CN 208796672 U CN208796672 U CN 208796672U CN 201821503911 U CN201821503911 U CN 201821503911U CN 208796672 U CN208796672 U CN 208796672U
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Abstract
The utility model relates to semiconductor production fields, disclose a kind of memory word-line driver structure with symmetric path, the activation configuration passes through two layers or two layers of setting or more of transistor combination circuit, and a transistor is individually placed in first layer, and the connection distance with the word-line of two sides of the transistor is made to be equal, and realize that the transistor and the connection of two sides word-line are equidistant, so that the current path in current path driver is symmetrical, be conducive to the performance for improving memory.
Description
Technical field
The utility model relates to semiconductor production fields, drive more particularly to the memory word-line with symmetric path
Device structure.
Background technique
The connection of the word-line of transistor and two sides in the driver of existing memory causes apart from inconsistent
Current path in driver shows asymmetry, and driver is made the time difference occur during opening the word-line of two sides,
Negative impact is caused to the performance of memory.
Utility model content
The purpose of this utility model is to overcome the current paths in the driver in memory of the existing technology
The problem of showing asymmetry provides a kind of memory word-line driver structure with symmetric path, the driver knot
Structure passes through two layers or two layers of setting or more of transistor combination circuit, and a transistor is individually placed in first layer, thus real
Now the connection of the transistor and two sides word-line is equidistant, so that the current path in current path driver is symmetrical,
Be conducive to improve the performance of memory.
To achieve the goals above, the one side of the embodiments of the present invention provides a kind of with symmetric path
Memory word-line driver structure, which is characterized in that the activation configuration includes:
The upper surface of first substrate, first substrate includes neighboring area, and first crystal is arranged in the neighboring area
Pipe, for is drivingly connected positioned at first substrate array region flush type word-line, the first of the first transistor
Grid, the first drain electrode and the first source electrode are set on first substrate；
First electrode separation layer is formed on first substrate, and the first electrode separation layer covering described first is brilliant
Body pipe, the first grid, first drain electrode and first source electrode are located in the first electrode separation layer；
First longitudinal direction connector is located in the first electrode separation layer, one end of the first longitudinal direction connector and institute
State the electrical connection of flush type word-line；
The first metal layer is set on the first electrode separation layer, the first metal layer connection first drain electrode
And the flush type word-line is electrically connected to via the first longitudinal direction connector；
First coating is formed on the first electrode separation layer, and first coating covers first metal
The surface of layer and the first electrode separation layer；
Second substrate is located on first coating, and second substrate includes the active island block of LAM type first, laminated
The LAM type isolation structure of the active island block of formula second and the isolation first active island block and the second active island block, described
It is provided with second transistor on first active island block, is provided with third transistor on the described second active island block, described second
Transistor includes the second grid being set on the described first active island block, the second drain electrode and the second source electrode, the third crystal
Pipe includes the third grid being set on the described second active island block, third drain electrode and third source electrode；
Second electrode separation layer is formed on second substrate, the second grid, second drain electrode, described the
Two source electrodes, the third grid, third drain electrode and the third source electrode are located in the second electrode separation layer；
Second metal layer is set on the second electrode separation layer, second metal layer connection second drain electrode
It drains with the third；
Second coating is formed on the second electrode separation layer, and second coating covers second metal
The surface of layer and the second electrode separation layer；
Wherein, the second transistor and the third transistor according to a medium line of the first transistor interlayer
LAM type balanced configuration and have in contrast to the first transistor transistor types；Also, the second metal layer connects
Connect second drain electrode and third drain electrode and via at least running through the isolation structure and the second electrode separation layer
Second longitudinal direction connector is electrically connected to the first longitudinal direction connector.
Preferably, first drain electrode of the first transistor and at least two institutes in the first transistor two sides
It is equal for stating the connection distance of flush type word-line.
Preferably, the first metal layer further includes the first electricity for being separately connected the first grid, first source electrode
Pole contact.
Preferably, the region that the isolation structure is projected on the first electrode separation layer include the first grid and
First source electrode.
Preferably, the second metal layer further includes being separately connected the second grid, second source electrode, the third
The contact of the second electrode of grid and the third source electrode.
Preferably, the activation configuration further includes being formed in the described second supratectal separation layer.
Preferably, the activation configuration further includes the third for connecting the first electrode contact of the first metal layer
Longitudinal connecting member, the third longitudinal connecting member between the described first active island block and the second active island block, wherein
The third longitudinal connecting member for connecting the first grid is mutually connected to word-line and opens a sluice gate voltage.
Preferably, the third longitudinal connecting member for connecting first source electrode is connected to word-line driving voltage.
Preferably, the activation configuration further include connect the second metal layer the second electrode contact the 4th
Longitudinal connecting member, wherein the 4th longitudinal connecting member for connecting the second grid is mutually connected to word-line and opens a sluice gate voltage, connection
The 4th longitudinal connecting member of the third grid is mutually connected to word-line barrier gate voltage.
Preferably, second drain electrode and third drain electrode are also via the described 4th be located in the second metal layer
Longitudinal connecting member is electrically connected to the second longitudinal direction connector, and the longitudinal length of the 4th longitudinal connecting member is less than described second
The longitudinal length of longitudinal connecting member.
Through the above technical solutions, a kind of memory word with symmetric path that the embodiments of the present invention provides
First line drive structure passes through two layers or two layers of setting or more of transistor combination circuit, and PMOS transistor is individually placed in
First layer, NMOS transistor are placed in the second layer to realize that PMOS transistor and the connection of two sides word-line are equidistant, thus
So that the current path in current path driver is symmetrical, be conducive to the performance for improving memory.
Detailed description of the invention
Fig. 1 is the memory word-line driver structure with symmetric path of embodiment according to the present utility model
Cross-sectional view；
Fig. 2 is the memory word-line driver structure with symmetric path of embodiment according to the present utility model
Circuit connection diagram；
Fig. 3 is the memory word-line driver structure with symmetric path of embodiment according to the present utility model
One of equivalent circuit diagram；
Fig. 4 is the memory word-line driver structure with symmetric path of embodiment according to the present utility model
The two of equivalent circuit diagram；
Fig. 5 A to Fig. 5 J is the memory word-line driving with symmetric path of embodiment according to the present utility model
The cross-sectional view of the corresponding activation configuration of each step of the forming method of device structure.
Description of symbols
1 first substrate, 2 the first transistor
3 flush type word-line, 4 first electrode separation layer
5 first longitudinal direction connector, 6 the first metal layer
7 first coating, 8 second substrate
9 second transistor, 10 third transistor
11 second electrode separation layer, 12 second metal layer
13 second coating, 14 second longitudinal direction connector
15 separation layer 16A-B third longitudinal connecting members
21 first grid of the 4th longitudinal connecting member of 17A-E
22 first 23 first source electrodes of drain electrode
61 first electrodes contact 81 first active island blocks
82 second active 83 isolation structures of island block
The drain electrode of 91 second grids 92 second
93 second source electrode, 101 third grid
102 thirds, 103 third source electrodes of drain electrode
The contact of 121 second electrodes
Specific embodiment
Specific embodiment of the present utility model is described in detail below in conjunction with attached drawing.It should be understood that herein
Described specific embodiment is only used for describing and explaining the present invention, and is not intended to limit the utility model.
Fig. 1 shows the memory word-line driver knot with symmetric path of embodiment according to the present utility model
The cross-sectional view of structure.The one side of the embodiments of the present invention provides a kind of memory word-line drive with symmetric path
Dynamic device structure, there is the memory word-line driver structure of symmetric path may include: for this
The upper surface of first substrate 1, the first substrate 1 includes neighboring area and array region, wherein can be in neighboring area
The first transistor 2 is set, for being drivingly connected the flush type word-line 3 for being located at array region, the first grid of the first transistor 2
21, the first drain electrode 22 and the first source electrode 23 are set to the drain electrode 22 of the first grid 21, first on the first substrate 1 and the first source electrode
23；
First electrode separation layer 4 is formed on the first substrate 1, and first electrode separation layer 4 can cover the first transistor 2,
Also, the drain electrode 22 of first grid 21, first of the first transistor 2 and the first source electrode 23 can be located in first electrode separation layer 4；
First longitudinal direction connector 5 is located in first electrode separation layer 4, and one end of first longitudinal direction connector 5 can be with embedment
Formula word-line 3 is electrically connected；
The first metal layer 6 is set on first electrode separation layer 4, and the first metal layer 6 can connect the first drain electrode 22 and pass through
It is electrically connected by the other end of first longitudinal direction connector 5 with flush type word-line 3；
First coating 7, is formed on first electrode separation layer 4, and the first coating 7 can cover 6 He of the first metal layer
The surface of first electrode separation layer 4；
Second substrate 8 is located on the first coating 7, and the second substrate 8 may include the active island block 81 of LAM type first, change
The active island block 82 of laminar second and the LAM type isolation structure 83 that the first active island block 81 and the second active island block 82 is isolated, the
Second transistor 9 can be set on one active island block 81, third transistor 10 can be set on the second active island block 82,
Second transistor 9 may include the drain electrode of second grid 91, second 92 being set on the first active island block 81 and second source electrode 93,
Third transistor 10 may include the third grid 101 being set on the second active island block 82, third drain electrode 102 and third source electrode
103；
Second electrode separation layer 11 is formed on the second substrate 8,92, second source electrode 93 of the drain electrode of second grid 91, second,
Third grid 101, third drain electrode 102 and third source electrode 103 can be located in second electrode separation layer 11；
Second metal layer 12 is set on second electrode separation layer 11, and second metal layer 12 can connect the second drain electrode 92
With third drain electrode 102；
Second coating 13, is formed on second electrode separation layer 11, and the second coating 13 can cover second metal layer
12 and second electrode separation layer 11 surface；
Wherein, this has second transistor 9 and third crystal in the memory word-line driver structure of symmetric path
Pipe 10 can be according to the interlayer balanced configuration of a medium line of the first transistor 2 and with the crystalline substance in contrast to the first transistor 2
Body cast state；Also, second metal layer 12 can connect the second drain electrode 92 and third drain electrode 102 and via at least through isolation junction
The second longitudinal direction connector 14 of structure 83 and second electrode separation layer 11 is electrically connected with first longitudinal direction connector 5, to make the second crystalline substance
Body pipe 9 and third transistor 10 are connected to flush type word-line 3.
Specifically, the first transistor 2 can be PMOS transistor, and second transistor 9 and third transistor 10 can be
NMOS transistor.In a kind of embodiment of the utility model, the first drain electrode 22 of the first transistor 2 (PMOS transistor) can
There is equal connection distance with the flush type word-line 3 of two sides, so that the flush type word-line of the first transistor 2 and two sides
3 current path has the symmetry of height, so as to avoid the memory word-line driver structure with symmetric path
There is the time difference during opening the word-line of two sides, is conducive to the performance for improving memory.
The first metal layer 6 can also include the first electrode contact 61 for being separately connected first grid 21, the first source electrode 23, with
Form corresponding electric current connecting line.
As shown in Figure 1, the region that isolation structure 83 is projected on first electrode separation layer 4 may include 21 He of first grid
First source electrode 23.
Second metal layer 12 can also include being separately connected second grid 91, the second source electrode 93, third grid 101 and third
The second electrode contact 121 of source electrode 103, to form corresponding electric current connecting line.
As shown in Figure 1, it can also include being formed in second that this, which has the memory word-line driver structure of symmetric path,
Separation layer 15 on coating 13, separation layer 15 is for providing necessary insulation and protection.
Fig. 2 shows the memory word-line driver knots with symmetric path of embodiment according to the present utility model
The circuit connection diagram of structure.As depicted in figs. 1 and 2, there is the memory word-line driver structure of symmetric path can also wrap for this
Include third the longitudinal connecting member 16A and 16B of the first electrode contact 61 of connection the first metal layer 6.Specifically, third is longitudinally connected
Part 16 is between the first active island block 81 and the second active island block 82.Wherein, the third for connecting first grid 21 is longitudinally connected
Part 16A phase is connected to word-line and opens a sluice gate voltage MWLb；The third longitudinal connecting member 16B for connecting the first source electrode 23 is connected to word-line drive
Dynamic voltage X012。
The memory word-line driver structure with symmetric path further includes the second electricity for connecting second metal layer 12
4th longitudinal connecting member 17A-17E of pole contact 121.Wherein, the 4th longitudinal connecting member 17B phase for connecting second grid 91 is connected to
Word-line opens a sluice gate voltage MWLb；4th longitudinal connecting member 17D phase of connection third grid 101 is connected to word-line barrier gate voltage
The connection of second metal layer 12 second drain electrode, 92 Hes of the memory word-line driver structure with symmetric path
Third drain electrode 102 is simultaneously electrically connected to first longitudinal direction connector 5 via second longitudinal direction connector 14.Specifically, such as dotted line generation in Fig. 2
Shown in the current path of table, the second drain electrode 92 and third drain electrode 102 are longitudinally connected via the be located in second metal layer 12 the 4th
Part 17C is electrically connected to second longitudinal direction connector 14, and then is electrically connected to embedment by the first metal layer 6, second longitudinal direction connector 5
Formula word-line 3.Through such a connection manner, so that the first drain electrode 21 of the first transistor 2, the first leakage of second transistor 9
First drain electrode 101 of pole 91 and third transistor 10 is interconnected and is connected to flush type word-line 3.4th longitudinal connecting member
The longitudinal length of 17A-17E is less than the longitudinal length of second longitudinal direction connector 14.
The embodiments of the present invention provide this there is the memory word-line driver structure of symmetric path to include
Upper layer and lower layer, one of ordinary skill in the art are appreciated that bilevel structure is only preferred embodiment, naturally it is also possible to be designed to
Three layers or more of structure.
Fig. 3 shows the memory word-line driver knot with symmetric path of embodiment according to the present utility model
One of equivalent circuit diagram of structure, Fig. 4 show the memory word with symmetric path of embodiment according to the present utility model
The two of the equivalent circuit diagram of first line drive structure.As shown in figure 3, this has the memory word-line driver knot of symmetric path
The structure (Layer1, Layer2) of the brilliant pipe of upper layer and lower layer electricity of structure forms the word-line driver circuit in driver.Fig. 5 A extremely schemes
5J shows the formation of the memory word-line driver structure with symmetric path of embodiment according to the present utility model
The cross-sectional view of the corresponding activation configuration of each step of method.It is described briefly below Fig. 2 shows equivalent circuit diagram and Fig. 5 A to Fig. 5 J
The corresponding relationship of the activation configuration shown.With reference to Fig. 2 and Fig. 5 B, first crystal in 21 corresponding diagram 2 of first grid in Fig. 5 B
At the C of pipe 2, in Fig. 5 B in the first 22 corresponding diagrams 2 of drain electrode at the A of the first transistor 2, in Fig. 5 B in 23 corresponding diagram 2 of the first source electrode
At the B of the first transistor 2；With reference to Fig. 2 and Fig. 5 H, in Fig. 5 H in 91 corresponding diagram 2 of second grid at the C of second transistor 9, figure
In 5H in the second 92 corresponding diagrams 2 of drain electrode at the A of second transistor 9, second transistor 9 in 93 corresponding diagram 2 of the second source electrode in Fig. 5 H
D at；With reference to Fig. 2 and Fig. 5 H, the middle of third transistor 10 in 101 corresponding diagram 2 of third grid in Fig. 5 H, in Fig. 5 H
In third 102 corresponding diagrams 2 of drain electrode at the A of third transistor 10, third transistor 10 in 103 corresponding diagram 2 of third source electrode in Fig. 5 H
E at.
The memory word-line with symmetric path is further described below in conjunction with equivalent circuit diagram shown in Fig. 4 to drive
The circuit connection of dynamic device structure.As shown in figure 4, the of the lower layer of the memory word-line driver structure with symmetric path
First drain electrode 22 of one transistor 2 is by the A point in left side in Fig. 3 to connect and drive the flush type word-line 3 of two sides to be connected
Memory array.First source electrode 23 of the first transistor 2 connects the drive of flush type word-line 3 by the B point in left side in Fig. 3
Dynamic voltage source X012, and voltage MWLb and the first transistor 2 are opened a sluice gate with word-line) first grid 21 connect control driving
Voltage source X012By whether, thus whether controlling the conducting of flush type word-line 3.
As shown in figure 4, the third transistor 10 of the memory word-line driver structure top with symmetric path connects
It is connected to word-line barrier gate switch.Specifically, word-line barrier gate switchsFor the third grid 101 of third transistor 10
Control, the third source electrode 103 and negative potential V of third transistor 10NWLConnection (passes through the 4th longitudinal connecting member 17E shown in Fig. 2
Connection), make VNWLCurrent potential (negative potential) reaches the A point on right side in Fig. 4 via E point by the third drain electrode 102 of third transistor 10
Output closes flush type word-line 3 to flush type word-line 3.
As shown in figure 4, the second transistor 9 of the memory word-line driver structure top with symmetric path is with word
First line is opened a sluice gate voltage MWLb and is controlled as grid, the second source electrode 93 and negative potential V of second transistor 9NWLConnection (passes through Fig. 2 institute
The 4th longitudinal connecting member 17A connection shown), make VNWLCurrent potential (negative potential) is drained via D point by the third of second transistor 9
The A point in left side is exported to flush type word-line 3 in 92 arrival Fig. 4, and flush type word-line 3 is closed.
Fig. 5 A to Fig. 5 J shows the memory word-line with symmetric path of embodiment according to the present utility model
The cross-sectional view of the corresponding activation configuration of each step of the forming method of activation configuration.The embodiments of the present invention it is another
On the one hand a kind of forming method of memory word-line driver structure with symmetric path is additionally provided, such as Fig. 5 A to Fig. 5 J
Shown, which may include:
As shown in Figure 5A, one first substrate 1 is provided, the upper surface of the first substrate 1 includes neighboring area and array region, week
The first transistor 2 is provided in border region, array region is provided with flush type word-line 3；
As shown in Figure 5 B, first electrode separation layer 4 is formed on the first substrate 1, and the is formed in first electrode separation layer 4
The drain electrode 22 of first grid 21, first of one transistor 2 and first source electrode 23 and one end be electrically connected with flush type word-line 3 the
One longitudinal connecting member 5；
As shown in Figure 5 C, the first metal layer 6, first drain electrode of the connection of the first metal layer 6 are formed on first electrode separation layer 4
22 and it is electrically connected to flush type word-line 3 via first longitudinal direction connector 5, the first metal layer 6 further includes being separately connected the first grid
The first electrode contact 61 of pole 21, the first source electrode 23；
As shown in Figure 5 D, the first coating 7 is formed on first electrode separation layer 4, the first coating 7 covers the first metal
The surface of layer 6 and first electrode separation layer 4, and the second substrate 8 is formed on the first coating 7；
As shown in fig. 5e, the second substrate 8 is divided into the active island block 81 of LAM type first, the active island block 82 of LAM type second
And the LAM type isolation structure 83 of the first active island block 81 and the second active island block 82 of isolation；
As illustrated in figure 5f, second transistor 9 is set on the first active island block 81, the is arranged on the second active island block 82
Three transistors 10；
As shown in Fig. 5 G and 5H, second electrode separation layer 11 is formed on the second substrate 8, in second electrode separation layer 11
Form the third grid of second grid 91, second drain electrode 92 and the second source electrode 93 and third transistor 10 of second transistor 9
101, third drain electrode 102 and third source electrode 103；
As shown in fig. 5i, second metal layer 12, the connection of second metal layer 12 second are formed on second electrode separation layer 11
Drain electrode 92 and third drain electrode 102, second metal layer 12 further includes being separately connected second grid 91, the second source electrode 93, third grid
101 and third source electrode 103 second electrode contact 121；
As indicated at figure 5j, the second coating 13, the second coating 13 covering second are formed on second electrode separation layer 11
The surface of metal layer 12 and second electrode separation layer 11；
As indicated at figure 5j, setting at least runs through the second longitudinal direction connector of isolation structure 83 and second electrode separation layer 11
14, second metal layer 12 is electrically connected to first longitudinal direction connector 5 via second longitudinal direction connector 14；
In the embodiments of the present invention, this has the formation of the memory word-line driver structure of symmetric path
Method can also include:
Separation layer 15 is formed on the second coating 13 and is arranged for connecting the first metal layer 6 and second metal layer 12
Third longitudinal connecting member 16 and be electrically connected respectively with second grid 91, the second source electrode 93, third grid 101 and third source electrode 103
The 4th longitudinal connecting member 17 connect.
In a kind of embodiment of the utility model, the first of the first transistor 2 is formed in first electrode separation layer 4
The first longitudinal direction connector 5 that the drain electrode 22 of grid 21, first and the first source electrode 23 and one end are electrically connected with flush type word-line 3 has
May include: to body
The first counterbore is formed using being dry-etched in first electrode separation layer 4, forms first crystal in the first counterbore
The first longitudinal direction that the drain electrode 22 of first grid 21, first of pipe 2 and the first source electrode 23 and one end are electrically connected with flush type word-line 3
Connector 5.
In a kind of embodiment of the utility model, the first metal layer 6 is formed specifically on first electrode separation layer 4
May include:
The first metal original layer is formed on first electrode separation layer 4, converts the first metal original layer to using dry etching
The first metal layer 6.
In a kind of embodiment of the utility model, and forming on the first coating 7 second substrate 8 specifically can be with
Include:
It grows using epitaxy to form the second substrate 8, the material of the second substrate 8 is monocrystalline silicon.
In a kind of embodiment of the utility model, the second of second transistor 9 is formed in second electrode separation layer 11
The drain electrode 92 of grid 91, second and the second source electrode 93 and the third grid 101 of third transistor 10, third drain electrode 102 and third
Source electrode 103 specifically may include:
The second counterbore is formed using being dry-etched in second electrode separation layer 11, forms the second crystal in the second counterbore
The drain electrode 92 of second grid 91, second of pipe 9 and the second source electrode 93 and the third grid 101 of third transistor 10, third drain electrode
102 and third source electrode 103.
In a kind of embodiment of the utility model, second metal layer 12 is formed specifically on second electrode separation layer 11
May include:
The second metal original layer is formed on second electrode separation layer 11, converts the second metal original layer to using dry etching
Second metal layer 12.
In a kind of embodiment of the utility model, setting is at least through isolation structure 83 and second electrode separation layer 11
Second longitudinal direction connector 14 specifically may include:
The third counterbore at least running through isolation structure 83 and second electrode separation layer 11 is formed using dry etching, in third
Second longitudinal direction connector 14 is formed in counterbore.
Preferred embodiments of the present invention, still, the utility model and unlimited are described in detail in conjunction with attached drawing above
In this.In the range of the technology design of the utility model, a variety of simple variants can be carried out to the technical solution of the utility model,
It is combined in any suitable manner including each particular technique feature.In order to avoid unnecessary repetition, the utility model
To various combinations of possible ways, no further explanation will be given.But these simple variants and combination equally should be considered as the utility model institute
Disclosure belongs to the protection scope of the utility model.
Claims (10)
1. the memory word-line driver structure with symmetric path, which is characterized in that the activation configuration includes:
The upper surface of first substrate, first substrate includes neighboring area, and the first transistor is arranged in the neighboring area, is used
In be drivingly connected be located at first substrate array region flush type word-line, the first grid of the first transistor,
First drain electrode and the first source electrode are set on first substrate；
First electrode separation layer is formed on first substrate, and the first electrode separation layer covers the first transistor,
The first grid, first drain electrode and first source electrode are located in the first electrode separation layer；
First longitudinal direction connector is located in the first electrode separation layer, and one end of the first longitudinal direction connector is buried with described
Enter the electrical connection of formula word-line；
The first metal layer is set on the first electrode separation layer, and the first metal layer connection described first drains and passes through
The flush type word-line is electrically connected to by the first longitudinal direction connector；
First coating is formed on the first electrode separation layer, first coating cover the first metal layer and
The surface of the first electrode separation layer；
Second substrate is located on first coating, and second substrate includes the active island block of LAM type first, LAM type the
The LAM type isolation structure of two active island blocks and the isolation first active island block and the second active island block, described first
It is provided with second transistor on active island block, third transistor, second crystal are provided on the described second active island block
Pipe includes the second grid being set on the described first active island block, the second drain electrode and the second source electrode, the third transistor packet
Include the third grid being set on the described second active island block, third drain electrode and third source electrode；
Second electrode separation layer is formed on second substrate, the second grid, second drain electrode, second source
Pole, the third grid, third drain electrode and the third source electrode are located in the second electrode separation layer；
Second metal layer is set on the second electrode separation layer, and the second metal layer connection described second drains and institute
State third drain electrode；
Second coating is formed on the second electrode separation layer, second coating cover the second metal layer and
The surface of the second electrode separation layer；
Wherein, the second transistor and the third transistor are laminated according to the interlayer of a medium line of the first transistor
Formula balanced configuration and have in contrast to the first transistor transistor types；Also, the second metal layer connects institute
State the second drain electrode and third drain electrode and via at least running through the second of the isolation structure and the second electrode separation layer
Longitudinal connecting member is electrically connected to the first longitudinal direction connector.
2. activation configuration according to claim 1, which is characterized in that the first transistor it is described first drain electrode with
It is equal in the connection distance of at least two flush type word-lines of the first transistor two sides.
3. activation configuration according to claim 1, which is characterized in that the first metal layer further includes being separately connected institute
State the first electrode contact of first grid, first source electrode.
4. activation configuration according to claim 1, which is characterized in that the isolation structure is projected in the first electrode
Region on separation layer includes the first grid and first source electrode.
5. activation configuration according to claim 1, which is characterized in that the second metal layer further includes being separately connected institute
State the second electrode contact of second grid, second source electrode, the third grid and the third source electrode.
6. activation configuration according to claim 1, which is characterized in that the activation configuration further include be formed in it is described
Second supratectal separation layer.
7. activation configuration according to claim 3, which is characterized in that the activation configuration further includes connection described the
The third longitudinal connecting member of the first electrode contact of one metal layer, it is active that the third longitudinal connecting member is located at described first
Between island block and the second active island block, wherein the third longitudinal connecting member for connecting the first grid is mutually connected to character
Line opens a sluice gate voltage.
8. activation configuration according to claim 7, which is characterized in that the third of connection first source electrode is longitudinal
Connector is connected to word-line driving voltage.
9. activation configuration according to claim 5, which is characterized in that the activation configuration further includes connection described the
4th longitudinal connecting member of the second electrode contact of two metal layers, wherein connect the second grid the described 4th is vertical
It is mutually connected to word-line to connector and opens a sluice gate voltage, the 4th longitudinal connecting member for connecting the third grid is mutually connected to word-line
Barrier gate voltage.
10. activation configuration according to claim 9, which is characterized in that second drain electrode and third drain electrode are also
The second longitudinal direction connector is electrically connected to via the 4th longitudinal connecting member being located in the second metal layer, described the
The longitudinal length of four longitudinal connecting members is less than the longitudinal length of the second longitudinal direction connector.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110895954A (en) * | 2018-09-13 | 2020-03-20 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical path and forming method thereof |
| WO2021159601A1 (en) * | 2020-02-10 | 2021-08-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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2018
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110895954A (en) * | 2018-09-13 | 2020-03-20 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical path and forming method thereof |
| CN110895954B (en) * | 2018-09-13 | 2024-05-17 | 长鑫存储技术有限公司 | Memory word line driver structure with symmetrical paths and method of forming the same |
| WO2021159601A1 (en) * | 2020-02-10 | 2021-08-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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