JPS60226171A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the yield from lowering the manufacture of SRAMs by a method wherein an etchant-resisting mask is provided in an insulating film formed along the walls inside a fine hole and the insulating film at the bottom of the fine hole is selectively removed without affecting other portions thereby increasing the reliability of a high-resistance load element buried inside a fine hole. CONSTITUTION:A mask 19A formed in a previous process is used for the selective removal of an insulating film 8 on a mask 17 and, further, insulating films 8, 7 covering the bottom surface of a fine hole 6. Thereafter, an opening 8A is formed for the exposure of the primary surface of a substrate 1. Next, the mask 19A is selectively removed for the formation of an electroconductive layer 9, partly in contact with the substrate 1 electrically, constituting a high-resistance load element on the insulating film 8 along the fine hole 6. An insulating film 10 is formed, filling the fine hole 6, on the electroconductive layer 9. Unnecessary portions are removed of the insulating film 10, electrconductive layer 9, mask 17, and the insulating film 4A, whereafter an insulating film 11 is formed on the primary surface of a well region 3. Ordinary processes follow for the completion of an SRAM. In this way, the insulating film on the bottom surface of a fine hole can be completely removed to form an opening, without damaging other portions.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device that uses pores or narrow grooves. It is related to technology.

[Background Art] A semiconductor integrated circuit device (hereinafter referred to as a semiconductor integrated circuit device) equipped with a static random access memory in which a flip-flop is configured by a high-resistance load element and an MIS FET, and a memory cell is configured by the flip-flop and a switching element. , S
There is a trend toward higher integration of RAM (RAM) in order to increase the capacity of information.

Therefore, the applicant has previously filed an application for a technology to improve the degree of integration by forming a pore on the main surface of a semiconductor substrate and embedding the high resistance load element inside the pore to reduce its area. Application No. 57-216825).

A specific method for forming this high resistance load element is performed in the following manufacturing steps.

First, the main surface of the semiconductor substrate to which a predetermined potential is connected is etched using an anisotropic etching technique such as
A pore is formed with a width dimension of [μm] and a depth of 5.0 [μm].

Then, in order to electrically isolate the semiconductor substrate and the conductive layer forming the high resistance load element, an insulating film with a thickness of about 0.3 [μm], for example, is formed on the main surface of the semiconductor substrate along the pores. #! at the bottom of the pore to form and partially electrically connect the semiconductor substrate and the conductive layer. The I edge film is selectively removed using an anisotropic etching technique to expose the main surface of the semiconductor substrate.

Thereafter, a conductive layer serving as a high resistance load element is formed so as to be buried inside the pore so as to be electrically connected to the exposed main surface of the semiconductor substrate.

However, as a result of experiments and studies conducted by the present inventor regarding the etching technique, it has been found that complete anisotropy cannot be obtained using the current anisotropic etching technique.

Before removing the 1t@rim film at the bottom of the extremely thin and deep pore, the insulating film at the opening is removed, resulting in electrical connection between the semiconductor substrate and the conductive layer in unnecessary areas, resulting in high resistance. We have found a problem in that the electrical reliability of the load element is reduced and the yield of SRAM is reduced.

[Objective of the Invention] An object of the present invention is to provide a technical means capable of improving the electrical reliability of a high-resistance load element embedded in a pore in an SRAM using pores.

Another object of the present invention is to provide technical means for improving the electrical reliability of high-resistance load elements embedded in pores and preventing a decrease in yield in SRAMs that utilize pores. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, by forming an etching-resistant mask on the side of the insulating film formed along the inside of the pore,
Using this mask, the insulating film at the bottom of the pore can be selectively removed without affecting other parts.
It is possible to improve the electrical reliability of the high-resistance load element embedded inside the pore, and to prevent a decrease in the yield of SRAM.

Hereinafter, the configuration of the present invention will be explained along with examples.

In this embodiment, the present invention is applied to an SRAM configured by embedding a high resistance load element in a pore.

[Embodiment] FIG. 1 is an equivalent circuit diagram showing a memory cell of an SRAM for explaining the present invention in detail.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, WL is a word line extending in the row direction, and is used to control switching elements to be described later.

DL and DL are data lines provided extending in the column direction, and are used to transmit charges serving as information to memory cells to be described later.

Q,, Q2 are MISFETs with one end connected to the power supply terminal Vcc via a high resistance load element described later and the other end connected to the power supply terminal Vs's, R1 and R'2 are high resistance. It is a load element and is used to configure a flip-flop of a memory cell that stores information.

Q s , +Q s 2 is an MIS whose one end is connected to the data lines DL and D king, the other end is connected to a pair of input/output terminals of the flip-flop, and is controlled by the word line WL.
It is an FET and is used to constitute a switching element of a memory cell.

The memory cells of the SRAM are constituted by a flip-flop having a pair of input/output terminals and a switching element, and a plurality of memory cells are arranged at predetermined intersections between the word line WL and the data lines DL, DL.

Next, a specific configuration of this embodiment will be explained.

FIG. 2 is a plan view of a main part of an SRAM memory cell for explaining the present invention in detail, and FIG. 3 is a plan view of the main parts shown in FIG.
FIG. 3 is a cross-sectional view taken along a cutting line. In addition, in Figure 2,
In order to make the drawing easier to see, an interlayer insulating layer that should be provided between each conductive layer is not shown.

In FIGS. 2 and 3, l is an n+ type semiconductor substrate. This semiconductor substrate 1 is connected to a Vcc voltage.

Reference numeral 2 denotes an n-type epitaxial layer laminated on top of the semiconductor substrate l.

3 is a p-
This is a type well region, and although not shown, it is used to configure a semiconductor element such as a complementary MISFET with an n-type well region.

Note that the substantial semiconductor substrate is composed of the semiconductor base Fi1, the epitaxial layer 2, and the well region 3.

A field insulating film 4 is provided on the main surface of the well region 3 between the semiconductor element forming regions, and is used to electrically isolate the semiconductor elements.

A p-type channel stopper region 5 is provided on the main surface of the well region 3 under the field insulating film 4, and is used to further electrically isolate the semiconductor elements.

Reference numeral 6 denotes a pore extending inward from the main surface of the well region 3 in the semiconductor element forming region, in order to bury a high resistance load element constituting a flip-flop and improve the degree of integration of the memory cell. belongs to. This pore 6 may be provided so that its bottom reaches the main surface of the n' type semiconductor substrate 1.

7 is an insulating film provided along the inside of the pore 6 on the semiconductor substrate 1, the epitaxial layer 2, and the upper main surface of the well region 3;
is an insulating film provided above the insulating film 7 along the inside of the pore 6, and is used to electrically isolate a high resistance load element, which will be described later, and the semiconductor substrate 1.

8A is an opening provided by selectively removing the insulating films 8 and 7 at the bottom of the pore 6, and is for electrically connecting the semiconductor substrate 1 and a high resistance load element to be described later. According to the present invention, the opening 8A is formed by the pore 6.
The insulating film 8 provided inside is not damaged.

Reference numeral 9 denotes a conductive layer, a part of which is electrically connected to the semiconductor substrate 1 through the opening 8A, and is provided along the inside of the pore 6 and on top of the insulating film 8, and serves as a high resistance load element of the SRAM memory cell. This is for configuring R.

1O is an insulating film provided to cover the conductive layer 9 and fill the pores 6, and is used to alleviate the undulations of the upper part due to the provision of the pores 6.

Reference numeral 11 denotes an insulating film provided above the main surface of the well region 3 in the semiconductor element formation region, and is mainly used to constitute a gate insulating film of the MISFET.

11A is an opening provided by selectively removing a predetermined portion of #8 membrane 11, and conductive layer 9. This is for electrically connecting a conductive layer and a semiconductor region, which will be described later.

A conductive layer 12 has one end electrically connected to the conductive layer 9 and a semiconductor region to be described later through the opening 11A, and the other end provided on the insulating film 11 via the field insulating film 4 or simply on the insulating film 11. This layer is used to configure the gate electrode of the MI S FET.

Reference numeral 13 denotes a conductive layer which is integrated with the conductive layer 12 in the row direction serving as a switching element and is provided extending over the field insulating film 4, and is used to constitute a word line WL.

Reference numeral 14 denotes an n+ type semiconductor region provided on both sides of the conductive layer 12 via the insulating film 11 and on the main surface of the semiconductor substrate 1 below the conductive layer 12 in the opening 11A, and used as a source region or a drain region. So, MISFET
It is for configuring.

Memory cell flip-flop MISFETQI,Q
2 is mainly a well region 3. Insulating film 11, conductive layer 1
2 and a pair of semiconductor regions 14.

MISFETQs as switching elements of memory cells
t l QS2 is well region 3. It is composed of an insulating film 1/l, a conductive layer 12, and a pair of semiconductor regions 14.

Reference numeral 15 denotes an insulating film provided to cover the semiconductor element, and is used to electrically isolate the insulating film from the conductive layer provided above.

15A is an insulating film 11.15 on a predetermined upper part of the semiconductor region 14;
The connection hole is formed by selectively removing the insulating film 1.
5 for electrical connection with the conductive layer provided above.

16 has one end connected to the semiconductor region 14 through the connection hole 1.5A.
This is a conductive layer whose other end is electrically connected to the insulating film 15 and extends in the column direction, and is used to constitute a power line to which the data line DL, DL or Vss voltage is connected. be.

Next, a specific manufacturing method of this example will be explained.

4 to 9 are cross-sectional views of main parts showing the high resistance load element of the SRAM memory cell in each manufacturing process for explaining the manufacturing method of the embodiment of the present invention.

First, an n+ type semiconductor substrate 1 made of single crystal silicon is prepared. An n-type epitaxial layer 2 is laminated on top of this semiconductor substrate 1, and a P-type epitaxial layer 2 is formed on the main surface of the epitaxial layer 2.
A mold well region 3 is formed.

After that, an insulating film 4A is formed on the main surface of the well region 3,
A field insulating film 4 is selectively formed on the main surface of the well region 3 between the semiconductor element forming regions, and a P-type channel layer (region 5) is selectively formed on the main surface of the well region 3 below the field insulating film 4. Using silicon oxide film using oxidation technology, the film thickness is 0.04 to 0.05 [μm]
It is sufficient to form it to a certain extent. Then, a mask 17 is formed on the insulating film 4A, and a mask 18 is formed on the mask 17. f suf 1
The hole serves as an etching stopper for the mask 18.
For example, a polycrystalline silicon film formed by chemical vapor deposition (hereinafter referred to as CVD) technology is used, and the film thickness is 0.2 to 0.
The thickness may be about 3 [μm]. The mask 18 is an etching-resistant mask for forming pores, for example, using a silicon oxide film produced by CVD technology using high temperature and low pressure, and having a film thickness of 1.4 to 6 [μm]. ]. Thereafter, using the mask 18, the pores 6 are formed substantially in a predetermined main surface portion of the semiconductor substrate. This is formed by, for example, anisotropic etching technology, with a width of about 1.0 to 1.5 [μm] and a depth of about 4.0 to 1.5 [μm].
6.0 [μm] 81 guard - secretion punishment pull 1 i upper Ichiki 1, τ
As soon as possible, the semiconductor substrate 1 inside the pore 6 is removed. An insulating film 7 is formed on the epitaxial layer 2 and the main surface of the well region 3.
form. For example, a silicon oxide film formed by thermal oxidation technology is used, and the film thickness is set to 0.02 to 0.04 [μ
m].

After the process shown in FIG. 4, it is integrated with the mask 1.
An insulating film 8 is formed on the insulating film 7 above the pore 6 and along the inside of the pore 6.
form. In order to electrically isolate the semiconductor substrate 1 and the high-resistance load element, for example, silicon oxide film (CVD technology using high temperature and low pressure) is used, and the film thickness is 0.3. It may be formed to have a thickness of about 0.4 [μm]. Then, as shown in FIG. 5, a mask material 19 serving as an etching-resistant mask is formed on the insulating film 8. Then, as shown in FIG. This is because the etching rate varies depending on the introduction of impurities using ion implantation technology with extremely good directivity. It may be formed to a thickness of approximately [μm].

After the step shown in FIG. 5, impurities are selectively introduced into the mask material 19 at the top of the main surface of the semiconductor substrate 1 and at the bottom of the pores 6 using an ion implantation technique with extremely good directivity to form a defective layer. By selectively removing the defect layer, a mask 19A is formed on the insulating film 8 inside the pore 6, as shown in FIG. The impurity is, for example, I
Arsenic ions of the order of O" to lXl0" [at, oms/c+#] may be introduced using an ion implantation technique with an energy of about 50 [K e V ].

After the process shown in FIG. 6, as shown in FIG.
Then, the insulating films 8 and 7 at the bottom of the pore 6 are selectively removed to form an opening 8A to expose the main surface of the semiconductor substrate 1. When removing the insulating film 7, the insulating film 4A is not removed because the mask 17 is provided. The opening 8A is
By providing the mask 19A, it is possible to reliably form the insulating film 8 without damaging the other insulating films 8, regardless of whether isotropic etching or anisotropic etching is used.

After the step shown in FIG. 7, the mask 19A is selectively removed as shown in FIG. Note that the mask 19A does not need to be removed.

After the step shown in FIG. 8, a conductive layer 9 is formed, a part of which is electrically connected to the semiconductor substrate 1, on top of the insulation film 8 along the pores 6 to form a high resistance load element. . this is,
For example, a polycrystalline silicon film formed by CVD technology may be used to have a thickness of about 0.3 to 0.4 [tt m ]. Then, as shown in FIG. 9, an extreme R film 10 is formed on top of the conductive layer 9 so as to fill the pores 6. This can be done by using, for example, a silicon oxide film formed by CVD technology and having a thickness of about 0.5 to 0.7 [μml].

After the process shown in FIG. 9, unnecessary portions of the insulating film 10, conductive layer 9. selectively removing the mask 17 and the insulating film 4A;
An insulating film 11 is formed on the main surface of the well region 3, which will be a semiconductor element formation region. Thereafter, the SRAM of this embodiment is completed by performing normal manufacturing steps.

Note that a silicon nitride film may be used instead of the polycrystalline silicon film as the mask 19A for selectively removing the insulating films 8 and 7 at the bottom of the pore 6 to form the opening 8Δ. In this case (J), since the silicon nitride film has high insulation properties, its influence on the resistance value of the high resistance load element is smaller than that of the polycrystalline silicon film.

Furthermore, due to the parasitic MTS FET, the semiconductor substrate 1
In order to prevent unnecessary leakage between the semiconductor region 14 and the semiconductor region 14, a P-type channel stopper region may be provided on the main surface of the well region 3 where the pores 6 are formed.

[Effects and Effects] As explained above, according to the novel technical means disclosed in the present application, the following effects can be obtained.

(1) An insulating film is formed on the main surface of the semiconductor substrate inside the pore, and an etching-resistant mask is selectively applied to the top of the insulating film on the side of the pore using ion implantation technology with extremely good directivity. By forming this, the insulating film at the bottom of the pore can be reliably removed to form an opening without damaging anything else.

(2) An insulating film is formed on the main surface of the semiconductor substrate inside the pore, and an etching-resistant mask is selectively applied to the top of the insulating film on the side of the pore using ion implantation technology with extremely good directivity. By forming.

Either the isotropic etching technique or the anisotropic etching technique can be used to reliably remove the insulating film at the bottom of the pore and form the opening without causing damage to others.

(3) According to (1) and (2) above, the insulating film at the bottom of the pore is reliably removed and opened without causing any other damage.
Since the high resistance load element can be formed as a single portion, the electrical reliability of the high resistance load element can be improved.

(4) According to (1) to (3) above, the electrical reliability of high resistance load elements can be improved, so SRAM
It is possible to prevent a decrease in yield.

As mentioned above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above Examples, and within the scope of the gist thereof,
Of course, various modifications can be made.

For example, the above embodiments show that the present invention can be applied to SRA using pores.
Although we have described an example in which it is applied to M, the present invention is not limited to this, but it is also applicable to semiconductors in which it is necessary to reliably remove the insulating film at the bottom of the pores and grooves formed by etching from the main surface of the substrate. It can be applied to integrated circuit devices, etc.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing an SRAM memory cell for explaining the present invention in detail, and FIG. 2 is a main part plan view showing the SRAM memory cell for explaining the present invention in detail. FIG. 3 is a cross-sectional view taken along the line mm in FIG. FIG. 2 is a sectional view of a main part of a high resistance load element. In the figure, 1... semiconductor substrate, 2... epitaxial layer, 3... well region, 4... field insulating film, 5
... Channel stopper region, 6... Pore, 4A, 7
,8゜10.11.15...Insulating film, 8A, IIA・
・・Opening portion, 9, 12, 13. 16 ・・Conductive layer, 14
... Semiconductor region, 15A... Connection hole, 17, 18,
19A...Mask, 19...Mask material, WL...
・Word line, DL, DL...data line, R...high resistance load element, Q. It is a Qs-MISFET. Figure 1 ■CG Figure 2 Figure 3 Figure 4 ShiI Figure 5 Figure 7 (7('')/(/L+) Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] (1) Forming a pore extending inward from the main surface on the main surface of the semiconductor substrate, and forming an insulating film on the top of the main surface of the semiconductor substrate along the inside of the pore. forming a mask material for etching resistance on the top of the insulating film, selectively removing the mask material at the bottom of the pore to form a mask on the side of the pore, and using the mask. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: partially removing the insulating film formed at the bottom of the pore to expose the main surface of the semiconductor substrate. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the mask uses a polycrystalline silicon film or a silicon nitride film as the mask material. 3. The step of forming the mask uses a polycrystalline silicon film or a silicon nitride film as the mask material, and changes the etching rate of the mask material at the bottom of the pores using ion implantation technology with good directivity. A method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, characterized in that the masking material in portions is selectively removed. 4. The step of forming the pore is a step for forming a pore in which a high resistance load element constituting a flip-flop of a static random access memory is embedded. 3. A method for manufacturing a semiconductor integrated circuit device according to any one of Items 3 to 3.