CN208638793U - A kind of buried capacitor substrate - Google Patents
A kind of buried capacitor substrate Download PDFInfo
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- CN208638793U CN208638793U CN201820720151.8U CN201820720151U CN208638793U CN 208638793 U CN208638793 U CN 208638793U CN 201820720151 U CN201820720151 U CN 201820720151U CN 208638793 U CN208638793 U CN 208638793U
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Abstract
The utility model relates to a kind of buried capacitor substrates.The revealed buried layer substrate of the utility model includes first electrode layer and the second electrode lay;And the flexible material between the first electrode layer and the second electrode lay;Wherein the second electrode lay includes the first internal metal layer and the first outer metal layers, and first internal metal layer and first flexible material bond, and first outer metal layers are in conjunction with first internal metal layer.Buried capacitor substrate provided by the utility model and its processing method are not only not necessarily to propose that any particular/special requirement can smoothly complete production to the apparatus and process of plant substrate, and a circuit technique thereof can simultaneously process two plate bases, it can be promoted to make to produce, realize the advantageous effects achieved many things at one stroke.
Description
Technical field
The utility model relates generally to semiconductor processing technology, the embedment being especially built in capacity cell inside substrate
Formula capacitance technology.
Background technique
It is a kind of important of electronic system miniaturization that capacity cell, which is built in the buried capacitor technology inside substrate,
Solution is normally used in microphone and wearable electronic product, plays filtering, timing, decoupling and electric flux and deposits
The effect of storage.Its major advantage is that the stability of electronic system and reliability can be improved, and reduces the cost and diminution of product
The physical size of product.
Utility model content
That the capacitance material that industry (such as the offshore companies such as 3M, Faradflex) is developed at present provides is two layers of 35 μ
M or 70 μm of copper foil clips the ultra-thin dielectric material of a layer thickness≤20 μm (minimum generally can be 3 μm) (as shown in Figure 1, wherein
Dielectric substance be thick buried capacitor material with a thickness of 6 μm), which is usually prepared by industry supplied upstream manufacturer
The supplied materials of forming, but can also voluntarily be prepared by downstream packaging and testing manufacturer.
However, being processed to the capacitance material comprising ultra-thin dielectric material often very difficult.Due to shortage (such as
Glass fibre etc.) support construction is to capacitance material offer effectively support, in capacity substrate manufacture craft, often inevitably
The problems such as capacitance material fold, damaged and snap-gauge are encountered, are caused in systems such as equipment and the supplied materials disposition for facing plant substrate
When column require almost harsh condition, the prior art can not efficiently solve because capacitor layers fold, it is damaged with snap-gauge etc. due tos cause
Product processing procedure scrap or properties of product decline etc. technical problems.Also, to including interlayer soft (in addition to capacitance material)
Other stepped constructions processed, be also faced with same technical problem.
In view of this, the present invention provides a kind of buried capacitor substrate and its processing methods, to effectively solve by soft folder
Product processing procedure caused by the fold of layer (such as capacitor layers) is scrapped or the technical problems such as properties of product decline, to promote product
Yield.
One embodiment of the utility model provides a kind of method for processing buried layer substrate, and the method includes to form first to bury
Layer structure, it includes the first flexible material, first electrode layer and the second electrode lays, wherein the first electrode layer and described second
In the first flexible material two sides, the second electrode lay includes the first internal metal layer and the first outside metal for electrode layer setting
Layer, first internal metal layer and first flexible material bond, first outer metal layers and first inside
Metal layer is combined and is separated;The second buried structure is formed, it includes the second flexible material, third electrode layer and the 4th electrodes
Layer, wherein the third electrode layer and the 4th electrode layer are arranged in the second flexible material two sides, the 4th electrode layer packet
Containing the second internal metal layer and the second outer metal layers, second internal metal layer and second flexible material are bonded, institute
The second outer metal layers are stated in conjunction with second internal metal layer and are separated;Described the first of first buried structure
Supports loadboard is inserted between outer metal layers and second outer metal layers of second buried structure;Press described first
Buried structure, the supports loadboard and second buried structure pole, so that outside first outer metal layers and described second
Side metal layer is tightly engaged into the supports loadboard respectively;The successively shape in the first electrode layer of first buried structure
At the first figure route, the first supporting layer and the first metal layer, to form third buried structure;In second buried structure
Second graph route, the second supporting layer and second metal layer are sequentially formed on the third electrode layer, to form the 4th buried layer knot
Structure;The supports loadboard is removed, so that first outer metal layers are separated with first internal metal layer, and described second
Outer metal layers and second internal metal layer are separable;And it is based on the third buried structure and the 4th buried layer knot
It is configured to other figure routes.
Another embodiment according to the present utility model, first outer metal layers and the first internal metal layer knot
It can be mechanically decoupled after conjunction.
Another embodiment according to the present utility model, second outer metal layers and the second internal metal layer knot
It can be mechanically decoupled after conjunction.
Another embodiment according to the present utility model, a kind of buried layer substrate include: first electrode layer and the second electrode lay;With
And the flexible material between the first electrode layer and the second electrode lay;Wherein the second electrode lay includes first
Internal metal layer and the first outer metal layers, first internal metal layer and first flexible material bond, and described first
Outer metal layers are in conjunction with first internal metal layer.
Buried capacitor substrate provided by the utility model and its processing method are not only not necessarily to propose to appoint to the apparatus and process of plant substrate
What particular/special requirement can smoothly complete production, and a circuit technique thereof can simultaneously process two plate bases, to make to produce
It can be promoted, realize the advantageous effects achieved many things at one stroke.
Detailed description of the invention
Fig. 1 is shown in the prior art comprising the dielectric built-in capacity substrate of buried capacitor.
Fig. 2 (a)-(f) display forms the Double-side line process embodiment of built-in capacity substrate in the prior art.
Fig. 3 (a)-(e) display forms the single side route process embodiment of built-in capacity substrate in the prior art.
Fig. 4 is the schematic diagram of the utility model buried capacitor substrate.
Fig. 5 (a)-(g) is the schematic diagram that buried capacitor substrate is processed according to Fig.4,.
Specific embodiment
For the spirit for more fully understanding the utility model, it is made below in conjunction with the part preferred embodiment of the utility model
It further illustrates.
In the present specification, unless except being specified or being limited, the word of relativity for example: it is " central ", " longitudinal
", " lateral ", " front ", " rear ", " right ", " left ", " internal ", " external ", " lower ",
" higher ", " horizontal ", " vertical ", " being higher than ", " being lower than ", " top ", " lower section ", " top ", " bottom " and
Its derivative word (such as " horizontally ", " down ", " upward " etc.) should be construed to reference and be retouched under discussion
State or retouch in the accompanying drawings the direction shown.The word of these relativities is only used for the convenience in description, and is not required for this Shen
Please construction or operation in a certain direction.
The various embodiments of the utility model discussed in detail below.It, should although discussing specific implementation
Understand, these embodiments are for illustration purposes only.It is in related fields it will be recognized that without departing from this is practical
In the case where novel spirit and scope, other component and configuration can be used.
Fig. 2 (a)-(f) is to carry out Double-side line processing based on conventional built-in capacity substrate shown in FIG. 1 in the prior art
Process.Fig. 2 (a) is capacitor copper-clad plate, by electrode layer 201, counter electrode layer 203 and is located at electrode layer 201 and electricity relatively
Ultra-thin dielectric layer 202 between pole layer 203 is constituted, and wherein electrode layer 201 and counter electrode layer 203 are metal foil, wherein gold
Belonging to foil can be copper foil.Fig. 2 (b) is shown on the electrode layer 201 and counter electrode layer 203 of capacitor copper-clad plate shown in Fig. 2 (a) directly
Connect to form route, the route can from above and below two be formed simultaneously into direction.
Fig. 2 (c) shows two-sided process for pressing, that is, electrode layer 201 be formed by route formed interval insulant 205 and
Upper electrode layer 206, and formation interval insulant 205' and lower electrode layer 206' on route is formed by counter electrode layer 203.It needs
It should be noted that although interval insulant 205 and interval insulant 205' are just subsequent to guarantee with certain supportive once being formed
Processing will not further damage ultra-thin dielectric layer 202, but form interval insulant 205 and the process of interval insulant 205' itself and still can
Damage is brought to ultra-thin dielectric layer 202.
Next, as shown in Fig. 2 (d), for example, by the side such as filling perforation copper facing between electrode layer 201 and upper electrode layer 206
Formula forms metal contact 207, and correspondingly passes through same or similar side between counter electrode layer 203 and lower electrode layer 206'
The step of formula forms metal contact, and the formation metal contacts can carry out simultaneously.Fig. 2 (e) is shown in upper electrode layer 206 and lower electricity
Pattern is formed on the layer 206' of pole, further to form the upper substrate outer layer 208 as shown in Fig. 2 (f) on the pattern under
Substrate outer 208'.As one embodiment, the upper substrate outer layer 208 and lower substrate outer layer 208' can be green paint, nickel gold etc.
Material.
However, causing since ultra-thin dielectric layer 202 is soft materials and lacks effectively support in Fig. 2 (b) and Fig. 2 (c) institute
In the process shown, ultra-thin dielectric layer 202 is easily set to generate fold even damaged, and lead to the problems such as snap-gauge.Therefore,
Even if applying harsh operating condition, above-mentioned process remains difficult to avoid damage to soft ultra-thin dielectric layer 202, so as to cause production
Product processing procedure is scrapped or properties of product decline.
Fig. 3 (a)-(e) is to carry out the processing of single side route based on built-in capacity substrate for example shown in FIG. 1 in the prior art
Process, to be improved to Double-side line processing flow shown in Fig. 2 (a)-(f).Fig. 3 (a) is capacitor copper-clad plate, by electricity
Pole layer 301, counter electrode layer 303 and the ultra-thin dielectric layer 302 between electrode layer 301 and counter electrode layer 303 are constituted,
Wherein electrode layer 301 and counter electrode layer 303 are metal foil, and wherein metal foil can be copper foil.
Fig. 3 (b), which is shown, directly forms route on the only counter electrode layer 303 of the capacitor copper-clad plate shown in Fig. 3 (a), this
When electrode layer 301 is not processed.Fig. 3 (c) shows single side process for pressing, that is, is formed by route in counter electrode layer 303
Upper formation interval insulant 304 and lower electrode layer 305.Next, directly forming route on electrode layer 301 as shown in Fig. 3 (d).
Further, it is formed by route in electrode layer 301 and forms interval insulant 306 and upper electrode layer 307 shown in Fig. 3 (e).This
Field technical staff knows, further can form metal by mode shown in similar Fig. 2 (d) on the basis of Fig. 3 (e) and connect
Touching, and then the upper and lower substrates outer layer (being made of materials such as example green paint, nickel gold) as shown in Fig. 2 (f) is formed, therefore herein not
Add display in order to avoid repeating.
However, adding shown in Fig. 3 (b) and Fig. 3 (c) since ultra-thin dielectric layer 302 is soft materials and lacks effectively support
Work process still can frequently result in dielectric layer 302 and generate fold even breakage, therefore it is upper to be still unavoidable from Fig. 2 (a)-(f)
Problem is stated, is scrapped so as to cause product processing procedure or properties of product declines.
To solve the above-mentioned technical problem that is faced of the prior art, the application provides a kind of buried capacitor substrate and its processing side
Method.
Fig. 4 shows the buried capacitor substrate 400 of an embodiment of the present invention, by first electrode layer 401, internal metal layer
403, the ultra-thin dielectric layer 402 between first electrode layer 401 and internal metal layer 403 and outer metal layers 404 are constituted.
Wherein, outer metal layers 404 are bonded with internal metal layer 403 to collectively form the second electrode lay.At one of the utility model
In embodiment, outer metal layers 404 can be mechanically decoupled with internal metal layer 403.
In another embodiment, Fig. 5 (a)-(g) shows the method stream processed to buried capacitor substrate shown in Fig. 4 400
Journey.Buried capacitor substrate 500 in Fig. 5 (a) has structure identical with buried capacitor substrate 400 shown in Fig. 4.That is, buried capacitor substrate 500 by
First electrode layer 501, internal metal layer 503, the ultra-thin dielectric layer between first electrode layer 501 and internal metal layer 503
502 and outer metal layers 504 constitute, and outer metal layers 504 be bonded with internal metal layer 503 it is electric to collectively form second
Pole layer, and outer metal layers 504 can be separated with internal metal layer 503, the separation is including but not limited to mechanically decoupled.
Next, in Fig. 5 (b), by the identical buried capacitor substrate 500 of two block structures and buried capacitor substrate 500' with its outside gold
Belong to layer mode relative to each other to oppose placements, then the insertion supports loadboard 505 between buried capacitor substrate 500 and buried capacitor substrate 500',
Then buried capacitor substrate 500, buried capacitor substrate 500' and supports loadboard 505 are closely pressed.Wherein, the supports loadboard 505 is hard
Property material and be enough in process to comprising soft ultra-thin dielectric material capacitance material provide effectively support.As one
Embodiment, the supports loadboard 505 can be the resin material with glass fibre.Also, buried capacitor substrate 500 and buried capacitor substrate
Binding force between the respective outer metal layers of 500' and supports loadboard 505 is greater than and buried capacitor substrate 500 and buried capacitor substrate 500'
Binding force between respective internal metal layer.
Due to having obtained effective support of supports loadboard 505, Fig. 5 (c) can be from upper and lower both direction simultaneously to buried capacitor substrate
The respective first electrode layer of 500 and buried capacitor substrate 500' is processed to form route, without will cause appointing for ultra-thin dielectric layer
What is damaged.Further, as shown in Fig. 5 (d), apply two-sided process for pressing to be formed in 500 first electrode layer of buried capacitor substrate
Route on form interval insulant 506 and upper electrode layer 507, and be formed by simultaneously in the first electrode layer of buried capacitor substrate 500'
Interval insulant 506' and lower electrode layer 507' is formed on route.It should be noted that above-mentioned two-sided process for pressing is not limited in
It is formed to upper electrode layer 507 and lower electrode layer 507', can also repeatedly be pressed under effective support of supports loadboard 505, with
Multiple electrodes layer is formed simultaneously in upper and lower both direction, any damage without will cause ultra-thin dielectric layer.
After obtaining required upper electrode layer 507 and lower electrode layer 507', supports loadboard 505 can remove.Fig. 5 (e) is aobvious
The step of showing removal supports loadboard 505.In this step, due to buried capacitor substrate 500 and the respective outside gold of buried capacitor substrate 500'
The binding force belonged between layer and supports loadboard 505 is greater than itself and buried capacitor substrate 500 and the respective inner metal of buried capacitor substrate 500'
Binding force between layer, so that when buried capacitor substrate 500 and buried capacitor substrate 500' and supports loadboard 505 is mechanically decoupled, buried capacitor
Substrate 500 and the respective outer metal layers of buried capacitor substrate 500' be still tightly attached to 505 two sides of supports loadboard to respectively with buried capacitor base
Plate 500 and buried capacitor substrate 500' are mechanically decoupled.By mechanically decoupled, new structure 508, structure 508' and structure 509 are formed.Extremely
This, (being made of two outer metal layers and supports loadboard 505) structure 509 that support mission is completed can be sacrificed, and
Exit subsequent job step.
Fig. 5 (f) is shown on the basis of Fig. 5 (e) step resulting structures 508 directly on the internal metal layer of structure 508
Form route.At this point, it is hereby ensured that in Fig. 5 (g) due to the existing interval insulant with certain supportive of structure 508
Being formed will not be to ultra-thin Jie in the procedure of processing and subsequent any procedure of processing of lower section interval insulant 510 and electrode layer 511
Electric layer damages.Wherein, lower section interval insulant 510 is formed by shown in Fig. 5 (g) and can be according to the step of electrode layer 511
Formation interval insulant 205 shown in Fig. 2 (c) and implement the step of interval insulant 205', and can formed shown in Fig. 5 (g)
After lower section interval insulant 510 and electrode layer 511, continue to process according to step shown in Fig. 2 (d) -2 (f), until on being formed
Substrate outer and lower substrate outer layer.As one embodiment, the upper substrate outer layer and lower substrate outer layer can be green paint, nickel gold etc.
Material.
Buried capacitor base plate processing method provided by buried capacitor substrate and Fig. 5 (a)-(g) provided by Fig. 4 can effectively solve the problem that existing
There is the technical issues of technology is faced, and reduce the apparatus and process requirement to processor, and a linemen's can be used
Skill simultaneously processes two plate bases.
Meanwhile the proposed buried capacitor substrate of the utility model and its processing method are applicable not only to burying comprising ultra-thin dielectric layer
Hold substrate and its processing method, applies also for any including that the interior of soft layer buries substrate and its processing method.
The technology contents and technical characterstic of the utility model are described by above-mentioned related embodiment, however above-mentioned implementation
Example is only to implement the example of the utility model.Those skilled in the art are still potentially based on the teaching of the utility model and take off
Show and makees various replacements and modification without departing substantially from the spirit of the present invention.Therefore, the published embodiment of the utility model is not
Limit the scope of the utility model.On the contrary, being contained in the modification of the spirit and scope of claims and impartial setting is wrapped
It includes in the scope of the utility model.
Claims (5)
1. a kind of buried capacitor substrate, it includes:
First electrode layer and the second electrode lay;And
The first flexible material between the first electrode layer and the second electrode lay, it is characterised in that: wherein described
The second electrode lay includes the first internal metal layer and the first outer metal layers, first internal metal layer and described first soft
Material combines, and first outer metal layers are in conjunction with first internal metal layer.
2. buried capacitor substrate according to claim 1, wherein first flexible material is dielectric substance.
3. buried capacitor substrate according to claim 1, wherein the thickness of first internal metal layer is greater than outside described first
The thickness of side metal layer.
4. the buried capacitor substrate in -3 described in any one according to claim 1, wherein first internal metal layer and described first
Outer metal layers are copper foil.
5. buried capacitor substrate according to claim 1, wherein first outer metal layers and first internal metal layer
It can be mechanically decoupled.
Priority Applications (1)
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CN201820720151.8U CN208638793U (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201820720151.8U CN208638793U (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate |
Publications (1)
Publication Number | Publication Date |
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CN208638793U true CN208638793U (en) | 2019-03-22 |
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CN201820720151.8U Active CN208638793U (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate |
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