CN108419365A - A kind of buried capacitor substrate and processing method - Google Patents
A kind of buried capacitor substrate and processing method Download PDFInfo
- Publication number
- CN108419365A CN108419365A CN201810464194.9A CN201810464194A CN108419365A CN 108419365 A CN108419365 A CN 108419365A CN 201810464194 A CN201810464194 A CN 201810464194A CN 108419365 A CN108419365 A CN 108419365A
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- layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
Abstract
The present invention relates to a kind of buried capacitor substrate and processing methods.Disclosed buried layer substrate includes first electrode layer and the second electrode lay；And the flexible material between the first electrode layer and the second electrode lay；The wherein described the second electrode lay includes the first internal metal layer and the first outer metal layers, and first internal metal layer is bonded with first flexible material, and first outer metal layers are combined with first internal metal layer.
Description
Technical field
The present invention relates generally to semiconductor fabrication, and capacity cell is especially built in the electricity of the flush type inside substrate
Appearance technology.
Background technology
It is a kind of important of electronic system miniaturization that capacity cell, which is built in the buried capacitor technology inside substrate,
Solution is normally used in microphone and wearable electronic product, plays filtering, timing, decoupling and electric flux and deposits
The effect of storage.Its major advantage is that the stability and reliability of electronic system can be improved, and reduces cost and the diminution of product
The physical size of product.
Invention content
That the capacitance material that industry (such as the offshore companies such as 3M, Faradflex) is developed at present provides is two layers of 35 μ
M or 70 μm of copper foil clips the ultra-thin dielectric material of a layer thickness≤20 μm (minimum generally can be 3 μm) (as shown in Figure 1, wherein
Dielectric substance be thickness be 6 μm of thick buried capacitor material), which is usually prepared by industry supplied upstream manufacturer
The supplied materials of forming, but also can voluntarily be prepared by downstream packaging and testing manufacturer.
However, being processed to the capacitance material comprising ultra-thin dielectric material often very difficult.Due to shortage (such as
Glass fibre etc.) support construction is to capacitance material offer effectively support, in capacity substrate manufacture craft, often inevitably
The problems such as capacitance material fold, damaged and snap-gauge are encountered, are caused in systems such as equipment and the supplied materials disposition for facing plant substrate
When row require almost harsh condition, the prior art can not efficiently solve because capacitor layers fold, it is damaged with snap-gauge etc. due tos cause
Product processing procedure scrap or properties of product decline etc. technical problems.Also, to including the soft interlayer (in addition to capacitance material)
Other stepped constructions be processed, be also faced with same technical problem.
In view of this, a kind of buried capacitor substrate of present invention offer and its processing method, to effectively solve by soft interlayer (example
Such as capacitor layers) fold caused by product processing procedure scrap or properties of product decline etc. technical problems, to promote product yield.
One embodiment of the invention provides a kind of method of processing buried layer substrate, and the method includes to form the first buried layer knot
Structure, it includes the first flexible material, first electrode layer and the second electrode lays, wherein the first electrode layer and the second electrode
In the first flexible material both sides, the second electrode lay includes the first internal metal layer and the first outer metal layers, institute for layer setting
It states the first internal metal layer to bond with first flexible material, first outer metal layers and first internal metal layer
In conjunction with and separate；The second buried structure is formed, it includes the second flexible material, third electrode layer and the 4th electrode layers, wherein
In the second flexible material both sides, the 4th electrode layer includes in second for the third electrode layer and the 4th electrode layer setting
Side metal layer and the second outer metal layers, second internal metal layer are bonded with second flexible material, outside described second
Side metal layer is combined and is separated with second internal metal layer；In first outside metal of first buried structure
It is inserted into supports loadboard between layer and second outer metal layers of second buried structure；Press the first buried layer knot
Structure, the supports loadboard and second buried structure pole so that first outer metal layers and second outside metal
Layer is tightly engaged into the supports loadboard respectively；First is sequentially formed in the first electrode layer of first buried structure
Figure circuit, the first supporting layer and the first metal layer, to form third buried structure；Described the of second buried structure
Second graph circuit, the second supporting layer and second metal layer are sequentially formed on three electrode layers, to form the 4th buried structure；Removal
The supports loadboard so that first outer metal layers and the first inner metal layer separation, and second outside gold
It is separable with second internal metal layer to belong to layer；And it is formed based on the third buried structure and the 4th buried structure
Other figure circuits.
According to another embodiment of the invention, after first outer metal layers are combined with first internal metal layer
It can be mechanically decoupled.
According to another embodiment of the invention, after second outer metal layers are combined with second internal metal layer
It can be mechanically decoupled.
According to another embodiment of the present invention, a kind of buried layer substrate includes：First electrode layer and the second electrode lay；And position
Flexible material between the first electrode layer and the second electrode lay；The wherein described the second electrode lay includes the first inside
Metal layer and the first outer metal layers, first internal metal layer are bonded with first flexible material, first outside
Metal layer is combined with first internal metal layer.
Buried capacitor substrate provided by the invention and its processing method are not only not necessarily to propose any spy to the apparatus and process of plant substrate
Different requirement can smoothly complete production, and a circuit technique thereof can simultaneously be processed two plate bases, to make production capacity obtain
To be promoted, the advantageous effects achieved many things at one stroke are realized.
Description of the drawings
Fig. 1 shows to include the dielectric built-in capacity substrate of buried capacitor in the prior art.
Fig. 2 (a)-(f) displays form the Double-side line process embodiment of built-in capacity substrate in the prior art.
Fig. 3 (a)-(e) displays form the single side circuit process embodiment of built-in capacity substrate in the prior art.
Fig. 4 is the schematic diagram of buried capacitor substrate of the present invention.
Fig. 5 (a)-(g) is the schematic diagram that buried capacitor substrate is processed according to Fig.4,.
Specific implementation mode
To more fully understand the spirit of the present invention, it is made furtherly below in conjunction with the part preferred embodiment of the present invention
It is bright.
In the present specification, unless except through specifying or limiting, the word of relativity is for example：It is " central ", " longitudinal
", " lateral ", " front ", " rear ", " right ", " left ", " internal ", " external ", " lower ",
" higher ", " horizontal ", " vertical ", " being higher than ", " being less than ", " top ", " lower section ", " top ", " bottom " and
Its derivative word (such as " flatly ", " down ", " upward " etc.) should be construed to reference and be retouched under discussion
State or retouch in the accompanying drawings the direction shown.The word of these relativities is only used for the convenience in description, and is not required for this Shen
Please construction or operation in a certain direction.
The various embodiments of the present invention discussed in detail below.Although discussing specific implementation, but it is to be understood that
These embodiments are for illustration purposes only.It is in related field it will be recognized that without departing from the present invention essence
In the case of refreshing and protection domain, other component and configuration can be used.
Fig. 2 (a)-(f) is to carry out Double-side line processing based on conventional built-in capacity substrate shown in FIG. 1 in the prior art
Flow.Fig. 2 (a) is capacitance copper-clad plate, by electrode layer 201, counter electrode layer 203 and positioned at electrode layer 201 and electricity relatively
Ultra-thin dielectric layer 202 between pole layer 203 is constituted, and wherein electrode layer 201 and counter electrode layer 203 are metal foil, wherein gold
It can be copper foil to belong to foil.Fig. 2 (b) is shown on the electrode layer 201 and counter electrode layer 203 of capacitance copper-clad plate shown in Fig. 2 (a) directly
Connect to form circuit, the circuit can from above and below two to being formed simultaneously into direction.
Fig. 2 (c) shows two-sided process for pressing, that is, electrode layer 201 be formed by circuit formed interval insulant 205 and
Upper electrode layer 206, and it is formed by formation interval insulant 205' and lower electrode layer 206' on circuit in counter electrode layer 203.It needs
It should be noted that although interval insulant 205 and interval insulant 205' are just follow-up to ensure with certain supportive once being formed
Processing will not further damage ultra-thin dielectric layer 202, but the process itself for forming interval insulant 205 and interval insulant 205' still can
Damage is brought to ultra-thin dielectric layer 202.
Next, as shown in Fig. 2 (d), for example, by the side such as filling perforation copper facing between electrode layer 201 and upper electrode layer 206
Formula forms metal contact 207, and correspondingly passes through same or similar side between counter electrode layer 203 and lower electrode layer 206'
The step of formula forms metal contact, and the formation metal contacts can be carried out at the same time.Fig. 2 (e) is shown in upper electrode layer 206 and lower electricity
Pattern is formed on the layer 206' of pole, further to form the upper substrate outer layer 208 as shown in Fig. 2 (f) on the pattern under
Substrate outer 208'.As one embodiment, the upper substrate outer layer 208 and lower substrate outer layer 208' can be green paint, nickel gold etc.
Material.
However, since ultra-thin dielectric layer 202 is soft materials and lacks effectively support, cause in Fig. 2 (b) and Fig. 2 (c) institutes
In the process shown, ultra-thin dielectric layer 202 is easily set to generate fold even breakage, and lead to the problems such as snap-gauge.Therefore,
Even if applying harsh operating condition, above-mentioned process remains difficult to avoid damage to soft ultra-thin dielectric layer 202, so as to cause production
Product processing procedure is scrapped or properties of product decline.
Fig. 3 (a)-(e) is to carry out single side circuit processing based on built-in capacity substrate for example shown in FIG. 1 in the prior art
Flow, to be improved to Double-side line processing flow shown in Fig. 2 (a)-(f).Fig. 3 (a) is capacitance copper-clad plate, by electricity
Pole layer 301, counter electrode layer 303 and the ultra-thin dielectric layer 302 between electrode layer 301 and counter electrode layer 303 are constituted,
Wherein electrode layer 301 and counter electrode layer 303 are metal foil, and wherein metal foil can be copper foil.
Circuit is directly formed on Fig. 3 (b) displays only counter electrode layer 303 of the capacitance copper-clad plate shown in Fig. 3 (a), this
When electrode layer 301 is not processed.Fig. 3 (c) shows single side process for pressing, that is, is formed by circuit in counter electrode layer 303
Upper formation interval insulant 304 and lower electrode layer 305.Next, as shown in Fig. 3 (d), circuit is directly formed on electrode layer 301.
Further, it is formed by circuit in electrode layer 301 and forms interval insulant 306 and upper electrode layer 307 shown in Fig. 3 (e).This
Field technology personnel know, further can form metal by mode shown in similar Fig. 2 (d) on the basis of Fig. 3 (e) and connect
It touches, and then forms the upper and lower substrate outer (being made of materials such as example green paint, nickel gold) as shown in Fig. 2 (f), therefore herein not
Add display in order to avoid repeating.
However, since ultra-thin dielectric layer 302 is soft materials and lacks effectively support, add shown in Fig. 3 (b) and Fig. 3 (c)
Work process still can frequently result in dielectric layer 302 and generate fold even breakage, therefore be still unavoidable from the upper of Fig. 2 (a)-(f)
Problem is stated, is scrapped so as to cause product processing procedure or properties of product declines.
To solve the above-mentioned technical problem that the prior art is faced, a kind of buried capacitor substrate of the application offer and its processing side
Method.
Fig. 4 shows the buried capacitor substrate 400 of one embodiment of the invention, by first electrode layer 401, internal metal layer 403, position
Ultra-thin dielectric layer 402 and outer metal layers 404 between first electrode layer 401 and internal metal layer 403 are constituted.Wherein,
Outer metal layers 404 are bonded with internal metal layer 403 to collectively form the second electrode lay.In one embodiment of the application,
Outer metal layers 404 can be mechanically decoupled with internal metal layer 403.
In another embodiment, Fig. 5 (a)-(g) shows the method stream being processed to buried capacitor substrate shown in Fig. 4 400
Journey.Buried capacitor substrate 500 in Fig. 5 (a) has 400 identical structure of buried capacitor substrate as shown in fig. 4.That is, buried capacitor substrate 500 by
First electrode layer 501, internal metal layer 503, the ultra-thin dielectric layer between first electrode layer 501 and internal metal layer 503
502 and outer metal layers 504 constitute, and outer metal layers 504 be bonded with internal metal layer 503 it is electric to collectively form second
Pole layer, and outer metal layers 504 can be detached with internal metal layer 503, the separation is including but not limited to mechanically decoupled.
Next, in Fig. 5 (b), by the identical buried capacitor substrate 500 of two block structures and buried capacitor substrate 500' with its outside gold
Belong to layer mode relative to each other to oppose placements, then the insertion supports loadboard 505 between buried capacitor substrate 500 and buried capacitor substrate 500',
Then buried capacitor substrate 500, buried capacitor substrate 500' and supports loadboard 505 are closely pressed.Wherein, the supports loadboard 505 is hard
Property material and be enough in process to comprising soft ultra-thin dielectric material capacitance material provide effectively support.As one
Embodiment, the supports loadboard 505 can be the resin material with glass fibre.Also, buried capacitor substrate 500 and buried capacitor substrate
Binding force between the respective outer metal layers of 500' and supports loadboard 505 is more than and buried capacitor substrate 500 and buried capacitor substrate 500'
Binding force between respective internal metal layer.
Due to having obtained effective support of supports loadboard 505, Fig. 5 (c) can be from upper and lower both direction simultaneously to buried capacitor substrate
The respective first electrode layers of 500 and buried capacitor substrate 500' are processed to form circuit, without causing appointing for ultra-thin dielectric layer
What is damaged.Further, as shown in Fig. 5 (d), apply two-sided process for pressing to be formed in 500 first electrode layer of buried capacitor substrate
Circuit on form interval insulant 506 and upper electrode layer 507, and be formed by simultaneously in the first electrode layer of buried capacitor substrate 500'
Interval insulant 506' and lower electrode layer 507' is formed on circuit.It should be noted that above-mentioned two-sided process for pressing is not limited in
It is formed to upper electrode layer 507 and lower electrode layer 507', can also repeatedly be pressed under effective support of supports loadboard 505, with
Multiple electrodes layer is formed simultaneously in upper and lower both direction, any damage without causing ultra-thin dielectric layer.
After obtaining required upper electrode layer 507 and lower electrode layer 507', supports loadboard 505 can remove.Fig. 5 (e) is aobvious
The step of showing removal supports loadboard 505.In this step, due to buried capacitor substrate 500 and the respective outside gold of buried capacitor substrate 500'
The binding force belonged between layer and supports loadboard 505 is more than itself and buried capacitor substrate 500 and the respective inner metals of buried capacitor substrate 500'
Binding force between layer so that when by buried capacitor substrate 500 and buried capacitor substrate 500' mechanically decoupled with supports loadboard 505, buried capacitor
Substrate 500 and the respective outer metal layers of buried capacitor substrate 500' be still tightly attached to 505 both sides of supports loadboard to respectively with buried capacitor base
Plate 500 and buried capacitor substrate 500' are mechanically decoupled.By mechanically decoupled, new structure 508, structure 508' and structure 509 are formed.Extremely
This, (being made of two outer metal layers and supports loadboard 505) structure 509 of support mission, which is completed, to be sacrificed, and
Exit subsequent job step.
Fig. 5 (f) is shown on the basis of Fig. 5 (e) steps resulting structures 508 directly on the internal metal layer of structure 508
Form circuit.At this point, due to the existing interval insulant with certain supportive of structure 508, it is hereby ensured that in Fig. 5 (g)
It will not be to ultra-thin Jie in the procedure of processing and follow-up any procedure of processing of interval insulant 510 and electrode layer 511 below being formed
Electric layer damages.Wherein, lower section interval insulant 510 is formed by shown in Fig. 5 (g) and can be according to the step of electrode layer 511
Interval insulant 205 is formed shown in Fig. 2 (c) and is implemented the step of interval insulant 205', and can formed shown in Fig. 5 (g)
After lower section interval insulant 510 and electrode layer 511, continue to process according to the step shown in Fig. 2 (d) -2 (f), until on being formed
Substrate outer and lower substrate outer layer.As one embodiment, the upper substrate outer layer and lower substrate outer layer can be green paint, nickel gold etc.
Material.
The buried capacitor base plate processing method that the buried capacitor substrate and Fig. 5 (a)-(g) that Fig. 4 is provided are provided can effectively solve the problem that existing
There is the technical issues of technology is faced, and reduce the apparatus and process requirement to processor, and a linemen's can be used
Skill is simultaneously processed two plate bases.
Meanwhile buried capacitor substrate proposed by the invention and its processing method are applicable not only to include the buried capacitor base of ultra-thin dielectric layer
Plate and its processing method, it includes that the interior of soft layer buries substrate and its processing method to apply also for any type.
The technology contents and technical characterstic of the present invention are described by above-mentioned related embodiment, however above-described embodiment is only
To implement the example of the present invention.Those skilled in the art be still potentially based on teachings of the present invention and announcement and make it is various not
Away from the replacement and modification of spirit of that invention.Therefore, the published embodiment of the present invention is not limiting as the scope of the present invention.On the contrary
Ground, the modification and impartial setting for being contained in the spirit and scope of claims are included in the scope of the present invention.
Claims (9)
1. a kind of method of processing buried layer substrate, the method include：
The first buried structure is provided, it includes the first flexible material, first electrode layer and the second electrode lays, wherein first electricity
In first flexible material both sides, the second electrode lay includes the first inner metal for pole layer and the second electrode lay setting
Layer and the first outer metal layers, first internal metal layer are bonded with first flexible material, first outside metal
Layer is combined with first internal metal layer；
The second buried structure is provided, it includes the second flexible material, third electrode layer and the 4th electrode layers, wherein the third is electric
In second flexible material both sides, the 4th electrode layer includes the second inner metal for pole layer and the 4th electrode layer setting
Layer and the second outer metal layers, second internal metal layer are bonded with second flexible material, second outside metal
Layer is combined with second internal metal layer；
Press first buried structure, supports loadboard and second buried structure so that first outer metal layers and
Second outer metal layers are tightly engaged into the supports loadboard respectively；
The first figure line layer, the first supporting layer and the first gold medal are formed in the first electrode layer of first buried structure
Belong to layer, and forms on the third electrode layer of second buried structure second graph line layer, the second supporting layer and the
Two metal layers；And
Remove the supports loadboard so that first outer metal layers and the first inner metal layer separation, and described the
Two outer metal layers and the second inner metal layer separation, obtain processed buried layer substrate.
2. according to the method described in claim 1, wherein described first flexible material and second flexible material are dielectric
Material.
3. according to the method described in claim 1, the thickness of wherein described first internal metal layer is more than first outside gold
Belong to the thickness of layer, and the thickness of second internal metal layer is more than the thickness of second outer metal layers.
4. according to the method described in claim 3, wherein described first internal metal layer and first outer metal layers are copper
Foil, and second internal metal layer and second outer metal layers are copper foil.
5. according to the method described in claim 1, the wherein described first figure line layer and the second graph line layer are simultaneously
It is formed, first supporting layer and second supporting layer are formed simultaneously, and the first metal layer and the second metal layer
It is formed simultaneously.
6. according to the method described in claim 1, wherein described first supporting layer and second supporting layer are with glass fibers
The resin material of dimension.
7. according to the method described in claim 1, wherein before removing the supports loadboard, in the institute of first buried structure
It states and is further formed third figure line layer, third supporting layer and third metal layer on the first metal layer, and buried described second
It is further formed the 4th figure line layer, the 4th supporting layer and the 4th metal layer in the second metal layer of layer structure.
8. according to the method described in claim 7, the wherein described third figure line layer and the 4th figure line layer are simultaneously
It is formed, the third supporting layer and the 4th supporting layer are formed simultaneously, and the third metal layer and the 4th metal layer
It is formed simultaneously.
9. according to the method described in claim 1, the wherein described separation is mechanically decoupled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810464194.9A CN108419365A (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate and processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810464194.9A CN108419365A (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate and processing method |
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| CN108419365A true CN108419365A (en) | 2018-08-17 |
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| CN201810464194.9A Pending CN108419365A (en) | 2018-05-15 | 2018-05-15 | A kind of buried capacitor substrate and processing method |
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|---|---|---|---|---|
| US20060057420A1 (en) * | 2002-10-30 | 2006-03-16 | Toshiko Yokota | Copper foil provided with dielectric layer for forming capacitor layer, copper clad laminate for formation of capacitor layer using such such copper foil with dielectric layer, and method for producing such copper foil with dielectric layer for formation of capacitor layer |
| CN101541145A (en) * | 2009-03-17 | 2009-09-23 | 上海美维科技有限公司 | Processing method of ultra-thin core board in manufacturing of printed circuit board or integrated circuit package substrate |
| CN102651278A (en) * | 2012-05-24 | 2012-08-29 | 北京科技大学 | Embedded capacitor and preparation method thereof |
| CN104284530A (en) * | 2013-07-11 | 2015-01-14 | 上海美维科技有限公司 | Method for manufacturing printed circuit board or integrated circuit package substrate through coreless board process |
| CN106463468A (en) * | 2015-03-11 | 2017-02-22 | 野田士克林股份有限公司 | Thin film capacitor manufacturing method, integrated circuit mounting substrate, and semiconductor device provided with integrated circuit mounting substrate |
-
2018
- 2018-05-15 CN CN201810464194.9A patent/CN108419365A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060057420A1 (en) * | 2002-10-30 | 2006-03-16 | Toshiko Yokota | Copper foil provided with dielectric layer for forming capacitor layer, copper clad laminate for formation of capacitor layer using such such copper foil with dielectric layer, and method for producing such copper foil with dielectric layer for formation of capacitor layer |
| CN101541145A (en) * | 2009-03-17 | 2009-09-23 | 上海美维科技有限公司 | Processing method of ultra-thin core board in manufacturing of printed circuit board or integrated circuit package substrate |
| CN102651278A (en) * | 2012-05-24 | 2012-08-29 | 北京科技大学 | Embedded capacitor and preparation method thereof |
| CN104284530A (en) * | 2013-07-11 | 2015-01-14 | 上海美维科技有限公司 | Method for manufacturing printed circuit board or integrated circuit package substrate through coreless board process |
| CN106463468A (en) * | 2015-03-11 | 2017-02-22 | 野田士克林股份有限公司 | Thin film capacitor manufacturing method, integrated circuit mounting substrate, and semiconductor device provided with integrated circuit mounting substrate |
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Application publication date: 20180817 |