CN208547942U - Simulate vector-matrix multiplication operation circuit - Google Patents
Simulate vector-matrix multiplication operation circuit Download PDFInfo
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Abstract
The utility model provides a kind of simulation vector-matrix multiplication operation circuit, it is realized using programmable storage device array, in programmable semiconductor device array, the grid of all programmable semiconductor devices of every a line is connected to same analog voltage input, M row programmable semiconductor device is correspondingly connected with M analog voltage input, the drain electrode (or source electrode) of all programmable semiconductor devices of each column is connected to same bias voltage input, N column programmable semiconductor device is correspondingly connected with N number of bias voltage input, the source electrode (or drain electrode) of all programmable semiconductor devices of each column is connected to the same analog current output end, N column programmable semiconductor device is correspondingly connected with N number of analog current output end, by the threshold voltage for controlling programmable semiconductor device, each programmable semiconductor device is regarded as One variable equivalent simulation weight realizes matrix multiplication operation function.
Description
Technical field
The utility model relates to field of signal processing more particularly to a kind of simulation vector-matrix multiplication operation circuits.
Background technique
Matrix multiplication operation is widely used in the field of data mining such as image procossing, recommender system, Data Dimensionality Reduction, however,
Traditional Technical Architecture and wanting for current mass data processing is more and more only not suitable with based on serial manner by single computer
It asks.Therefore, expand the operation scale of matrix multiplication and reduce its operation time, be beneficial to meet matrix decomposition algorithm processing greatly
The requirement of scale data.However, matrix multiplication time complexity with higher, classical matrix multiplication by ask left matrix row with
The inner product of right rectangular array carrys out the product of solution matrix.This algorithm can be implemented as distributed algorithm, but its performance is not allowed to find pleasure in
It sees.Another form for matrix multiplication be the column of left matrix and the corresponding row of right matrix are subjected to apposition operation, thus
The partial results of matrix of consequence are obtained, are finally summed to various pieces result.Although in terms of parallelization, this algorithm and tradition
Algorithm, which is compared, has a very big promotion in efficiency, but there is also certain bottleneck, when matrix size is very big, arrives individual machine greatly
Memory cannot store left matrix a line and right matrix one column when, just cannot calculate.
Vector-matrix multiplication is a kind of common logic calculation function.In traditional von Neumann counting system structure, deposit
What reservoir and processor were a physically separate, it is attached between the two by data/address bus, executes vector-matrix multiplication operation
When, it is necessary first to vector sum matrix data to be processed is read out from memory, is transferred in processor, is patrolled
It collects and calculates, then calculated result is stored back into memory.This calculation consumes a large amount of data bus bandwidth and transmission
Power consumption.It is just more complicated for vector-matrix multiplication operation of analog signal.Firstly, it is necessary to by the methods of analog-to-digital conversion,
Analog signal is converted into digital signal, stores in memory, then carries out vector-Matrix Multiplication according to treatment process above
After method operation, then by the methods of digital-to-analogue conversion, digital signal is converted into analog signal.This simulation vector-matrix multiplication
Operation causes bigger power consumption and cost overhead, and process performance is bad.With big data apply rise, the transmission of mass data with
Processing has been further exacerbated by these problems.
Utility model content
In view of this, the utility model embodiment provides a kind of simulation vector-matrix multiplication operation circuit, solve existing
The bad problem of the process performance of matrix multiplication operation.
In order to achieve the above object, the utility model adopts the following technical solution:
A kind of simulation vector-matrix multiplication operation circuit, comprising: multiple analog voltage inputs, programmable semiconductor device
Part array, multiple first ends and multiple second ends；
In programmable semiconductor device array, the grid of all programmable semiconductor devices of every a line is connected to same
Analog voltage input, multirow programmable semiconductor device are correspondingly connected with multiple analog voltage inputs, and all of each column can
The drain electrode of programming semiconductor device is connected to same first end, and multiple row programmable semiconductor device is correspondingly connected with multiple first
End, the source electrode of all programmable semiconductor devices of each column are connected to same second end, multiple row programmable semiconductor device
Multiple second ends are correspondingly connected with, the threshold voltage of each programmable semiconductor device is adjustable；
Wherein, first end is bias voltage input, and second end is analog current output end,
Alternatively, first end is analog current output end, second end is bias voltage input.
In one embodiment, vector-matrix multiplication operation circuit is simulated further include:
Programmed circuit connects source electrode, the grid of each programmable semiconductor device in programmable semiconductor device array
And/or substrate, for regulating and controlling the threshold voltage of programmable semiconductor device.
In one embodiment, programmed circuit includes: voltage generation circuit and voltage control circuit, and voltage generation circuit is for producing
Raw program voltage or erasing voltage, program voltage for being loaded onto selected programmable semiconductor device by voltage control circuit
Source electrode, alternatively, erasing voltage to be loaded onto the grid or substrate of selected programmable semiconductor device, to regulate and control programmable half
The threshold voltage of conductor device.
In one embodiment, vector-matrix multiplication operation circuit is simulated further include:
Controller connects programmed circuit, is worked by control programming electric circuit, control the programmable semiconductor device devoted oneself to work
The threshold voltage of the quantity of part and each programmable semiconductor device.
In one embodiment, controller includes: ranks decoder, for gating programmable semiconductor device to be programmed.
In one embodiment, vector-matrix multiplication operation circuit is simulated further include: conversion equipment is connected to multiple simulation electricity
Before pressing input terminal, for multiple analog current input signals to be respectively converted into analog voltage input signal, transport to corresponding
Analog voltage input.
In one embodiment, conversion equipment includes multiple programmable semiconductor devices；
The grid of each programmable semiconductor device is connected with drain electrode, and is connected to corresponding analog voltage input；
The source electrode of each programmable semiconductor device accesses the first bias voltage.
In one embodiment, vector-matrix multiplication operation circuit is simulated further include: current detecting output circuit is connected to mould
After quasi- current output terminal, the analog current output signal for exporting to analog current output end is handled and exported.
In one embodiment, current detecting output circuit includes: multiple operational amplifiers, and the positive of each operational amplifier is defeated
Enter the second bias voltage of end connection, inverting input terminal is connected to corresponding analog current output end, also, inverting input terminal with it is defeated
A resistor or transistor are connected between outlet.
In one embodiment, programmable semiconductor device uses floating transistor.
The utility model also provides a kind of storage device, including above-mentioned simulation vector-matrix multiplication operation circuit.
The utility model also provides a kind of chip, including above-mentioned simulation vector-matrix multiplication operation circuit.
Simulation vector-matrix multiplication operation circuit provided by the utility model, by being adjusted in advance according to certain rule dynamic
Save the threshold voltage V of each programmable semiconductor deviceTH, each programmable semiconductor device can be regarded as to a variable equivalent simulation
Weight, is equivalent to one analogue data of storage, and programmable semiconductor device array then stores an analogue data array；Circuit work
When making, a column analog voltage vector or a column are applied by the analog voltage vector that the converted device of analog current vector is converted into
To the grid of corresponding programmable semiconductor device, the grid of programmable semiconductor device is made to obtain a voltage signal, source electrode (or leakage
Pole) one analog current output signal of output, according to programmable semiconductor device characteristic, each programmable semiconductor device source electrode
The analog current output signal of (or drain electrode) output is equal to voltage multiplied by weight, because of all programmable semiconductor device of each column
The source electrode (or drain electrode) of part is connected to the same analog current output end, according to Kirchhoff's law, so in simulation electricity
The analog current output signal for flowing output end is the sum of the source electrode of the column all programmable semiconductor devices (or drain electrode) electric current, i.e.,
For the grid voltage of the column all programmable semiconductor devices and the sum of products of weight, multiple analog current output ends export multiple grid
The sum of products of pressure and weight realizes matrix multiplication operation function；The utility model is real using programmable semiconductor device array
Vector-matrix multiplication operation is now simulated, because programmable semiconductor device integrated level height, fast response time, low in energy consumption, is adopted
Analog-to-digital conversion, digital-to-analogue are effectively reduced with simulation vector-matrix multiplication operation circuit that programmable semiconductor device array is realized
Brings expense, the process performances such as conversion, data transmission improve.
Also, simulation vector-matrix multiplication operation circuit provided by the utility model can be compiled when being in idle condition
Journey array of semiconductor devices may be used as flash memory or Electrically Erasable Programmable Read-Only Memory, realize answering for electric elements
With raising element utilization efficiency saves the hardware cost of integrated circuit.
In addition, simulation vector-matrix multiplication operation circuit provided by the utility model, by analog current output end it
Current detecting output circuit is set afterwards, the complete electric current of operation is accurately handled and exported, or is connected to next may be programmed and partly leads
The input of body device array can effectively improve output current precision.
Integrated simulation vector-matrix multiplication operation circuit on storage device provided by the utility model is directly filled in storage
Vector-matrix multiplication operation is carried out to analog signal in setting, the transfer data between memory and processor is not needed, mentions
High disposal performance reduces power consumption and cost overhead.
For the above and other objects, features and advantages of the utility model can be clearer and more comprehensible, preferable reality is cited below particularly
Example is applied, and cooperates institute's accompanying drawings, is described in detail below.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Figure 1A is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit first embodiment；
Figure 1B is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit second embodiment；
Fig. 2 is the floating gate transistor structures in a kind of simulation vector-matrix multiplication operation circuit of the utility model embodiment
Figure；
Fig. 3 A is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit 3rd embodiment；
Fig. 3 B is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit fourth embodiment；
Fig. 4 is the schematic diagram that the utility model simulates the 5th embodiment of vector-matrix multiplication operation circuit；
Fig. 5 is a kind of flow chart for simulating vector-matrix multiplication operation circuit control method of the utility model embodiment.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
Vector-matrix multiplication is a kind of common logic calculation function, existing simulation vector-matrix multiplication operation property
Energy, power consumption and cost are to be improved.Simulation vector-matrix multiplication operation circuit provided by the utility model can be compiled by adjusting
The threshold voltage of journey semiconductor devices regards each programmable semiconductor device as a variable equivalent simulation weight, quite
In analog matrix data, analog voltage is applied to programmable semiconductor device array, realizes matrix multiplication operation function, circuit knot
Structure is simple, component number is few, fast response time, low in energy consumption, substantially reduces the bands such as analog-to-digital conversion, digital-to-analogue conversion, data transmission
The expense come, process performance greatly improve.
Figure 1A is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit first embodiment.Such as Figure 1A
Shown, which includes: M analog voltage input, a M row × N column programmable half
Conductor device array, N number of first end and N number of second end, wherein first end is bias voltage input, and second end is simulation
Current output terminal.
In the programmable semiconductor device array, the grid of all programmable semiconductor devices of every a line is connected to together
One analog voltage input, M row programmable semiconductor device are correspondingly connected with M analog voltage input, and all of each column can
The drain electrode of programming semiconductor device is connected to same bias voltage input, and N column programmable semiconductor device is correspondingly connected with N number of
Bias voltage input, the source electrode of all programmable semiconductor devices of each column are connected to the same analog current output
End, N column programmable semiconductor device are correspondingly connected with N number of analog current output end, wherein the threshold of each programmable semiconductor device
Threshold voltage is adjustable.N is the positive integer more than or equal to zero, and M is the positive integer more than or equal to zero, and M and N can be equal, can also
With differ.
By foregoing circuit connection type, the topological structure of grid coupling, source electrode summation is formed.
Wherein, by advance according to the threshold voltage V of each programmable semiconductor device of certain regular dynamic regulationTH, can incite somebody to action
Each programmable semiconductor device regards a variable equivalent simulation weight as and (is denoted as WK, f, wherein 0 < k < M and 0 < j < N difference
Represent line number and row number), it is equivalent to one analogue data of storage, and programmable semiconductor device array then stores a simulation number
According to array
When circuit works, by a column analog voltage signal V1~VMIt is respectively applied to M row programmable semiconductor device, wherein
The grid of line k all programmable semiconductor devices obtains an analog voltage signal Vk, one bias voltage V of drain electrode inputb, source
Distinguish output current signal I in poleK, 1~IK, N, according to the characteristic of programmable semiconductor device, each programmable semiconductor of I=V × W
The source electrode output electric current of device is equal to grid voltage multiplied by the weight of the programmable semiconductor device, i.e. IK, 1=VkWK, 1, IK, N=
VkWK, N, because the source electrode of all programmable semiconductor devices of each column is connected to the same analog current output end, according to
Kirchhoff's law, so in the electric current I of the analog current output endjFor the source electrode electricity of the column all programmable semiconductor devices
The sum of stream, asMultiple analog current output ends export multiple electric currents andRealize matrix multiplication operation function.
The utility model realizes simulation vector-matrix multiplication operation using programmable semiconductor device array, because can compile
It is journey semiconductor devices integrated level height, fast response time, low in energy consumption, thus the simulation realized using programmable semiconductor device to
Amount-matrix multiplication operation circuit effectively reduces the brings expenses such as analog-to-digital conversion, digital-to-analogue conversion, data transmission, treatability
It can greatly improve.
Figure 1B is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit second embodiment.Such as Figure 1B
It is shown, the simulation vector-matrix multiplication operation circuit include: M analog voltage input, a M row × N column it is programmable
Array of semiconductor devices, N number of first end and N number of second end, wherein first end is analog current output end, and second end is inclined
Set voltage input end.
In the programmable semiconductor device array, the grid of all programmable semiconductor devices of every a line is connected to together
One analog voltage input, M row programmable semiconductor device are correspondingly connected with M analog voltage input, and all of each column can
The source electrode of programming semiconductor device is connected to same bias voltage input, and N column programmable semiconductor device is correspondingly connected with N number of
Bias voltage input, the drain electrode of all programmable semiconductor devices of each column are connected to the same analog current output
End, N column programmable semiconductor device are correspondingly connected with N number of analog current output end, wherein the threshold of each programmable semiconductor device
Threshold voltage is adjustable.N is the positive integer more than or equal to zero, and M is the positive integer more than or equal to zero, and M and N can be equal, can also
With differ.
By foregoing circuit connection type, the topological structure of grid coupling, drain electrode summation is formed.
Wherein, by advance according to the threshold voltage V of each programmable semiconductor device of certain regular dynamic regulationTH, can incite somebody to action
Each programmable semiconductor device regards a variable equivalent simulation weight as and (is denoted as WK, f, wherein 0 < k < M and 0 < j < N difference
Represent line number and row number), it is equivalent to one analogue data of storage, and programmable semiconductor device array then stores a simulation number
According to array
When circuit works, by a column analog voltage signal V1~VMIt is respectively applied to M row programmable semiconductor device, wherein
The grid of line k all programmable semiconductor devices obtains an analog voltage signal Vk, one bias voltage V of source electrode inputb, leakage
Distinguish output current signal I in poleK, 1~IK, N, wherein according to the characteristic of programmable semiconductor device, I=V × W each be may be programmed
The drain electrode output electric current of semiconductor devices is equal to grid voltage multiplied by the weight of the programmable semiconductor device, i.e. IK, 1=VkWK, 1, IK, N
=VkWK, N, because the drain electrode of all programmable semiconductor devices of each column is connected to the same analog current output end, root
According to Kirchhoff's law, so in the electric current I of the analog current output endjFor the drain electrode of the column all programmable semiconductor devices
The sum of electric current, asMultiple analog current output ends export multiple electric currents andRealize matrix multiplication operation function.
The utility model realizes simulation vector-matrix multiplication operation using programmable semiconductor device array, because can compile
It is journey semiconductor devices integrated level height, fast response time, low in energy consumption, thus the simulation realized using programmable semiconductor device to
Amount-matrix multiplication operation circuit effectively reduces the brings expenses such as analog-to-digital conversion, digital-to-analogue conversion, data transmission, treatability
It can greatly improve.
In addition, due to the gate source voltage V of programmable semiconductor deviceGSDetermine the output electric current of programmable semiconductor device,
The output electric current of programmable semiconductor device is very sensitive to source voltage, may cause calculating error, and the present embodiment uses
The topological structure of grid coupling, drain electrode summation will not cause to calculate error, can be improved even if source voltage fluctuates
The precision of calculating.
In the first embodiment or the second embodiment, optionally, which can use floating gate crystal
Pipe realizes that the structure of floating transistor is as shown in Fig. 2, the floating transistor includes substrate, insulating layer, grid G, source S, drain electrode
D and floating gate F, floating gate are set between grid and insulating layer, and insulating layer is set between floating gate and substrate, for protecting floating gate
In electronics will not leak, can store electronics in floating gate；By adjusting the electron amount in floating gate, the dynamic regulation floating gate is brilliant
The threshold voltage of body pipe can be regarded as a variable equivalent simulation power due to this architectural characteristic of floating transistor
Weight, stores an analogue data.
In the first embodiment or the second embodiment, optionally, which can also be wrapped
It includes:
Programmed circuit connects source electrode, the grid of each programmable semiconductor device in programmable semiconductor device array
And/or substrate, for regulating and controlling the threshold voltage of programmable semiconductor device.
Preferably, programmed circuit includes: voltage generation circuit and voltage control circuit, and voltage generation circuit is for generating volume
Journey voltage or erasing voltage, voltage control circuit are used to for program voltage being loaded onto the source of selected programmable semiconductor device
Pole, alternatively, erasing voltage to be loaded onto the grid or substrate of selected programmable semiconductor device, to regulate and control programmable semiconductor
The threshold voltage of device.
Specifically, programmed circuit utilizes thermoelectron injection effect, according to programmable semiconductor device threshold voltage demand number
According to, to the source electrode of programmable semiconductor device apply high voltage, by channel electrons accelerate to high speed, to increase programmable semiconductor
The threshold voltage of device.
Also, programmed circuit utilizes tunneling effect, according to programmable semiconductor device threshold voltage demand data, Xiang Kebian
The grid or substrate of journey semiconductor devices apply high voltage, to reduce the threshold voltage of programmable semiconductor device.
In the first embodiment or the second embodiment, optionally, simulation vector-matrix multiplication operation circuit can also be wrapped
It includes:
Controller connects programmed circuit, is worked by control programming electric circuit, adjust the programmable semiconductor device devoted oneself to work
The threshold voltage of the quantity of part and each programmable semiconductor device, to adapt to-matrix multiplication operation demand.
Preferably, controller includes: ranks decoder, for gating programmable semiconductor device to be programmed.
In the first embodiment or the second embodiment, optionally, which can also be wrapped
Include: bias-voltage generating circuit is input to bias voltage input for generating preset bias voltage, it is to be understood that
Simulation vector-matrix multiplication operation the circuit can also be not provided with bias-voltage generating circuit, by multiplexing programmed circuit
Voltage generation circuit controls the voltage generation circuit and generates preset bias voltage, is input to bias voltage input.
Fig. 3 A is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit 3rd embodiment, the simulation
Vector-matrix multiplication operation circuit is including full content in second embodiment shown in first embodiment shown in Figure 1A or Figure 1B
On the basis of, it can also include: conversion equipment 5, conversion equipment 5 is connected to before multiple analog voltage inputs, and being used for will be multiple
Analog current input signal is respectively converted into analog voltage input signal, transports to corresponding analog voltage input.
In an alternative embodiment, conversion equipment 5 includes multiple programmable semiconductor devices.
The grid of each programmable semiconductor device is connected with drain electrode, and is connected to corresponding analog voltage input.
The source electrode of each programmable semiconductor device accesses the first bias voltage.
Wherein it is possible to understand, the first bias voltage of source electrode access can be ground voltage, i.e. the source electrode is grounded.
In the embodiment, the grid of each programmable semiconductor device is connected with drain electrode, for receiving simulation electricity
Flow input signal.
Optionally, floating transistor can be used in programmable semiconductor device in conversion equipment 5.
When circuit works, by a column analog current input signal Iin~IinColumn simulation electricity is converted to by conversion equipment 5
Press input signal V1~VMAfter be respectively applied to M row programmable semiconductor device.By the way that conversion equipment is arranged, so that this is practical new
Simulation vector-matrix multiplication operation circuit in type embodiment is not only adapted to analog voltage input signal, is further adapted for analog current
Input signal can increase simulation vector-matrix multiplication operation circuit applicability.
Fig. 3 B is the schematic diagram that the utility model simulates vector-matrix multiplication operation circuit fourth embodiment, the simulation
Vector-matrix multiplication operation circuit is including full content in second embodiment shown in first embodiment shown in Figure 1A or Figure 1B
On the basis of, it can also include: conversion equipment 5, conversion equipment 5 is connected to before multiple analog voltage inputs, and being used for will be multiple
Analog current input signal is respectively converted into analog voltage input signal, transports to corresponding analog voltage input.
In an alternative embodiment, conversion equipment 5 includes multiple resistors, multiple resistors and multiple analog voltages
Input terminal connects one to one.
Each resistor one end connects corresponding analog voltage input, and the other end connects the first bias voltage, wherein can
With understanding, the first bias voltage can be ground voltage, i.e. the other end ground connection of resistor.
When circuit works, by a column analog current input signal Iin1~IinMColumn simulation is converted to by conversion equipment 5
Voltage input signal V1~VMAfter be respectively applied to M row programmable semiconductor device.
By the way that conversion equipment is arranged, so that simulation vector-matrix multiplication operation circuit in the utility model embodiment is not
Only it is suitable for analog voltage input signal, is further adapted for analog current input signal, simulation vector-matrix multiplication operation electricity can be increased
The applicability on road.
It is worth noting that the implementation of above-mentioned conversion equipment is a kind of example, it is all be able to achieve electric current is defeated
Enter that signal is converted to the circuit structure of voltage input signal or circuit element is used equally for implementing the conversion equipment, such as metal half
Conductor field effect transistor.
Fig. 4 is the schematic diagram that the utility model simulates the 5th embodiment of vector-matrix multiplication operation circuit.Such as Fig. 4 institute
Show, which includes above-mentioned first embodiment to complete described in any one of fourth embodiment
On the basis of portion's content, it can also include: current detecting output circuit 6, be connected to after analog current output end, for mould
The analog current output signal of quasi- current output terminal output is handled and exported.
Wherein, it is accurately handled and is exported by the current detecting output circuit electric current complete to operation, or be connected to
The input of next programmable semiconductor array can effectively realize that electric current precisely exports.
In an alternative embodiment, current detecting output circuit may include: multiple operational amplifiers, each described
The normal phase input end of operational amplifier connects the second bias Vs, and inverting input terminal is connected to the corresponding analog current output
End, also, a resistor or transistor are connected between inverting input terminal and output end etc..
Wherein, which is generally grounded, which exists the voltage control of analog current output end
It is equal with the voltage of normal phase input end, for guaranteeing the gate source voltage V of programmable semiconductor deviceGSOnly by the programmable semiconductor
The corresponding input voltage control of device, so that the output end voltage of operational amplifier represents respective column programmable semiconductor device
The amplitude of the output electric current of part.
The above is only illustrate each mould in simulation vector-matrix multiplication operation circuit provided by the embodiment of the utility model
The specific structure of block, in the specific implementation, the specific structure of above-mentioned each module are not limited on provided by the embodiment of the utility model
State structure, can also be skilled person will appreciate that other structures, be not limited thereto.
The embodiment of the present application also provides a kind of simulation vector-matrix multiplication operation circuit control methods, can be used for
The described simulation vector-matrix multiplication operation circuit of the various embodiments described above is controlled, as described in the following examples.Due to control
The principle that method solves the problems, such as is similar to foregoing circuit, therefore the implementation of control method may refer to the implementation of foregoing circuit, weight
Multiple place repeats no more.
Simulation vector-matrix multiplication operation circuit control method as shown in figure 5, for control it is above-mentioned it is each simulate to
Amount-matrix multiplication operation circuit, control method include:
Step S430: multiple analog voltage input signals are applied to corresponding row by multiple analog voltage inputs and are owned
The grid of programmable semiconductor device.
Step S440: a default bias voltage is applied to respective column all programmable by multiple bias voltage inputs
Semiconductor devices.
Wherein, in the step, when simulation vector-matrix multiplication operation circuit is using the topology of grid coupling, source electrode summation
When structure, default bias voltage is applied to the drain electrode of programmable semiconductor device；When simulation vector-matrix multiplication operation circuit is adopted
When the topological structure summed with grid coupling, drain electrode, default bias voltage is applied to the source electrode of programmable semiconductor device.
Step S450: by the corresponding multiple analog current output ends of multiple row programmable semiconductor device, multiple moulds are obtained
Quasi- current output signal.
Optionally, if input signal is analog current input signal, conversion equipment 5 is first passed through multiple analog currents are defeated
Enter signal and be respectively converted into multiple analog voltage input signals, then analog voltage input signal is transported into analog voltage input,
Carry out matrix-multiplying.
Optionally, each to arrange obtained analog current output signal are as follows: the analog voltage of the every a line being connected with the column
The product of the weight of each programmable semiconductor device of input signal with the column is summed again.
Preferably, vector-matrix multiplication operation circuit control method is simulated further include:
Step S420: regulate and control the threshold voltage of programmable semiconductor device by programmed circuit.
Preferably, control method further include:
Step S410: the digit demand based on matrix multiplication operation, programmable half to be devoted oneself to work using controller control
The quantity of conductor device.
The utility model embodiment also provides a kind of storage device, including above-mentioned simulation vector-matrix multiplication operation circuit.
Integrated simulation vector-matrix multiplication operation circuit on the storage device directly carries out vector-to analog signal in the storage device
Matrix multiplication operation, does not need the transfer data between memory and processor, improves process performance, reduce power consumption at
This expense.
Preferably, which is flash memory or Electrically Erasable Programmable Read-Only Memory.
Preferably, which is NOR type flash memory.
The utility model embodiment also provides a kind of chip, including above-mentioned simulation vector-matrix multiplication operation circuit.
In the various embodiments described above, floating transistor can be SONOS type floating transistor (floating-
Gatetransistor), Split type floating transistor (Split-gate floating-gate transistor) or charge type
Floating transistor (Charge-trapping floating-gate transistor), including but not limited to this, it is all can
The utility model embodiment is belonged to by adjusting the transistor that electron amount adjusts transistor threshold voltage itself in floating gate
Protection scope.
The utility model embodiment simulates vector-matrix multiplication operation circuit, control method, storage device and chip,
It can be used in the terminals such as computer, mobile phone, tablet computer executing related operation, for the simulation vector-matrix multiplication operation electricity
Other essential component parts on road are not do herein superfluous it will be apparent to an ordinarily skilled person in the art that have
It states, also should not be used as limitations of the present invention.
By adjusting the threshold voltage of programmable semiconductor device, regarding each programmable semiconductor device as one be can be changed
Equivalent simulation weight, be equivalent to analog matrix data, to programmable semiconductor device array apply analog voltage, realize matrix
Multiplying function, circuit structure is simple, component number is few, fast response time, low in energy consumption, substantially reduces analog-to-digital conversion, number
The brings expenses such as mould conversion, data transmission, effectively increase the process performance of computing circuit.
Also, simulation vector-matrix multiplication operation circuit provided by the utility model can be compiled when being in idle condition
Journey array of semiconductor devices may be used as flash memory or Electrically Erasable Programmable Read-Only Memory, realize answering for electric elements
With raising element utilization efficiency saves the hardware cost of integrated circuit.
Integrated simulation vector-matrix multiplication operation circuit on storage device provided by the utility model is directly filled in storage
Vector-matrix multiplication operation is carried out to analog signal in setting, the transfer data between memory and processor is not needed, mentions
High disposal performance reduces power consumption and cost overhead.
Specific embodiment is applied in the utility model to be expounded the principles of the present invention and embodiment, with
The explanation of upper embodiment is merely used to help understand the method and its core concept of the utility model；Meanwhile for this field
Those skilled in the art, based on the idea of the present invention, there will be changes in the specific implementation manner and application range, comprehensive
Upper described, the content of the present specification should not be construed as a limitation of the present invention.
Claims (10)
1. a kind of simulation vector-matrix multiplication operation circuit characterized by comprising multiple analog voltage inputs may be programmed
Array of semiconductor devices, multiple first ends and multiple second ends；
In the programmable semiconductor device array, the grid of all programmable semiconductor devices of every a line is connected to same
Analog voltage input, multirow programmable semiconductor device are correspondingly connected with multiple analog voltage inputs, and all of each column can
The drain electrode of programming semiconductor device is connected to same first end, and multiple row programmable semiconductor device is correspondingly connected with multiple first
End, the source electrode of all programmable semiconductor devices of each column are connected to same second end, multiple row programmable semiconductor device
Multiple second ends are correspondingly connected with, the threshold voltage of each programmable semiconductor device is adjustable；
Wherein, the first end be bias voltage input, the second end be analog current output end, realize grid coupling,
The topological structure of source electrode summation；
Alternatively, the first end be analog current output end, the second end be bias voltage input, realize grid coupling,
Drain the topological structure summed.
2. simulating vector-matrix multiplication operation circuit according to claim 1, which is characterized in that further include:
Programmed circuit, connect the source electrode of each programmable semiconductor device in programmable semiconductor device array, grid and/or
Substrate, for regulating and controlling the threshold voltage of programmable semiconductor device.
3. simulating vector-matrix multiplication operation circuit according to claim 2, which is characterized in that the programmed circuit includes:
Voltage generation circuit and voltage control circuit, the voltage generation circuit are described for generating program voltage or erasing voltage
Voltage control circuit is used to for the program voltage being loaded onto the source electrode of selected programmable semiconductor device, alternatively, will erasing
Voltage-drop loading to selected programmable semiconductor device grid or substrate, with regulate and control programmable semiconductor device threshold value electricity
Pressure.
4. simulating vector-matrix multiplication operation circuit according to claim 3, which is characterized in that further include:
Controller connects the programmed circuit, is worked by controlling the programmed circuit, controls devote oneself to work programmable and partly leads
The threshold voltage of the quantity of body device and each programmable semiconductor device.
5. simulating vector-matrix multiplication operation circuit according to claim 4, which is characterized in that the controller includes: row
Column decoder, for gating programmable semiconductor device to be programmed.
6. simulating vector-matrix multiplication operation circuit according to claim 1, which is characterized in that further include: conversion equipment,
It is connected to before multiple analog voltage inputs, for multiple analog current input signals to be respectively converted into analog voltage
Input signal transports to the corresponding analog voltage input.
7. simulating vector-matrix multiplication operation circuit according to claim 6, which is characterized in that the conversion equipment includes
Multiple programmable semiconductor devices；
The grid of each programmable semiconductor device is connected with drain electrode, and is connected to the corresponding analog voltage input
End；
The source electrode of each programmable semiconductor device accesses the first bias voltage.
8. simulating vector-matrix multiplication operation circuit according to claim 1, which is characterized in that further include: current detecting is defeated
Circuit out is connected to after the analog current output end, and the analog current for exporting to the analog current output end is defeated
Signal is handled and exported out.
9. simulating vector-matrix multiplication operation circuit according to claim 8, which is characterized in that the current detecting output
Circuit includes: multiple operational amplifiers, and the normal phase input end of each operational amplifier connects the second bias voltage, and reverse phase is defeated
Enter end and be connected to the corresponding analog current output end, also, connected between inverting input terminal and output end a resistor or
Transistor.
10. according to claim 1 to any one of 9 simulation vector-matrix multiplication operation circuits, which is characterized in that it is described can
Programming semiconductor device uses floating transistor.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108763163A (en) * | 2018-08-02 | 2018-11-06 | 北京知存科技有限公司 | Simulate vector-matrix multiplication operation circuit |
| CN110276048A (en) * | 2019-05-25 | 2019-09-24 | 南京惟心光电系统有限公司 | A kind of control method of matrix-vector multiplication array |
| CN112835552A (en) * | 2021-01-26 | 2021-05-25 | 算筹信息科技有限公司 | Method for solving inner product of sparse matrix and dense matrix by outer product accumulation |
| CN114117986A (en) * | 2022-01-29 | 2022-03-01 | 深圳市芯茂微电子有限公司 | Arithmetic unit |
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2018
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108763163A (en) * | 2018-08-02 | 2018-11-06 | 北京知存科技有限公司 | Simulate vector-matrix multiplication operation circuit |
| WO2020024608A1 (en) * | 2018-08-02 | 2020-02-06 | 北京知存科技有限公司 | Analog vector-matrix multiplication circuit |
| US11379673B2 (en) | 2018-08-02 | 2022-07-05 | Beijing Zhicun Witin Technology Corporation Limited | Analog vector-matrix multiplication circuit |
| CN110276048A (en) * | 2019-05-25 | 2019-09-24 | 南京惟心光电系统有限公司 | A kind of control method of matrix-vector multiplication array |
| CN110276048B (en) * | 2019-05-25 | 2023-06-09 | 南京惟心光电系统有限公司 | Control method for matrix vector multiplication array |
| CN112835552A (en) * | 2021-01-26 | 2021-05-25 | 算筹信息科技有限公司 | Method for solving inner product of sparse matrix and dense matrix by outer product accumulation |
| CN114117986A (en) * | 2022-01-29 | 2022-03-01 | 深圳市芯茂微电子有限公司 | Arithmetic unit |
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