CN114117986A - Arithmetic unit - Google Patents
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- CN114117986A CN114117986A CN202210109806.9A CN202210109806A CN114117986A CN 114117986 A CN114117986 A CN 114117986A CN 202210109806 A CN202210109806 A CN 202210109806A CN 114117986 A CN114117986 A CN 114117986A
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Abstract
The invention discloses an arithmetic unit which comprises an analog-to-digital conversion module, an adjustable resistance module, a control module and a voltage conversion current module, wherein a resistance value corresponding to a first voltage is obtained through the analog-to-digital conversion module, the control module and the adjustable resistance module, a current value corresponding to a second voltage is obtained through the voltage conversion current module, and a product or quotient of the first voltage and the second voltage can be obtained through a voltage value at the output end of the arithmetic unit based on ohm's law. In summary, the invention does not need to directly perform multiplication and division operations on the first voltage and the second voltage, and indirectly obtains the product or quotient of the first voltage and the second voltage by using ohm's law, so that the arithmetic unit has low requirements on device precision and is not easily affected by packaging stress or device mismatch.
Description
Technical Field
The invention relates to the field of analog circuit design, in particular to an arithmetic unit.
Background
With the development of scientific and technological intelligence, the requirements of application systems on the signal processing capability of analog chips are higher and higher, and many analog chips need to realize the function of multiplication or division operation when processing input signals. The conventional method for realizing multiplication or division in the analog circuit technology, such as a log-anti-log multiplier, directly utilizes the operating dc characteristic of a semiconductor device to realize multiplication or division. This implementation itself requires the use of high precision analog devices to ensure its operating accuracy. Meanwhile, the high-precision analog device has higher requirement on the process stability and is easily influenced by the packaging stress after packaging. The packaging stress can cause the mismatch of devices in the analog circuit for realizing multiplication or division, so that the output precision of the functional analog circuit is influenced.
Disclosure of Invention
The invention aims to provide an arithmetic unit, which reduces the requirement on the precision of devices in the arithmetic unit on the basis of realizing multiplication or division operation, and the operation result is not easily influenced by the packaging stress or device mismatch of the arithmetic unit.
In order to solve the technical problem, the invention provides an arithmetic unit, which comprises an analog-to-digital conversion module, an adjustable resistance module, a control module and a voltage conversion current module;
the analog-to-digital conversion module is used for converting the first voltage from analog quantity to digital quantity;
the control module is used for controlling the adjustable resistance module to adjust the resistance value of the adjustable resistance module based on the digital quantity;
the voltage conversion current module is used for converting the second voltage into current;
the input end of the analog-to-digital conversion module is used for inputting the first voltage, the output end of the analog-to-digital conversion module is connected with the input end of the control module, the output end of the control module is connected with the control end of the adjustable resistance module, the first end of the adjustable resistance module is grounded, and the common end, which is connected with the output end of the voltage conversion current module and is connected with the second end of the adjustable resistance module, is the output end of the arithmetic unit.
Preferably, the analog-to-digital conversion module comprises a constant current source, a first comparator, a coding input module and a coding output module, the coding input module comprises N first resistors and N first controllable switches, and N is a positive integer;
the N first resistors are connected in series, one end of the series circuit is respectively connected with the output end of the constant current source and the positive input end of the first comparator, the other end of the series circuit is grounded, and the N first controllable switches are respectively connected in parallel at two ends of the N first resistors in a one-to-one correspondence manner;
the negative input end of the first comparator is the input end of the analog-to-digital conversion module, the output end of the first comparator is connected with the input end of the coding output module, and the output end of the coding output module is the output end of the analog-to-digital conversion module;
the encoding output module is used for generating a digital quantity with N bits based on the output of the first comparator, and the values of the N bits of the digital quantity correspond to the switch states of the N first controllable switches one by one so that the voltage of the positive input end of the first comparator is equal to the first voltage.
Preferably, the adjustable resistor module includes N second controllable switches and N second resistors, the resistance of the ith second resistor is k times the resistance of the ith first resistor, k is a positive number,
and i is an integer;
the N second resistors are connected in series, the first end of the series circuit is the first end of the adjustable resistor module, the second end of the series circuit is the second end of the adjustable resistor module, the N second controllable switches are connected in parallel to the two ends of the N second resistors in a one-to-one correspondence manner, and the control ends of the N second controllable switches are the control ends of the adjustable resistor module;
the control module is specifically configured to control on or off of the N second controllable switches in a one-to-one correspondence manner based on the values of the N bits of the digital quantity so that the adjustable resistance module adjusts the resistance value of the adjustable resistance module.
Preferably, the voltage conversion current module includes a second comparator, a third resistor, a first PMOS and a second PMOS;
a positive input end of the second comparator is an input end of the voltage conversion current module, a negative input end of the second comparator is connected with an output end of the second comparator, a connected common end of the negative input end of the second comparator and the output end of the second comparator is respectively connected with a first end of the third resistor and a drain electrode of the first PMOS, and a second end of the third resistor is grounded;
the grid electrode of the first PMOS is respectively connected with the grid electrode of the second PMOS and the drain electrode of the first PMOS, the source electrode of the first PMOS and the source electrode of the second PMOS are both connected with the power supply, and the common end, which is connected with the first end of the circuit formed by connecting the drain electrodes of the second PMOS and the N second resistors in series and is connected with, is the output end of the arithmetic unit.
Preferably, the size of the first PMOS is the same as the size of the second PMOS.
Preferably, the voltage conversion current module includes a third comparator, a fourth resistor, a third PMOS and a fourth PMOS;
the positive input end of the third comparator is the input end of the voltage conversion current module, the negative input end of the third comparator is connected with the output end of the third comparator, the public end of the connection is connected with the first end of the circuit formed by connecting the N second resistors in series, and the drain electrode of the third PMOS is connected with the output end of the third comparator;
the grid electrode of the third PMOS is respectively connected with the drain electrode of the third PMOS and the grid electrode of the fourth PMOS, the source electrode of the third PMOS and the source electrode of the fourth PMOS are both connected with the power supply, the common end of the drain electrode of the fourth PMOS, which is connected with the first end of the fourth resistor, is the output end of the arithmetic unit, and the second end of the fourth resistor is grounded.
Preferably, the size of the third PMOS is the same as the size of the fourth PMOS.
Preferably, the resistance value of the (i + 1) th first resistor in the N first resistors is 1/2 of the resistance value of the (i) th first resistor,
and i is an integer.
Preferably, k is 1, that is, the resistance value of the ith second resistor is equal to the resistance value of the ith first resistor.
Preferably, the encoding output module is a SAR.
The invention provides an arithmetic unit which comprises an analog-to-digital conversion module, an adjustable resistance module, a control module and a voltage conversion current module, wherein a resistance value corresponding to a first voltage is obtained through the analog-to-digital conversion module, the control module and the adjustable resistance module, a current value corresponding to a second voltage is obtained through the voltage conversion current module, and a product or quotient of the first voltage and the second voltage can be obtained through a voltage value at the output end of the arithmetic unit based on ohm's law. In summary, the invention does not need to directly perform multiplication and division operations on the first voltage and the second voltage, and indirectly obtains the product or quotient of the first voltage and the second voltage by using ohm's law, so that the arithmetic unit has low requirements on device precision and is not easily affected by packaging stress or device mismatch.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an arithmetic unit according to the present invention;
FIG. 2 is a circuit diagram of another arithmetic unit according to the present invention;
FIG. 3 is a circuit diagram of another arithmetic unit according to the present invention;
fig. 4 is a schematic input/output diagram of an SAR provided by the present invention.
Detailed Description
The core of the invention is to provide an arithmetic unit, which reduces the requirement on the precision of devices in the arithmetic unit on the basis of realizing multiplication or division operation, and the operation result is not easily influenced by the packaging stress of the arithmetic unit or the mismatch of the devices.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an arithmetic unit according to the present invention, which includes an analog-to-digital conversion module 01, an adjustable resistance module 03, a control module 02, and a voltage-to-current conversion module 04;
the analog-to-digital conversion module 01 is used for converting the first voltage from analog quantity to digital quantity;
the control module 02 is used for controlling the adjustable resistance module 03 to adjust the resistance value of the adjustable resistance module 03 based on the digital quantity;
the voltage conversion current module 04 is configured to convert the second voltage into a current;
the input end of the analog-to-digital conversion module 01 is used for inputting a first voltage, the output end of the analog-to-digital conversion module 01 is connected with the input end of the control module 02, the output end of the control module 02 is connected with the control end of the adjustable resistance module 03, the first end of the adjustable resistance module 03 is grounded, the second end of the adjustable resistance module 03 is connected with the output end of the voltage conversion current module 04, and the connected common end is the output end of the arithmetic unit.
In the arithmetic unit in the prior art, the two values are directly multiplied or divided by using the working characteristics of the analog device, so that the requirement on the precision of the analog device is higher, and the analog device is easily influenced by packaging stress and a production process, so that the operation result is not accurate enough.
In order to solve the above technical problem, the present application provides an arithmetic unit, which universally converts one of the values from an analog value to a digital value without depending on the operating characteristics of an analog device, and performs multiplication and division operations on the one value and the other value by using the ohmic characteristics after the digital processing.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an arithmetic unit according to the present invention, where Vin1 is a first voltage, Vin2 is a second voltage, and Vout is a voltage of an output terminal of the arithmetic unit. Specifically, first, the analog-to-digital conversion module 01 converts the first voltage from an analog value to a digital value, and the control module 02 controls the adjustable resistance module 03 to adjust its resistance value based on the digital value. Based on ohm's law, the quantitative relationship between the adjusted resistance value of the adjustable resistance module 03 and the first voltage can be determined, for example, the constant current source 11 can be connected to one end of the adjustable resistance module 03, and then the control module 02 can control the resistance value of the adjustable resistance module 03 to be equal to the quotient obtained by dividing the first voltage by the output current of the constant current source 11. The voltage-to-current module 04 converts the second voltage into the current, and the quantitative relationship between the second voltage and the current converted by the voltage-to-current module 04 may also be determined based on ohm's law, for example, a resistor may be disposed in the voltage-to-current module 04, the voltage on the resistor is the second voltage, and the current on the resistor is the quotient of the second voltage divided by the resistance of the resistor.
The quantity relation between the resistance value of the adjustable resistance module 03 and the first voltage is determined, the quantity relation between the output current of the voltage conversion current module 04 and the second voltage is also determined, and the product or quotient of the first voltage and the second voltage can be obtained through the voltage value of the output end of the arithmetic unit based on ohm's law. When the specific circuit structure of the operator is different, how to obtain the product or quotient of the first voltage and the second voltage according to the voltage value of the output end of the operator is also different, and the present application is not particularly limited thereto.
In summary, the invention does not need to directly perform multiplication and division operations on the first voltage and the second voltage, and indirectly obtains the product or quotient of the first voltage and the second voltage by using ohm's law, so that the arithmetic unit has low requirements on device precision and is not easily affected by packaging stress or device mismatch.
On the basis of the above-described embodiment:
as a preferred embodiment, the analog-to-digital conversion module 01 includes a constant current source 11, a first comparator 12, a code input module 13 and a code output module 14, where the code input module 13 includes N first resistors and N first controllable switches, where N is a positive integer;
the N first resistors are connected in series, one end of the series circuit is respectively connected with the output end of the constant current source 11 and the positive input end of the first comparator 12, the other end of the series circuit is grounded, and the N first controllable switches are respectively connected in parallel at two ends of the N first resistors in a one-to-one correspondence manner;
the negative input end of the first comparator 12 is the input end of the analog-to-digital conversion module 01, the output end of the first comparator 12 is connected with the input end of the coding output module 14, and the output end of the coding output module 14 is the output end of the analog-to-digital conversion module 01;
the encoding output module 14 is configured to generate a digital quantity with a bit number N based on the output of the first comparator 12, where values of N bits of the digital quantity correspond to switching states of the N first controllable switches one to one, so that a voltage at the positive input terminal of the first comparator 12 is equal to the first voltage.
Referring to fig. 2, fig. 2 is a circuit diagram of another arithmetic unit according to the present invention.
In this embodiment, the analog-to-digital conversion module 01 includes a constant current source 11, a first comparator 12, a code input module 13 and a code output module 14, where the code input module 13 includes N first resistors and N first controllable switches, so as to achieve the purpose of converting the first voltage from an analog quantity to a digital quantity.
Specifically, the value of each bit of the digital quantity generated by the code output module 14 corresponds to the on-off states of the N first controllable switches one to one, and the purpose is to change the resistance value of the resistor string formed by the N first resistors and the N first controllable switches by controlling the on-off states of the first controllable switches, so that the voltage at the positive input end of the first comparator 12 is equal to the first voltage. Assuming that the resistance of the resistor string is finally R1, the first voltage is Vin1, and the output current of the constant current source 11 is Iref, R1= Vin 1/Iref.
There are various implementations of the encoding output module 14 for generating digital quantity meeting the requirement, and this application is not limited to this. For example, the first controllable switch connected in parallel to two ends of the first resistor is first controlled to be closed, at this time, the voltage at the positive input end of the first comparator 12 is the product of the resistance value of the first resistor and the current output by the constant current source 11, the product is compared with the voltage at the negative input end of the first comparator 12, that is, the first voltage, and if the product is smaller than the first voltage, the first bit of the digital quantity generated by the encoding output module 14 is 1. And closing the second first controllable switch to the nth first controllable switch in sequence according to the above process to obtain the values of other bits of the digital quantity generated by the code output module 14. The digital quantity generated by the final encoding output module 14 is such that the voltage across the resistor string is at its maximum close to the first voltage.
In addition, the magnitude relationship between the resistance values of the N first resistors is not particularly limited in this application, for example, the resistance values of the N first resistors may sequentially decrease, when the encoding output module 14 converts the first voltage into the digital quantity, the first controllable switch corresponding to the first resistor with the largest resistance value is closed first, if the voltage at the positive input end of the first comparator 12 is smaller than the voltage at the negative input end of the first comparator 12, that is, the first voltage, the first bit of the digital quantity output by the encoding output module 14 is 1, and then the first controllable switches corresponding to the remaining first resistors are sequentially closed to obtain the values of the other bits of the digital quantity generated by the encoding output module 14.
In a preferred embodiment, the adjustable resistor module 03 includes N second controllable switches and N second resistors, where the resistance of the ith second resistor is k times the resistance of the ith first resistor, k is a positive number,
and i is an integer;
the N second resistors are connected in series, a first end of the circuit after the series connection is a first end of the adjustable resistor module 03, a second end of the circuit after the series connection is a second end of the adjustable resistor module 03, the N second controllable switches are respectively connected in parallel to two ends of the N second resistors in a one-to-one correspondence manner, and control ends of the N second controllable switches are control ends of the adjustable resistor module 03;
the control module 02 is specifically configured to control the on or off of the N second controllable switches in a one-to-one correspondence manner based on the values of the N bits of the digital quantity so that the adjustable resistance module 03 adjusts the resistance value of itself.
Referring to fig. 2, fig. 2 is a circuit diagram of another arithmetic unit according to the present invention.
In this embodiment, the adjustable resistor module 03 includes N second controllable switches and N second resistors, and when the switch states of the second controllable switches are changed, the resistance value of the adjustable resistor module 03 is also changed. Specifically, the analog-to-digital conversion module 01 makes the voltage at the positive input end of the first comparator 12 equal to the first voltage to obtain a digital quantity corresponding to the first voltage, and the control module 02 controls the on-off state of the second controllable switch in a one-to-one correspondence manner based on the digital quantity to change the resistance value of the adjustable resistance module 03.
Since the resistance value of the ith second resistor is k times the resistance value of the ith first resistor, the resistance value adjusted by the adjustable resistor module 03 is k times the final resistance value of the code input module 13 in the analog-to-digital conversion module 01, and the resistance value adjusted by the adjustable resistor module 03 is R2, R2= k R1= (k Vin 1)/Iref. Based on ohm's law, the product or quotient of the first voltage and the second voltage can be obtained from the voltage value at the output terminal of the operator.
As a preferred embodiment, the voltage-to-current conversion module 04 includes a second comparator, a third resistor, a first PMOS and a second PMOS;
the positive input end of the second comparator is the input end of the voltage conversion current module 04, the negative input end of the second comparator is connected with the output end of the second comparator, and the connected common end is respectively connected with the first end of the third resistor and the drain electrode of the first PMOS, and the second end of the third resistor is grounded;
the grid electrode of the first PMOS is respectively connected with the grid electrode of the second PMOS and the drain electrode of the first PMOS, the source electrode of the first PMOS and the source electrode of the second PMOS are both connected with the power supply, and the common end, connected with the first end of the circuit formed by connecting the drain electrode of the second PMOS in series with the N second resistors, of the second PMOS is the output end of the arithmetic unit.
Referring to fig. 2, fig. 2 is a circuit diagram of another arithmetic unit according to the present invention.
In this embodiment, a specific circuit structure of the voltage-to-current conversion module 04 is provided, and the circuit in this embodiment, the analog-to-digital conversion module 01, the control module 02, and the adjustable resistance module 03 can implement the operation of the product of the first voltage and the second voltage.
Specifically, the second voltage is input through the positive input end of the second comparator, and the negative input end of the second comparator is connected with the output end of the second comparator, so that the voltage of the output end of the second comparator is equal to the second voltage, and therefore the current of the loop in which the drain electrode of the first PMOS is located is a quotient obtained by dividing the second voltage by the resistance value of the third resistor. The first PMOS and the second PMOS form a cascode current mirror, and it is assumed that the mirror ratio between the second PMOS and the first PMOS is a: 1, the current of the loop in which the drain of the second PMOS is located is equal to a times of the current of the loop in which the drain of the first PMOS is located.
If the current output by the drain of the first PMOS is I, the second voltage is Vin2, and the resistance value of the third resistor is Rin3, I = Vin2/Rin3, and the current output by the drain of the second PMOS is a = (a × Vin 2)/Rin 3, then the voltage Vout of the output terminal of the arithmetic unit = (k × Vin1/Iref) (a × Vin2/Rin3) = (k × a × Vin1 × Vin 2)/(Iref 3), where Vout, k, a, Iref, and Rin3 are known quantities, the product of Vin1 and Vin2 can be obtained, and without directly performing a multiplication and division operation on two values, the product of the second voltage and the first voltage can be indirectly obtained by using an ohm law, so that the arithmetic unit is not sensitive to the precision of the device and is not easily affected by the package stress or the mismatch of the device.
In a preferred embodiment, the first PMOS has the same size as the second PMOS.
In this embodiment, the size of the first PMOS is the same as the size of the second PMOS, and then the mirror ratio between the second PMOS and the first PMOS is 1: 1, the current of the loop where the drain of the second PMOS is located is equal to the current of the loop where the drain of the first PMOS is located, so Vout = (k × Vin1/Iref) × (Vin 2/Rin3) = (k × Vin1 × Vin 2)/(Iref × Rin3), which makes the operation simpler.
As a preferred embodiment, the voltage-to-current conversion module 04 includes a third comparator, a fourth resistor, a third PMOS and a fourth PMOS;
the positive input end of the third comparator is the input end of the voltage conversion current module 04, the negative input end of the third comparator is connected with the output end of the third comparator, the public end of the connection is connected with the first end of the circuit formed by connecting the N second resistors in series, and the drain electrode of the third PMOS is connected with the output end of the third comparator;
the grid electrode of the third PMOS is respectively connected with the drain electrode of the third PMOS and the grid electrode of the fourth PMOS, the source electrode of the third PMOS and the source electrode of the fourth PMOS are both connected with the power supply, the drain electrode of the fourth PMOS is connected with the first end of the fourth resistor, the public end of the connection is the output end of the arithmetic unit, and the second end of the fourth resistor is grounded.
Referring to fig. 2, fig. 2 is a circuit diagram of another arithmetic unit according to the present invention.
In this embodiment, another specific circuit structure of the voltage-to-current conversion module 04 is provided, and the circuit in this embodiment, the analog-to-digital conversion module 01, the control module 02, and the adjustable resistance module 03 can implement the operation on the quotient of the first voltage and the second voltage.
Specifically, the second voltage is input through the positive input end of the third comparator, and the negative input end of the third comparator is connected to the output end of the third comparator, so that the voltage at the output end of the third comparator is equal to the second voltage, and therefore the current of the loop in which the drain of the third PMOS is located is a quotient obtained by dividing the second voltage by the resistance value of the adjustable resistance module 03. The third PMOS and the fourth PMOS form a cascode current mirror, and it is assumed that the mirror ratio between the fourth PMOS and the third PMOS is B: 1, the current of the loop in which the drain of the fourth PMOS is located is equal to B times the current of the loop in which the drain of the third PMOS is located.
If the current output by the drain of the third PMOS is I, the second voltage is Vin2, the resistance of the fourth resistor is Rin4, I = Vin2/R2= Vin 2/(k × Vin1/Iref) = (Vin 2 × Iref)/(k × Vin 1), and the current output by the drain of the fourth PMOS is B × I = (B × Vin2 | _ Iref)/(k × Vin 1), the voltage output by the operator is Vout = (B × Vin2 × Iref Rin 4)/(k × Vin 1), where Vout, k, B, Iref, and Rin4 are known quantities, the quotient of Vin2 divided by Vin1 can be calculated without directly performing a multiplication and division operation on two ohm values, and the quotient of the second voltage and the first voltage is obtained indirectly, so that the accuracy of the operator on the packaged device is not easily affected by stress or stress mismatch.
As a preferred embodiment, the size of the third PMOS is the same as the size of the fourth PMOS.
In this embodiment, the size of the third PMOS is the same as the size of the fourth PMOS, and then the mirror comparison between the fourth PMOS and the third PMOS is 1: 1, the current of the loop where the drain of the third PMOS is located is equal to the current of the loop where the drain of the fourth PMOS is located, Vout = (Vin 2 × Iref Rin 4)/(k × Vin 1), so that the operation is simpler and more convenient.
In a preferred embodiment, the value of the (i + 1) th first resistor in the N first resistors is 1/2 times the value of the (i) th first resistor,
and i is an integer.
In this embodiment, the resistance of the i +1 th first resistor of the N first resistors is 1/2 of the resistance of the i first resistor, so that the voltage at the positive input end of the first comparator 12 in the encoding output module 14 can be close to the first voltage to the greatest extent, and the operation result of the operator is more accurate.
For example, the code output module 14 first closes the first controllable switch corresponding to the first resistor with the largest resistance value, if the voltage at the positive input end of the first comparator 12 is smaller than the voltage at the negative input end of the first comparator 12, that is, the first voltage, the first bit of the digital quantity output by the code output module 14 is 1, the resistance value of the first resistor with the largest resistance value is R, then the first controllable switches corresponding to the resistance values of R/2 are sequentially closed to obtain the value of the second bit of the digital quantity generated by the code output module 14, the above process is repeated to be low N times, and at this time, the voltage value superposed on the positive input end of the first comparator 12 is the voltage value superposed on the positive input end of the first comparator 12
If N is large enough, the voltage superposed on the positive input terminal of the first comparator 12 is very small, which represents that the voltage of the positive input terminal of the first comparator 12 is very close to the voltage of the second input terminalA voltage.
In a preferred embodiment, k is 1, i.e. the resistance of the ith second resistor is equal to the resistance of the ith first resistor.
In this embodiment, k is 1, i.e. the resistance of the ith second resistor is equal to the resistance of the ith first resistor, so that the arithmetic operation of the arithmetic unit is simpler and more convenient. For example, Vout = (Vin1/Iref) (a × Vin2/Rin3) = (a × Vin1 × Vin 2)/(Iref × Rin3) when multiplication of the first voltage and the second voltage is performed; when the division operation of the first voltage and the second voltage is realized, Vout = (B × Vin2 × Iref Rin 4)/Vin 1.
In a preferred embodiment, the code output module 14 is a SAR.
In the present embodiment, an SAR is selected as the encoding output module 14, and the SAR is a successive approximation register type, which has the characteristics of low power consumption, small size, wide application range, and the like, and is substantially a binary search algorithm. Referring to fig. 4, fig. 4 is a schematic diagram of input and output of an SAR according to the present invention, which is different in SAR implementation modes, but the basic structure of the SAR is very simple, the SAR controls the internal circuit timing to be inverted by a periodic oscillation signal OSC so as to output different signals, controls the resistance values of variable resistor strings composed of N first controllable switches and N first resistors so as to generate different voltages, compares the voltages with the first voltage by the first comparator 12 to generate corresponding Judge signals, and inputs the Judge signals to the control terminal of the SAR so as to control the generation of the signals, so that the voltage value of the variable resistor strings is close to the first voltage to the maximum extent.
There are many ways for SAR to generate digital quantity, which are commonly used but not limited to the comparison sequence that is sequentially overlapped from high to low, that is, comparing a large voltage value with a first voltage to determine the value of the bit (for example, if the voltage value is lower than the first voltage, the bit takes 1, otherwise, the bit takes 0). On the basis, a relatively small voltage is superimposed to compare with the first voltage, for example, if the voltage is still lower than the first voltage, the bit takes 1, and this is repeated to the nth bit, for example, the voltage value superimposed each time is 1/2 of the voltage value superimposed last time, if N is large enough, the voltage value superimposed by the nth bit is small, which represents that the voltage value on the variable resistor string composed of the N first controllable switches and the N first resistors at this time, that is, the voltage value at the positive input terminal of the first comparator 12 is very close to the first voltage.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An arithmetic unit is characterized by comprising an analog-to-digital conversion module, an adjustable resistance module, a control module and a voltage conversion current module;
the analog-to-digital conversion module is used for converting the first voltage from analog quantity to digital quantity;
the control module is used for controlling the adjustable resistance module to adjust the resistance value of the adjustable resistance module based on the digital quantity;
the voltage conversion current module is used for converting the second voltage into current;
the input end of the analog-to-digital conversion module is used for inputting the first voltage, the output end of the analog-to-digital conversion module is connected with the input end of the control module, the output end of the control module is connected with the control end of the adjustable resistance module, the first end of the adjustable resistance module is grounded, and the common end, which is connected with the output end of the voltage conversion current module and is connected with the second end of the adjustable resistance module, is the output end of the arithmetic unit.
2. The arithmetic unit of claim 1, wherein the analog-to-digital conversion module comprises a constant current source, a first comparator, a code input module and a code output module, the code input module comprises N first resistors and N first controllable switches, N is a positive integer;
the N first resistors are connected in series, one end of the series circuit is respectively connected with the output end of the constant current source and the positive input end of the first comparator, the other end of the series circuit is grounded, and the N first controllable switches are respectively connected in parallel at two ends of the N first resistors in a one-to-one correspondence manner;
the negative input end of the first comparator is the input end of the analog-to-digital conversion module, the output end of the first comparator is connected with the input end of the coding output module, and the output end of the coding output module is the output end of the analog-to-digital conversion module;
the encoding output module is used for generating a digital quantity with N bits based on the output of the first comparator, and the values of the N bits of the digital quantity correspond to the switch states of the N first controllable switches one by one so that the voltage of the positive input end of the first comparator is equal to the first voltage.
3. The arithmetic unit of claim 2, wherein the adjustable resistance module comprises N second controllable switches and N second resistors, wherein the ith second resistor has a resistance k times the resistance of the ith first resistor, and wherein k is a positive number,
and i is an integer;
the N second resistors are connected in series, the first end of the series circuit is the first end of the adjustable resistor module, the second end of the series circuit is the second end of the adjustable resistor module, the N second controllable switches are connected in parallel to the two ends of the N second resistors in a one-to-one correspondence manner, and the control ends of the N second controllable switches are the control ends of the adjustable resistor module;
the control module is specifically configured to control on or off of the N second controllable switches in a one-to-one correspondence manner based on the values of the N bits of the digital quantity so that the adjustable resistance module adjusts the resistance value of the adjustable resistance module.
4. The arithmetic unit of claim 3, wherein the voltage-to-current module comprises a second comparator, a third resistor, a first PMOS and a second PMOS;
a positive input end of the second comparator is an input end of the voltage conversion current module, a negative input end of the second comparator is connected with an output end of the second comparator, a connected common end of the negative input end of the second comparator and the output end of the second comparator is respectively connected with a first end of the third resistor and a drain electrode of the first PMOS, and a second end of the third resistor is grounded;
the grid electrode of the first PMOS is respectively connected with the grid electrode of the second PMOS and the drain electrode of the first PMOS, the source electrode of the first PMOS and the source electrode of the second PMOS are both connected with the power supply, and the common end, which is connected with the first end of the circuit formed by connecting the drain electrodes of the second PMOS and the N second resistors in series and is connected with, is the output end of the arithmetic unit.
5. The operator of claim 4, wherein a size of the first PMOS is the same as a size of the second PMOS.
6. The arithmetic unit of claim 3, wherein the voltage-to-current module comprises a third comparator, a fourth resistor, a third PMOS and a fourth PMOS;
the positive input end of the third comparator is the input end of the voltage conversion current module, the negative input end of the third comparator is connected with the output end of the third comparator, the public end of the connection is connected with the first end of the circuit formed by connecting the N second resistors in series, and the drain electrode of the third PMOS is connected with the output end of the third comparator;
the grid electrode of the third PMOS is respectively connected with the drain electrode of the third PMOS and the grid electrode of the fourth PMOS, the source electrode of the third PMOS and the source electrode of the fourth PMOS are both connected with the power supply, the common end of the drain electrode of the fourth PMOS, which is connected with the first end of the fourth resistor, is the output end of the arithmetic unit, and the second end of the fourth resistor is grounded.
7. The operator of claim 6, wherein a size of the third PMOS is the same as a size of the fourth PMOS.
8. The arithmetic unit of claim 2, wherein the i +1 th one of the N first resistors has a resistance value of 1/2 times that of the i first resistor,
and i is an integer.
9. The arithmetic unit of claim 3, wherein k is 1, i.e., the resistance of the ith second resistor is equal to the resistance of the ith first resistor.
10. The arithmetic unit of any one of claims 2 to 9 wherein the coded output module is a SAR.
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