CN209514618U - Dynamic bias simulates vector-matrix multiplication operation circuit - Google Patents
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Abstract
The utility model provides a kind of dynamic bias simulation vector-matrix multiplication operation circuit, dynamic bias simulation vector-matrix multiplication operation circuit includes: that positive value weight arranges, constant column and subtracter, the quantity of subtracter is equal to the quantity of positive value weight column and the two connects one to one, and the quantity of constant column is less than the quantity of positive value weight column；The minuend input terminal of subtracter is correspondingly connected with the output end of positive value weight column, and subtracting input connects the output end of constant column, and output end exports operation result；Wherein, the subtracting input of multiple subtracters connects same constant column.Before programmable semiconductor device is written in weight, each element in weight array is added into a constant positive value and obtains weight array to be configured, positive value weight is written in weight array to be configured to arrange, constant positive value is written in constant column, with this, it does not need setting negative value weight to arrange, circuit structure can be simplified.
Description
Technical field
The utility model relates to semiconductor integrated circuit fields more particularly to a kind of dynamic bias to simulate vector-Matrix Multiplication
Method computing circuit.
Background technique
Matrix multiplication operation is widely used in the field of data mining such as image procossing, recommender system, Data Dimensionality Reduction, however,
Traditional Technical Architecture and wanting for current mass data processing is more and more only not suitable with based on serial manner by single computer
It asks.Therefore, expand the operation scale of matrix multiplication and reduce its operation time, be beneficial to meet matrix decomposition algorithm processing greatly
The requirement of scale data.
But weight is stored in flash memory transistor battle array by existing simulation vector-matrix multiplication operation circuit (as shown in Figure 1)
In broomrape, when practical application, simulation vector-matrix multiplication operation weight has positive value also to have negative value, but flash memory transistor is only
Positive value weight can be stored, so, for negative value weight, need to realize by subtraction circuit, flash array needs to be arranged at this time
Multiple positive value weight column and multiple negative value weights column, in general, needing to be spaced setting on the occasion of weight column and negative value weight column, such as odd
Ordered series of numbers stores positive value weight, and even column stores negative value weight, or conversely, and a positive value weight arranges and a negative value weight
Column are connected to a subtraction circuit, and the weight column that positive value also stores negative value can be stored by forming one, and this method greatly causes
Area loss and cost overhead.
Utility model content
In view of this, the present invention provides a kind of dynamic bias to simulate vector-matrix multiplication operation circuit, Neng Goujian
Change circuit structure, effectively reduce component number, reduce circuit area, reduce cost overhead, is conducive to integrated.
To achieve the goals above, the utility model adopts the following technical solution:
A kind of dynamic bias simulation vector-matrix multiplication operation circuit is provided, comprising: programmable semiconductor device array with
And subtracter；
The programmable semiconductor device array includes: positive value weight column and constant column, and the quantity of the subtracter is being equal to this just
The quantity and the two of value weight column connect one to one, and the quantity of constant column is less than the quantity of positive value weight column；
Wherein, constant column can be a column or duplication multiple row；
The minuend input terminal of subtracter is correspondingly connected with the output end of positive value weight column, and subtracting input connects constant column
Output end, output end output simulation vector-matrix multiplication operation result；
Wherein, the subtracting input of multiple subtracters connects same constant column.
Further, dynamic bias simulates vector-matrix multiplication operation circuit further include: current stabilization module, the current stabilization module
It is connected to the output end of constant column.
Further, dynamic bias simulates vector-matrix multiplication operation circuit further include:
Programmed circuit connects source electrode, the grid of each programmable semiconductor device in programmable semiconductor device array
And/or substrate, for regulating and controlling the threshold voltage of programmable semiconductor device.
Further, which includes: voltage generation circuit and voltage control circuit, which is used for
Generate program voltage or erasing voltage, which is used to for the program voltage being loaded onto selected programmable partly lead
The source electrode of body device, alternatively, erasing voltage is loaded onto the grid or substrate of selected programmable semiconductor device, it can with regulation
The threshold voltage of programming semiconductor device.
Further, dynamic bias simulates vector-matrix multiplication operation circuit further include:
Controller connects the programmed circuit, by controlling programmed circuit work, controls devote oneself to work programmable and partly leads
The threshold voltage of the quantity of body device and each programmable semiconductor device.
Further, dynamic bias simulates vector-matrix multiplication operation circuit further include: ranks decoder, for gating
Programmable semiconductor device to be programmed.
Further, which uses floating transistor.
Dynamic bias provided by the utility model simulates vector-matrix multiplication operation circuit, programmable semiconductor device
Array includes: that positive value weight arranges, and constant column and subtracter, the quantity of subtracter are equal to the quantity of positive value weight column and the two one by one
It is correspondingly connected with, the quantity of constant column is less than the quantity of positive value weight column；The minuend input terminal of subtracter is correspondingly connected with positive value power
The output end of rearrangement, subtracting input connect the output end of constant column, and output end exports operation result；Wherein, multiple subtracters
Subtracting input connect same constant column.It, will be each in weight array before programmable semiconductor device is written in weight
A element adds a constant positive value and obtains weight array to be configured, and constant positive value is more than or equal in the weight array absolutely
It is worth the absolute value of maximum negative value weight, makes do not have negative value weight in weight array to be configured with this, by weight battle array to be configured
Column write-in positive value weight arranges, and constant positive value is written in constant column, the minuend input terminal of subtracter is correspondingly connected with positive value power
The output end of rearrangement, subtracting input connect the output end of constant column, and output end exports operation result, i.e., are being transported by subtracter
The influence for subtracting the constant positive value in result is calculated, with this, setting negative value weight is not needed and arranges, and multiple positive value weight column are shared normal
Ordered series of numbers can simplify circuit structure, effectively reduce component number, reduce circuit area, reduce cost overhead, be conducive to integrated
Change.
For the above and other objects, features and advantages of the utility model can be clearer and more comprehensible, preferable reality is cited below particularly
Example is applied, and cooperates institute's accompanying drawings, is described in detail below.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is existing simulation vector-matrix multiplication operation circuit circuit structure diagram；
Fig. 2 is that the utility model embodiment dynamic bias simulates vector-matrix multiplication operation circuit circuit structure diagram one；
Fig. 3 is that the utility model embodiment dynamic bias simulates vector-matrix multiplication operation circuit circuit structure diagram two；
Fig. 4 is that the utility model embodiment dynamic bias simulates vector-matrix multiplication operation circuit circuit structure diagram three；
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
The multiple positive value weight column of existing simulation vector-matrix multiplication operation circuit setting and multiple negative value weights column, respectively
For storing positive value weight and negative value weight, in general, needing to be spaced setting, such as odd column on the occasion of weight column and negative value weight column
Storage positive value weight, even column store negative value weight, or conversely, according to programmable semiconductor device characteristic: I=VW, I are indicated
Electric current is exported, V indicates that carrying voltage, W indicate the weight of programmable semiconductor device, and above formula is usually become I=by available circuit
(VW+)-(VW-), wherein W+ and W- respectively indicates positive value weight and negative value weight, with positive value weight column and negative value weight column difference
Storage positive value weight and negative value weight, greatly cause area loss and cost overhead.
To solve above-mentioned technical problem in the prior art, the utility model embodiment provide a kind of dynamic bias simulate to
Amount-matrix multiplication operation circuit, as shown in Fig. 2, dynamic bias simulation vector-matrix multiplication operation circuit includes: programmable
Array of semiconductor devices and subtracter 301~30n。
The programmable semiconductor device array includes: positive value weight column 101~10nWith constant column 20, the subtracter 301~
30nQuantity be equal to the positive value weight column 101~10nQuantity and the two connect one to one, the quantity of the constant column 20 is less than
The positive value weight column 301~30nQuantity (example is carried out with the scheme that the quantity of constant column 20 is 1 couple of the application in the present embodiment
Property explanation).
The minuend input terminal of subtracter is correspondingly connected with the output end of positive value weight column, and subtracting input connects constant column
20 output end, output end operation result；
Wherein, multiple subtracters 301~30nSubtracting input connect same constant column 20.
Wherein, it simulates vector-matrix multiplication operation circuit and realizes that simulation vector-matrix multiplication operation principle is as follows: needle
To a M row × N column programmable semiconductor device array, the source electrode of all programmable semiconductor devices of each column is all connected with
To same analog voltage input, N column programmable semiconductor device is correspondingly connected with N number of analog voltage input, the institute of every a line
There is the grid of programmable semiconductor device to be connected to same bias voltage input, M row programmable semiconductor device is corresponding to be connected
M bias voltage input is connect, the drain electrode of all programmable semiconductor devices of each column is connected to the same analog current
Output end, N column programmable semiconductor device are correspondingly connected with N number of analog current output end, wherein each programmable semiconductor device
Threshold voltage it is adjustable.N is the positive integer more than or equal to zero, and M is the positive integer more than or equal to zero, and M and N can be equal,
It can not also wait, so as to form the topological structure of source electrode coupling, drain electrode summation.
Wherein, by advance according to the threshold voltage V of each programmable semiconductor device of certain regular dynamic regulationTH, can incite somebody to action
Each programmable semiconductor device regards a variable equivalent simulation weight as and (is denoted as Wk,j, wherein 0 < k < M and 0 < j < N difference
Represent line number and row number), it is equivalent to one analogue data of storage, and programmable semiconductor device array then stores a simulation number
According to array
When circuit works, by a line analog voltage signal V1~VNIt is respectively applied to N column programmable semiconductor device, wherein
The source electrode of K column all programmable semiconductor devices obtains an analog voltage signal Vk, one bias voltage V of grid inputb, leakage
Distinguish output current signal I in polek,1~Ik,N, wherein according to programmable semiconductor device characteristic, I=V × W each may be programmed half
The drain electrode output electric current of conductor device is equal to source voltage multiplied by the weight of the programmable semiconductor device, i.e. Ik,1=VkWk,1,
Ik,N=VkWk,N, because the drain electrode of all programmable semiconductor devices of each column is connected to the same analog current output
End, according to Kirchhoff's law, so in the electric current I of the analog current output endjFor the column all programmable semiconductor devices
The sum of drain current, asMultiple analog current output ends export multiple electric currents andRealize matrix multiplication operation function.
Certainly, which can also be using the topological structure or grid of grid coupling, source electrode summation
Pole coupling, drain electrode summation topological structure, the utility model embodiment to this with no restriction.
In the following, realizing subtraction to using the utility model embodiment dynamic bias simulation vector-matrix multiplication operation circuit
The principle of operation is illustrated:
Before programmable semiconductor device is written in weight array, each element in weight array is added one
Constant positive value C, obtains weight array to be configured, and constant positive value is more than or equal to the negative value power of maximum absolute value in the weight array
The absolute value of weight, makes do not have negative value weight in weight array to be configured with this；Then, positive value is written into weight array to be configured
Constant positive value is written in the constant column weight column, and the minuend input terminal of a subtracter is correspondingly connected with a positive value weight column
Output end, subtracting input connect the output end of constant column, and output end output simulation vector-matrix multiplication operation is as a result, i.e.
The influence of the constant positive value is subtracted in operation result by subtracter, with this, do not need setting negative value weight arrange, and it is multiple just
Be worth weight and arrange shared constant column, circuit structure can be simplified, effectively reduce component number, reduce circuit area, reduce at
This expense is conducive to integrated.
In the following, with weight for [5, -3,6, -8], for input voltage is V, illustrating the application's for for certain a line
(this example has selected weight behavior example the simplest, in practical applications, weight for concise description the application principle to principle
The scale of array is depending on operation demand, and for deep neural network operation, weight array is often on a grand scale, this is practical
Novel advantage is more obvious).
If for the row, then being needed brilliant in the first positive value weight using existing simulation vector-matrix multiplication operation circuit
Write-in 5 in body pipe (corresponding first positive value weight arranges), corresponding first negative value weight transistor (corresponding first negative value weight
Column) in write-in 0, after corresponding subtracter, export 5V；0 is written in the second positive value transistor, in the second negative value transistor
Write-in -3, after corresponding subtracter, output -3V；6 are written in third positive value transistor, is write in third negative value transistor
Enter 0, after corresponding subtracter, exports 6V；0 is written in the 4th positive value transistor, is written -8 in the 4th negative value transistor,
After corresponding subtracter, output -8V, and then final result [5V, -3V, 6V, -8V] is obtained, 8 transistors are needed altogether
It realizes.
And simulation vector-matrix multiplication operation circuit provided by the embodiment of the utility model is used, first by all weighted values
Plus 9 (being more than or equal to 8), weight column [14,6,15,1] to be configured are obtained, then are needed in the first positive value weight transistor
14 are written in (corresponding 1st positive value weight arranges), 6 are written in the second positive value transistor, is written the 14, the 4th in third positive value transistor
1 is written in positive value transistor, write-in 9 in constant transistor (corresponding constant column) after corresponding subtracter, exports final
As a result [5V, -3V, 6V, -8V] needs 5 transistors to realize, it follows that compared with prior art, the application effectively subtracts altogether
About 38% transistor is lacked.
It will be appreciated by persons skilled in the art that operation scale is bigger, the advantage of the application is more obvious.
In an alternative embodiment, referring to Fig. 3, which simulates vector-matrix multiplication operation circuit can be with
Multiple constant column are set, are not interspersed in multiple constant column equal parts or partially in entire programmable semiconductor device array, from
And when programmable semiconductor device array scale is larger, the columns for sharing the positive value weight column of constant column can be effectively reduced,
With this, the influence of parasitic parameter can be reduced, improves driving force, using and controlling for circuit also can be more flexible, improves operation
Accuracy and speed.
It will be appreciated by persons skilled in the art that constant column can uniformly be arranged when the constant is classified as multiple
Weight, at this point, weight array is considered as a whole；Each constant can also be arranged to corresponding positive value weight column
Together, as an arithmetic element, in carrying out practical application, weight array can be split by column, is then dispensed for different
In arithmetic element, the weighted value that each arithmetic element is arranged according to itself processor active task, setting constant carries out respective operation,
Operation can be realized more flexiblely with this, also, multioperation task parallel processing also may be implemented, and can effectively improve operation
Speed and efficiency.
In an alternative embodiment, referring to fig. 4, dynamic bias simulation vector-matrix multiplication operation circuit also wraps
Include: current stabilization module 40, the current stabilization module 40 are connected to the output end of the constant column 20.
Wherein, current stabilization module is arranged by the output end in constant column 20, the influence of parasitic parameter can be effectively reduced, into
One step improves driving force, improves the accuracy and speed of operation.
In an alternative embodiment, which simulates vector-matrix multiplication operation circuit further include: programming electricity
Road connects source electrode, grid and/or the substrate of each programmable semiconductor device in programmable semiconductor device array, is used for
Regulate and control the threshold voltage of programmable semiconductor device.
Wherein, which may include: voltage generation circuit and voltage control circuit, which is used for
Generate program voltage or erasing voltage, which is used to for the program voltage being loaded onto selected programmable partly lead
The source electrode of body device, alternatively, erasing voltage is loaded onto the grid or substrate of selected programmable semiconductor device, it can with regulation
The threshold voltage of programming semiconductor device.
Specifically, programmed circuit utilizes thermoelectron injection effect, according to programmable semiconductor device threshold voltage demand number
According to, to the source electrode of programmable semiconductor device apply high voltage, by channel electrons accelerate to high speed, to increase programmable semiconductor
The threshold voltage of device.
Also, programmed circuit utilizes tunneling effect, according to programmable semiconductor device threshold voltage demand data, Xiang Kebian
The grid or substrate of journey semiconductor devices apply high voltage, to reduce the threshold voltage of programmable semiconductor device.
In an alternative embodiment, dynamic bias simulation vector-matrix multiplication operation circuit can also include: control
Device processed connects the programmed circuit, by controlling programmed circuit work, controls the number for the programmable semiconductor device devoted oneself to work
The threshold voltage of amount and each programmable semiconductor device；Also, the controller can also be transported according to simulation vector-matrix multiplication
Calculation demand controls operation.
In an alternative embodiment, dynamic bias simulation vector-matrix multiplication operation circuit can also include: row
Column decoder, for gating programmable semiconductor device to be programmed.
In the above-described embodiments, which can use floating transistor.
In the above-described embodiments, dynamic bias simulation vector-matrix multiplication operation circuit can also include: bias voltage
Generation circuit is input to bias voltage input for generating preset bias voltage, it is to be understood that the simulation vector-
Matrix multiplication operation circuit can also be not provided with bias-voltage generating circuit, generate electricity by the voltage in multiplexing programmed circuit
Road controls the voltage generation circuit and generates preset bias voltage, is input to bias voltage input.
In an alternative embodiment, dynamic bias simulation vector-matrix multiplication operation circuit can also include: to turn
Changing device is connected to before multiple analog voltage inputs, for multiple analog current input signals to be respectively converted into simulation
Voltage input signal transports to corresponding analog voltage input.
Wherein, which may include: multiple operational amplifiers and corresponds company with multiple operational amplifiers
The multiple programmable semiconductor devices connect.The inverting input terminal of each operational amplifier is connected to corresponding programmable semiconductor device
The drain electrode of part, normal phase input end connect the first fixed-bias transistor circuit Vd, the output end of operational amplifier and programmable semiconductor device
Source electrode is connected, and is connected to corresponding analog voltage input, and the grid of programmable semiconductor device connects the first fixed-bias transistor circuit
Vd, the inverting input terminal of operational amplifier is for receiving analog current input signal Iin1~IinN。
In an alternative embodiment, dynamic bias simulation vector-matrix multiplication operation circuit can also include: electricity
Stream detection output circuit, is connected to after analog current output end, the analog current for exporting to analog current output end is defeated
Signal is handled and exported out.
Wherein, it is accurately handled and is exported by the current detecting output circuit electric current complete to operation, or be connected to
The input of next programmable semiconductor array can effectively realize that electric current precisely exports.
The current detecting output circuit may include: multiple operational amplifiers, the normal phase input end of each operational amplifier
The second fixed bias Vs is connected, inverting input terminal is connected to corresponding analog current output end, also, inverting input terminal and output
A resistor or transistor etc. are connected between end.Wherein, which is generally high voltage, and the operational amplifier is by mould
The voltage control of quasi- current output terminal is equal with the voltage of normal phase input end, for guaranteeing the grid source of programmable semiconductor device
Voltage is only controlled by the corresponding input voltage of the programmable semiconductor device, so that the output end voltage generation of operational amplifier
The amplitude of the output electric current of table respective column programmable semiconductor device.
The above is only illustrate each mould in simulation vector-matrix multiplication operation circuit provided by the embodiment of the utility model
The specific structure of block, in the specific implementation, the specific structure of above-mentioned each module are not limited on provided by the embodiment of the utility model
State structure, can also be skilled person will appreciate that other structures, be not limited thereto.
On the other hand, the utility model embodiment also provides a kind of chip, the chip include above-mentioned dynamic bias simulate to
Amount-matrix multiplication operation circuit.
In addition, the utility model embodiment also provides a kind of electronic equipment, which may include above-mentioned dynamic
Biasing simulation vector-matrix multiplication operation circuit, specifically, electronic equipment for example can be personal computer, calculating on knee
Machine, cellular phone, camera phone, smart phone, personal digital assistant, media player, navigation equipment, electronic mail equipment,
The combination of any equipment in game console, tablet computer, wearable device or these equipment.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including described want
There is also other identical elements in the process, method of element, commodity or equipment.
Specific embodiment is applied in the utility model to be expounded the principles of the present invention and embodiment, with
The explanation of upper embodiment is merely used to help understand the method and its core concept of the utility model；Meanwhile for this field
Those skilled in the art, based on the idea of the present invention, there will be changes in the specific implementation manner and application range, comprehensive
Upper described, the content of the present specification should not be construed as a limitation of the present invention.
Claims (7)
1. a kind of dynamic bias simulates vector-matrix multiplication operation circuit characterized by comprising programmable semiconductor device
Array and subtracter；
The programmable semiconductor device array includes: positive value weight column and constant column, and the quantity of the subtracter is equal to described
The quantity and the two of positive value weight column connect one to one, and the quantity of the constant column is less than the quantity of the positive value weight column；
The constant column can be a column or duplication multiple row；
The minuend input terminal of subtracter is correspondingly connected with the output end of positive value weight column, and subtracting input connects the output of constant column
End, output end export operation result；
Wherein, the subtracting input of multiple subtracters connects same constant column.
2. dynamic bias according to claim 1 simulates vector-matrix multiplication operation circuit, which is characterized in that further include:
Current stabilization module, the current stabilization module are connected to the output end of the constant column.
3. dynamic bias according to claim 1 simulates vector-matrix multiplication operation circuit, which is characterized in that further include:
Programmed circuit, connect the source electrode of each programmable semiconductor device in programmable semiconductor device array, grid and/or
Substrate, for regulating and controlling the threshold voltage of programmable semiconductor device.
4. dynamic bias according to claim 3 simulates vector-matrix multiplication operation circuit, which is characterized in that the volume
Journey circuit includes: voltage generation circuit and voltage control circuit, and the voltage generation circuit is for generating program voltage or wiping
Except voltage, the voltage control circuit is used to for the program voltage being loaded onto the source electrode of selected programmable semiconductor device,
Alternatively, erasing voltage to be loaded onto the grid or substrate of selected programmable semiconductor device, to regulate and control programmable semiconductor device
The threshold voltage of part.
5. dynamic bias according to claim 3 simulates vector-matrix multiplication operation circuit, which is characterized in that further include:
Controller connects the programmed circuit, is worked by controlling the programmed circuit, controls devote oneself to work programmable and partly leads
The threshold voltage of the quantity of body device and each programmable semiconductor device.
6. dynamic bias according to claim 1 simulates vector-matrix multiplication operation circuit, which is characterized in that further include:
Ranks decoder, for gating programmable semiconductor device to be programmed.
7. dynamic bias according to any one of claims 1 to 6 simulates vector-matrix multiplication operation circuit, feature exists
In the programmable semiconductor device uses floating transistor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112712173A (en) * | 2020-12-31 | 2021-04-27 | 北京清微智能科技有限公司 | Method and system for acquiring sparse operation data based on MAC (media Access control) multiply-add array |
| US20220137924A1 (en) * | 2019-02-26 | 2022-05-05 | Beljing Zhicun (Witin) Technology Corporation Limited | Dynamic bias analog vector-matrix multiplication operation circuit and operation control method therefor |
| CN112712173B (en) * | 2020-12-31 | 2024-06-07 | 北京清微智能科技有限公司 | Method and system for acquiring sparse operation data based on MAC multiply-add array |
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2019
- 2019-02-26 CN CN201920246764.7U patent/CN209514618U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220137924A1 (en) * | 2019-02-26 | 2022-05-05 | Beljing Zhicun (Witin) Technology Corporation Limited | Dynamic bias analog vector-matrix multiplication operation circuit and operation control method therefor |
| CN112712173A (en) * | 2020-12-31 | 2021-04-27 | 北京清微智能科技有限公司 | Method and system for acquiring sparse operation data based on MAC (media Access control) multiply-add array |
| CN112712173B (en) * | 2020-12-31 | 2024-06-07 | 北京清微智能科技有限公司 | Method and system for acquiring sparse operation data based on MAC multiply-add array |
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