CN208460769U - Planar gate IGBT device - Google Patents
Planar gate IGBT device Download PDFInfo
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- CN208460769U CN208460769U CN201821357767.XU CN201821357767U CN208460769U CN 208460769 U CN208460769 U CN 208460769U CN 201821357767 U CN201821357767 U CN 201821357767U CN 208460769 U CN208460769 U CN 208460769U
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- 238000009825 accumulation Methods 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000012535 impurity Substances 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 230000001413 cellular effect Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000005684 electric field Effects 0.000 description 13
- 238000003860 storage Methods 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The utility model relates to a kind of planar gate IGBT devices, it is on the section of the IGBT device, it further include the second conduction type floating layer for being set to the first conduction type drift region, the second conduction type floating layer is located at the underface of the first conduction type carrier accumulation layer and the second conduction type floating layer and the first conduction type carrier accumulation layer are adjacent；Lateral length of the second conduction type floating layer in the first conduction type drift region is not less than lateral length of the first conduction type carrier accumulation layer in the first conduction type drift region.The second conductivity regions are symmetrical arranged in the second conduction type base region two sides, and this second conductivity regions is connect with emitter.Its is compact-sized for the utility model, can effectively improve breakdown voltage, and turn-off power loss is effectively reduced, compatible with prior art, securely and reliably.
Description
Technical field
The utility model relates to a kind of IGBT device, especially a kind of planar gate IGBT device belongs to semiconductor IGBT device
The technical field of part.
Background technique
Since planar gate IGBT device has superior reliability compared to trench gate IGBT device, planar gate
IGBT has obtained large-scale application in the field required with higher reliability.In N-type planar gate IGBT device, planar gate
Carrier storage-type insulated gate bipolar transistor makes IGBT device close to grid due to using N-type charge storage layer structure
It is greatly improved with the carrier concentration profile of emitter position, to improve the conductance modulation of N-type drift region, makes
IGBT obtains low forward conduction voltage drop.
For planar gate carrier storage-type insulated gate bipolar transistor, the doping concentration of N-type charge storage layer is higher,
Forward conduction voltage drop is smaller；Simultaneously charge storage layer presence, improve the Carrier Profile of N-type drift region, it is certain just
To under conduction voltage drop, the small turn-off time can get.Therefore, planar gate charge storage type insulated gate bipolar transistor have compared with
Good forward conduction voltage drop and the compromise of turn-off time.But for planar gate charge storage type IGBT, since higher-doped is dense
The presence of the N-type charge storage layer of degree significantly reduces the breakdown voltage of device, and the doping concentration of N-type charge storage layer is higher,
The breakdown voltage of device is smaller.Influence of the N-type charge storage layer doping concentration to device electric breakdown strength limits planar gate charge
Storage-type insulated gate bipolar transistor structure breakdown voltage, forward conduction voltage drop and the optimization of turn-off time compromise.
Summary of the invention
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of planar gate IGBT device,
It is compact-sized, breakdown voltage can be effectively improved, and turn-off power loss is effectively reduced, it is compatible with prior art, securely and reliably.
According to technical solution provided by the utility model, the planar gate IGBT device, including semiconductor substrate and set
The structure cell being placed on the semiconductor substrate, semiconductor substrate include the first conduction type drift region；
On the section of the IGBT device, the structure cell uses plane cellular, and structure cell includes being set to the
The second conduction type base region in one conduction type drift region, the first conductive-type being set in second conduction type base region
Type emitter region and the first conduction type carrier accumulation layer being set to below the second conduction type base region, described first is conductive
Emitter metal Ohmic contact above type emitter region, the second conduction type type base area and the first conduction type drift region,
It further include the second conduction type being set in the first conduction type drift region on the section of the IGBT device
Floating layer, the second conduction type floating layer are located at the underface of the first conduction type carrier accumulation layer and the second conductive-type
Type floating layer and the first conduction type carrier accumulation layer are adjacent；Second conduction type floating layer is in the first conduction type drift region
Lateral length be not less than lateral length of the first conduction type carrier accumulation layer in the first conduction type drift region.
On the section of the IGBT device, the second conduction type source region is set in the second conduction type base region, it is described
Second conduction type source region is contacted with the first conduction type emitter region, and the second conduction type source region connects with emitter metal ohm
Touching.
On the section of the IGBT device, is also set up in first conduction type drift region and be symmetrically distributed in second and lead
Second conductive type impurity layer of electric type base area two sides, the second conductive type impurity layer is from the first conduction type drift region
Upper end extend vertically downward, the second conductive type impurity layer and emitter metal Ohmic contact, the second conductive type impurity layer
Lateral distance between the second conduction type base region is not less than 10 μm.
Depth of the second conductive type impurity layer in the first conduction type drift region is 4 μm~7 μm, and second is conductive
Depth of the type base area in the first conduction type drift region is 3 μm~7 μm, and the first conduction type carrier accumulation layer is first
Depth in conduction type drift region is 4 μm~7 μm, depth of the second conduction type floating layer in the first conduction type drift region
Degree is 5 μm~8 μm.
On the section of the IGBT device, Gate Electrode Conductive polycrystalline is also set up above the first conduction type drift region
Silicon, the Gate Electrode Conductive polysilicon are dielectrically separated from by insulation gate oxide with the first conduction type drift region；In the second conduction
The source contact openings of setting perforation Gate Electrode Conductive polysilicon and the gate oxide that insulate above type base area, are filled in source contact
Emitter metal in hole can be with the first conduction type emitter region and the second conduction type base region Ohmic contact, and emitter gold
Belong to and being isolated by insulating medium layer with Gate Electrode Conductive polysilicon insulation.
It further include being cut with the first adjacent conduction type of the first conduction type drift region on the section of the IGBT device
The second conduction type collecting zone is arranged in only layer on the first conduction type cutoff layer, in the second conduction type current collection
The collector electrode metal of Ohmic contact is set in area.
The material of the semiconductor substrate includes silicon, silicon carbide, GaAs or gallium nitride.
It is conductive for N-type power IGBT device, first in " first conduction type " and " the second conduction type " the two
Type refers to N-type, and the second conduction type is p-type；For p-type power IGBT device, the first conduction type and the second conduction type institute
The type of finger and N-type semiconductor device are exactly the opposite.
The advantages of the utility model: the second conduction type floating layer is set in the first conduction type drift region, and second leads
Electric type floating layer contacts with the first conduction type carrier accumulation layer and is located at the first conduction type carrier accumulation layer
Underface, utilize the second conduction type floating layer introduce PN junction and charge Electric Field Modulated effect, shield the first conductive-type
Type carrier accumulation layer is to the adverse effect of breakdown voltage, to improve the breakdown voltage of IGBT device；In the second conduction type
Base area two sides are symmetrical arranged the second conductive type impurity layer, the second conductive type impurity layer and emitter metal Ohmic contact, benefit
The transverse electric field distribution of the second conduction type base region Yu the first conduction type drift region can be improved with the second conductive type impurity layer,
And when off, hole split channel can be provided, turn-off power loss is effectively reduced, it is compatible with prior art, securely and reliably.
Detailed description of the invention
Fig. 1 is the schematic diagram of the utility model.
Description of symbols: 1-P+ collecting zone, 2-N type cutoff layer, 3-N type drift region, 4-P type floating layer, 5-P type impurity
Layer, 6-N type carrier accumulation layer, 7-P type base area, 8-N+ emitter region, 9-P+ source region, 10- insulation gate oxide, 11- grid are led
Electric polysilicon, 12- collector electrode metal, 13- source contact openings and 14- buried layer contact hole.
Specific embodiment
Below with reference to specific drawings and examples, the utility model is described in further detail.
As shown in Figure 1: in order to which electric field strength is effectively reduced, by taking N-type IGBT device as an example, the utility model includes partly leading
Structure base board and the structure cell being set on the semiconductor substrate, semiconductor substrate include N-type drift region 3；
On the section of the IGBT device, the structure cell uses plane cellular, and structure cell includes that setting N-type is floated
The p-type base area 7 moved in area 3, the N+ emitter region 8 that is set in the p-type base area 7 and P+ source region 9 and it is set to p-type base area 7
The N-type carrier accumulation layer 6 of lower section, emitter metal ohm of 3 top of the N+ emitter region 8, P+ source region 9 and N-type drift region
Contact,
It further include the p-type floating layer 4 being set in N-type drift region 3 on the section of the IGBT device, the p-type is floating
Dead level 4 is located at the underface of N-type carrier accumulation layer 6 and p-type floating layer 4 and N-type carrier accumulation layer 6 are adjacent；P-type floating layer
4 N-type drift region 3 lateral length be not less than lateral length of the N-type carrier accumulation layer 6 in N-type drift region 3.
Specifically, the material of the semiconductor substrate includes silicon, silicon carbide, GaAs or gallium nitride.Certainly, semiconductor-based
Plate can also use other common semiconductor materials, and specific material type, which can according to need, to be selected, no longer superfluous herein
It states.Semiconductor substrate includes N-type drift region 3, can the cellular needed for the front preparation of semiconductor substrate using N-type drift region 3
Structure, in the utility model embodiment, structure cell uses plane cellular.
In the utility model embodiment, to each cellular, including the p-type base area 7 being set in N-type drift region 3, each
The symmetrical N+ emitter region 8 of setting in p-type base area 7, the doping that the doping concentration of N+ emitter region 8 is greater than N-type drift region 3 are dense
N-type carrier accumulation layer 6 is arranged in the lower section of p-type base area 7 in degree, and N-type carrier accumulation layer 6 is contacted with the bottom of p-type base area 7,
The doping concentration of N-type carrier accumulation layer 6 is greater than the doping concentration of N-type drift region 3, can be effective using N-type carrier accumulation layer 6
Reduce conduction voltage drop.N+ emitter region 8, p-type base area 3 and emitter metal Ohmic contact, so that the emitter of IGBT device is formed,
Distribution situation of the emitter metal above N-type drift region 3, but emitter metal and N+ emitter region 8, P+ are not showed that in Fig. 1
Ohmic contact between source region 9 and the distribution situation above N-type drift region 3 are known to those skilled in the art, herein
It repeats no more.
In order to which electric field strength is effectively reduced, p-type floating layer 4 is also set up in N-type drift region 3, p-type floating layer 4 is located at N
The underface of type carrier accumulation layer 6, and p-type floating layer 4 and N-type carrier accumulation layer 6 are adjacent, the transverse direction of p-type floating layer 4 is long
Spend the lateral length of not small N-type carrier accumulation layer 6.When it is implemented, on the section of IGBT device, lateral length specifically with
Connection direction in p-type base area 7 between two N+ emitter region 8 is consistent.After p-type floating layer 4 is set in N-type drift region 3, benefit
The electric field strength at p-type base area 7 and 6 linkage interface of N-type carrier accumulation layer can be reduced with P floating layer 4, makes pressure-resistant raising；Its
Principle is to form the additional longitudinal electric field and original of additional PN junction generation by introducing P floating layer 4 and N-type carrier accumulation layer 6
Some p-type base areas 7 are overlapped with the electric field that N-type carrier accumulation layer 6 is formed and couple, and field distribution becomes rectangle from triangle
Play the role of electric Field Optimization, causes so as to avoid due to p-type base area 7 and 6 interface spike electric field of N-type carrier accumulation layer
Breakdown in advance, and then achieve the purpose that improve device breakdown voltage.Carry p-type base area 7 and N-type using p-type floating layer 4
The electric field spike for flowing sub- 6 interface of accumulation layer is flattened, and modulates electric field, shields highly doped N type carrier accumulation layer 6
To the adverse effect of IGBT device breakdown voltage, to improve the breakdown voltage of IGBT device.
Further, on the section of the IGBT device, P+ source region 9 is set in p-type base area 7, the P+ source region 9 with
N+ emitter region 8 contacts, P+ source region 9 and emitter metal Ohmic contact.
In the utility model embodiment, P+ source region 9 is located in p-type base area 7, and the doping concentration of P+ source region 9 is greater than p-type base area
7 doping concentration, depth of the P+ source region 9 in p-type base area 7 is greater than the depth of N+ emitter region 8, on the section of IGBT device,
Two N+ emitter region 8 are connected by P+ source region 9, and after the connection of N+ emitter region 8, P+ source region 9, emitter metal directly emits with N+
Area 8,9 Ohmic contact of P+ source region, i.e. emitter metal are electrically connected by P+ source region 9 with p-type base area 7.
Further, it on the section of the IGBT device, is also set up in the N-type drift region 3 and is symmetrically distributed in p-type
The p type impurity layer 5 of 7 two sides of base area, the p type impurity layer 5 extend vertically downward from the upper end of N-type drift region 3, p type impurity layer 5
With emitter metal Ohmic contact, the lateral distance between p type impurity layer 5 and p-type base area 7 is not less than 10 μm.
In the utility model embodiment, on the section of IGBT device, p type impurity layer 5 is symmetrically distributed in p-type base area 7
Two sides, p type impurity layer 5 extend vertically downward from the upper end face of N-type drift region 3, and emitter is arranged above N-type drift region 3
After metal, the emitter metal also with 5 Ohmic contact of p type impurity layer, between p type impurity layer 5 and p-type base area 7 laterally away from
From not less than 10 μm；In addition, N-type carrier accumulation layer 6, p-type floating layer 4 cannot be contacted with p type impurity layer 5.
In addition, depth of the p type impurity layer 5 in N-type drift region 3 is 4 μm~7 μm, p-type base area 7 is in N-type drift region
Depth in 3 is 3 μm~7 μm, and depth of the N-type carrier accumulation layer 6 in N-type drift region 3 is 4 μm~7 μm, p-type floating layer 4
Depth in N-type drift region 3 is 5 μm~8 μm.
In the utility model embodiment, the width of p-type base area 7, which can according to need, to be set, N-type carrier accumulation layer
6 width is not less than the width of p-type base area 7, and the concentration between the concentration and p-type base area 7 of p type impurity layer 5 can according to need
It is selected.After p type impurity layer 5 is set, introduce what additional p type impurity layer 5 was generated with the PN junction that N-type drift region 3 is formed
Attachment and original p-type base area 7 are superimposed with 3 transverse electric field of N-type drift region, and field distribution is made to have triangle to become rectangle, thus
Corner's electric field spike is effectively reduced.It, can be with so when off again since p type impurity layer 5 is connect by metal with emitter
Hole split channel is provided, turn-off power loss can be effectively reduced.
Further, on the section of the IGBT device, Gate Electrode Conductive polycrystalline is also set up in the top of N-type drift region 3
Silicon 11, the Gate Electrode Conductive polysilicon 11 are dielectrically separated from by the gate oxide 10 that insulate with N-type drift region 3；On p-type base area 7
The source contact openings 13 of side's setting perforation Gate Electrode Conductive polysilicon 11 and the gate oxide 10 that insulate, are filled in source contact openings 13
Interior emitter metal can with 7 Ohmic contact of N+ emitter region 8 and p-type base area, and emitter metal by insulating medium layer with
Gate Electrode Conductive polysilicon 11 is dielectrically separated from.
In the utility model embodiment, gate electrode needed for structure cell can be formed by Gate Electrode Conductive polysilicon 11,
Certainly, when forming gate electrode, Gate Electrode Conductive polysilicon 11 also needs to need and gate metal layer Ohmic contact, gate metal layer
It also is located at 3 top of N-type drift region, is not shown between gate metal layer, gate metal layer and Gate Electrode Conductive polysilicon 11 in Fig. 1
Ohmic contact situation, but the connection mated condition between gate metal layer, gate metal layer and Gate Electrode Conductive polysilicon 11 is
Known to those skilled in the art, details are not described herein again.After Gate Electrode Conductive polysilicon 11 is arranged, Gate Electrode Conductive polysilicon 11 is needed
It to be dielectrically separated from by insulation gate oxide 10 with N-type drift region 3, insulation gate oxide 10 can be silicon dioxide layer.
After Gate Electrode Conductive polysilicon 11 and insulation gate oxide 10 is arranged in the front in N-type drift region 3, in order to reality
Ohmic contact between existing emitter metal and N+ emitter region 8, P+ source region 9 and p type impurity layer 5, needs in N+ emitter region 8, P
Source contact openings 13 are arranged in the surface of type source region 9, and buried layer contact hole 14 is arranged in the surface of p type impurity layer 5, and source electrode connects
Contact hole 13, buried layer contact hole 14 penetrate through Gate Electrode Conductive polysilicon 11, insulation gate oxide 10, when emitter metal is filled in source
After pole contact hole 13, emitter metal can be with N+ emitter region 8,9 Ohmic contact of P+ source region, and emitter metal is filled in buried layer and connects
It can be with 5 Ohmic contact of p type impurity layer after in contact hole 14.Certainly, device for simplicity does not show that emitter metal layer in Fig. 1
It is filled in source contact openings 13, the situation in buried layer contact hole 14, but specific filling process and filled distribution situation
It is known to those skilled in the art, details are not described herein again.When it is implemented, in source contact openings 13, buried layer contact hole 14
Inner wall also set up insulating medium layer so that emitter metal by insulating medium layer and Gate Electrode Conductive polysilicon 11 insulate every
Can be prepared using the common insulating materials of the art from, insulating medium layer, if be able to achieve emitter metal with
Being dielectrically separated between Gate Electrode Conductive polysilicon 11, and will not be described here in detail.
It further, further include the N-type cutoff layer 2 adjacent with N-type drift region 3 on the section of the IGBT device,
P+ collecting zone 1 is set on the N-type cutoff layer 2, the collector electrode metal 12 of Ohmic contact is set on the P+ collecting zone 1.
In the utility model embodiment, the doping concentration of N-type cutoff layer 2 is greater than the doping concentration of N-type drift region 3, N-type drift
The thickness for moving area 3 is greater than the thickness of N-type cutoff layer 2.P+ collecting zone 1 is set on N-type cutoff layer 2, and N-type cutoff layer 2 and N-type are floated
Area 3, the adjoining of P+ collecting zone 1 are moved, N-type cutoff layer 2 is between P+ collecting zone 1, N-type drift region 3.It is arranged on P+ collecting zone 1
Collector electrode metal 12, collector electrode metal 12 and 1 Ohmic contact of P+ collecting zone are cooperated using collector electrode metal 12 and P+ collecting zone 1
The collector of IGBT device can be formed.
Claims (7)
1. a kind of planar gate IGBT device, including semiconductor substrate and the structure cell being set on the semiconductor substrate,
Semiconductor substrate includes the first conduction type silicon；
On the section of the IGBT device, the structure cell uses plane cellular, and structure cell includes being set to first to lead
The second conduction type base region in electric type drift region, the first conduction type being set in second conduction type base region hair
The the first conduction type carrier accumulation layer penetrating area and being set to below the second conduction type base region, first conduction type
The emitter metal Ohmic contact of top in emitter region, the second conduction type type base area and the first conduction type drift region,
It is characterized in:
It further include the second conduction type floating being set in the first conduction type drift region on the section of the IGBT device
Layer, the second conduction type floating layer is located at the underface of the first conduction type carrier accumulation layer and the second conduction type is floating
Dead level and the first conduction type carrier accumulation layer are adjacent；Second conduction type floating layer is in the first conduction type drift region
Lateral length is not less than lateral length of the first conduction type carrier accumulation layer in the first conduction type drift region.
2. planar gate IGBT device according to claim 1, it is characterized in that: on the section of the IGBT device,
Second conduction type source region, the second conduction type source region and the first conduction type emitter region are set in two conduction type base regions
Contact, the second conduction type source region and emitter metal Ohmic contact.
3. planar gate IGBT device according to claim 1, it is characterized in that: on the section of the IGBT device, in institute
State the second conductive type impurity for also setting up in the first conduction type drift region and being symmetrically distributed in the second conduction type base region two sides
Layer, the second conductive type impurity layer extend vertically downward from the upper end in the first conduction type drift region, the second conductive-type
Type impurity layer and emitter metal Ohmic contact, the lateral distance between the second conductive type impurity layer and the second conduction type base region
Not less than 10 μm.
4. planar gate IGBT device according to claim 3, it is characterized in that: the second conductive type impurity layer is first
Depth in conduction type drift region is 4 μm~7 μm, depth of second conduction type base region in the first conduction type drift region
Degree is 3 μm~7 μm, and depth of the first conduction type carrier accumulation layer in the first conduction type drift region is 4 μm~7 μm,
Depth of the second conduction type floating layer in the first conduction type drift region is 5 μm~8 μm.
5. planar gate IGBT device according to claim 1, it is characterized in that: on the section of the IGBT device,
Top in one conduction type drift region also sets up Gate Electrode Conductive polysilicon, and the Gate Electrode Conductive polysilicon passes through insulation gate oxidation
Layer is dielectrically separated from the first conduction type drift region；Above the second conduction type base region setting perforation Gate Electrode Conductive polysilicon with
And the source contact openings of insulation gate oxide, the emitter metal being filled in source contact openings can emit with the first conduction type
Area and the second conduction type base region Ohmic contact, and emitter metal passes through insulating medium layer and Gate Electrode Conductive polysilicon insulation
Isolation.
6. planar gate IGBT device according to claim 1, it is characterized in that: also being wrapped on the section of the IGBT device
The first conduction type cutoff layer adjacent with the first conduction type drift region is included, is arranged on the first conduction type cutoff layer
The collector electrode metal of Ohmic contact is arranged in second conduction type collecting zone on the second conduction type collecting zone.
7. planar gate IGBT device according to claim 1, it is characterized in that: the material of the semiconductor substrate include silicon,
Silicon carbide, GaAs or gallium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821357767.XU CN208460769U (en) | 2018-08-22 | 2018-08-22 | Planar gate IGBT device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821357767.XU CN208460769U (en) | 2018-08-22 | 2018-08-22 | Planar gate IGBT device |
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| Publication Number | Publication Date |
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| CN208460769U true CN208460769U (en) | 2019-02-01 |
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| CN201821357767.XU Withdrawn - After Issue CN208460769U (en) | 2018-08-22 | 2018-08-22 | Planar gate IGBT device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899362A (en) * | 2018-08-22 | 2018-11-27 | 江苏中科君芯科技有限公司 | Planar gate IGBT device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899362A (en) * | 2018-08-22 | 2018-11-27 | 江苏中科君芯科技有限公司 | Planar gate IGBT device |
| CN108899362B (en) * | 2018-08-22 | 2024-04-12 | 江苏中科君芯科技有限公司 | Planar gate IGBT device |
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