CN208224882U - A kind of current limliting low-pressure linear pressure stabilizing source circuit - Google Patents
A kind of current limliting low-pressure linear pressure stabilizing source circuit Download PDFInfo
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- CN208224882U CN208224882U CN201820727878.9U CN201820727878U CN208224882U CN 208224882 U CN208224882 U CN 208224882U CN 201820727878 U CN201820727878 U CN 201820727878U CN 208224882 U CN208224882 U CN 208224882U
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- pmos tube
- current
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- resistance
- tube
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Abstract
The utility model discloses a kind of current limliting low-pressure linear pressure stabilizing source circuits, including a reference voltage unit, an error amplifier, a NMOS, three PMOS, four resistance, a capacitor and current limiting element, wherein current limiting element is PMOS tube, first PMOS tube, the second PMOS tube, 3rd resistor and the 4th resistance are current sampling module, third PMOS tube is large scale power tube, first capacitor is the outer bulky capacitor of piece, is placed on chip exterior.The utility model provides a kind of current limliting low-pressure linear pressure stabilizing source circuit, can be limited by output electric current of the current limiting element to large scale power tube, avoids generating high current, burns out chip, scheme simple possible.
Description
Technical field
The utility model belongs to integrated circuit fields, is related to a kind of current limliting low-pressure linear pressure stabilizing source circuit.
Background technique
With the rapid development of electronic technology, various portable electronics play multimedia data stream, audio, are clearer
The demands such as display and more amusements are constantly promoted, and high performance power management scheme becomes more and more important.Low pressure difference linearity is steady
Depressor (Low Dropout Regulator, LDO) is because of the noise that its is at low cost, encapsulation is easy, peripheral equipment is few, ultralow, high electricity
Source inhibits one of the power solution than becoming great competitiveness with characteristics such as micro energy loses.
Traditional low pressure difference linear voltage regulator provides a little stable voltage to chip, needs a very large-sized function
Rate pipe, and this large-sized power tube be easy when powering on or being powered the irregular working of chip generate one it is non-
Often big electric current, high current can make chip be easy to burn out, and there are big risks.
Utility model content
The purpose of this utility model is to provide a kind of current limliting low-pressure linear pressure stabilizing source circuits, can pass through current limiting element pair
The output electric current of large scale power tube is limited, and is avoided generating high current, is burnt out chip.
To solve the above-mentioned problems, the utility model provides a kind of current limliting low-pressure linear pressure stabilizing source circuit comprising one
Reference voltage unit, an error amplifier, a NMOS tube, three PMOS tube, four resistance and a capacitor；
Reference voltage unit is connected with the positive input terminal of error amplifier, the output end Y of error amplifier and first
The grid of NMOS tube is connected, and the source electrode of the first NMOS tube is connected with the ground end gnd, the drain electrode of the first NMOS tube, the first PMOS
The grid of pipe, the drain electrode of the first PMOS tube, the grid of the second PMOS tube, third PMOS tube grid be connected to node B, first
The source electrode of PMOS tube is connected with one end of 3rd resistor, and the source electrode of the second PMOS tube is connected with one end of the 4th resistance, the
The other end of three resistance, the other end of the 4th resistance, third PMOS tube source electrode be connected to supply voltage vdd；Third PMOS tube
Drain electrode, one end of first resistor and one end of first capacitor be connected to vout point, the other end of first resistor, second resistance
The drain electrode of one end and the second PMOS tube is connected to A point, and the other end of second resistance, the other end of first capacitor are connected with ground terminal
It connects；
It further include current limiting element MP4, current limiting element is PMOS tube, and the grid of current limiting element is connected with C point, current limiting element
Source electrode be connected with supply voltage, the drain electrode of current limiting element is connected with B point.
Third PMOS tube is large scale power tube, output voltage can be maintained steady in the case where large load current changes
It is fixed.Four resistance are polysilicon resistance, the matching performance having had when domain is realized, so that circuit is generated one and accurately stablize
Voltage.First capacitor is the outer bulky capacitor of piece, is placed on chip exterior.
The utility model has the beneficial effects that the current limliting low-pressure linear pressure stabilizing source circuit in the utility model can pass through limit
Fluid element limits the output electric current of the power tube of circuit, avoids large scale power tube from generating high current, burns out chip, side
Case simple possible.
Detailed description of the invention
Fig. 1 is the circuit diagram of the utility model.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and examples.Following embodiment be it is descriptive, no
It is restrictive, protection scope of this utility model cannot be limited by this.
As shown in Figure 1, a kind of current limliting low-pressure linear pressure stabilizing source circuit, including a reference voltage unit, an error are put
Big device, a NMOS tube, three PMOS tube, four resistance and a capacitor；
Reference voltage unit is connected with the positive input terminal of error amplifier, the output end of error amplifier and the first NMOS
The grid of pipe is connected, and the source electrode of the first NMOS tube is connected with ground terminal, the drain electrode of the first NMOS tube, the first PMOS tube grid
Pole, the drain electrode of the first PMOS tube, the grid of the second PMOS tube, third PMOS tube grid be connected to section B point, the first PMOS tube
Source electrode is connected with one end of 3rd resistor, and the source electrode of the second PMOS tube is connected with one end of the 4th resistance, 3rd resistor
The other end, the other end of the 4th resistance, third PMOS tube source electrode be connected to supply voltage；The drain electrode of third PMOS tube, first
One end of resistance and one end of first capacitor are connected to vout point, one end and second of the other end of first resistor, second resistance
The drain electrode of PMOS tube is connected to A point, and the other end of second resistance, the other end of first capacitor are connected with ground terminal；
MP4 is current limiting element, and the grid of current limiting element is connected with C point, and the source electrode of current limiting element is connected with supply voltage
It connects, the drain electrode of current limiting element is connected with B point.
When big electric current occurs for large scale power tube, due to circuit negative-feedback, B point voltage can be reduced in circuit, and first
PMOS tube, the second PMOS tube, 3rd resistor and the 4th resistance sample large scale power tube current, due to B point voltage
Reduce, the electric current for flowing through the 4th resistance will increase, therefore the voltage of C point can also reduce in circuit, the grid of current limiting element MP4 and
Source electrode voltage difference of the two ends becomes larger, and current limiting element enters working condition, generates an electric current and charges to B point, B is made to press rising, this
Sample current limiting element limits B point brownout, so that limiting third PMOS tube generates high current, reaches current limitation effect.
The principles of the present invention are: when large scale power tube current is excessive, current limiting element enters current limliting working condition,
Current limiting element generates an electric current and charges to B point, prevents B point voltage from declining very low, limits the big of low-pressure linear source of stable pressure
Size power tube exports super-high-current, and high current is avoided to destroy chip, scheme simple possible.
The utility model is described in detail in conjunction with attached drawing above, but the utility model is not limited solely to above-mentioned tool
Body embodiment, those skilled in the art can also not depart from the utility model aims according to the knowledge having
Under the premise of make a variety of changes.
Claims (7)
1. a kind of current limliting low-pressure linear pressure stabilizing source circuit, including a reference voltage unit, an error amplifier, one
NMOS, three PMOS, four resistance and a capacitor；
Reference voltage unit is connected with the positive input terminal of error amplifier, the output end of error amplifier and the first NMOS tube
Grid is connected, and the source electrode of the first NMOS tube is connected with ground terminal, the drain electrode of the first NMOS tube, the grid of the first PMOS tube,
The drain electrode of one PMOS tube, the second PMOS tube grid be connected with the grid of third PMOS tube, the source electrode of the first PMOS tube and
One end of three resistance is connected, and the source electrode of the second PMOS tube is connected with one end of the 4th resistance, the other end of 3rd resistor,
The other end of four resistance, the source electrode of third PMOS tube are connected to supply voltage；The drain electrode of third PMOS tube, first resistor one end
The output node of low-pressure linear pressure stabilizing source circuit, the other end of first resistor, second resistance are connected to one end of first capacitor
One end be connected with the drain electrode of the second PMOS tube, the other end of second resistance, the other end of first capacitor are connected with ground terminal
It connects；
It is characterized by also including the current limiting element being made of the 4th PMOS tube, the grid of current limiting element and the second PMOS tube
Source electrode is connected, and the source electrode of current limiting element is connected with supply voltage, the drain electrode and the drain electrode phase of the first NMOS tube of current limiting element
Connection.
2. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: the current limiting element is PMOS
Pipe.
3. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: when occurring big electric current in circuit
When, current limiting element enters current limliting working condition, and current limiting element generates an electric current to the grid of the first PMOS tube and the second PMOS tube
The charging of pole node, prevents the gate node voltage of the first PMOS tube and the second PMOS tube from declining very low, limits low-pressure linear
Source of stable pressure circuit output super-high-current avoids high current from destroying chip.
4. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: the first PMOS tube, the 2nd PMOS
Pipe, 3rd resistor and the 4th resistance are current sampling module, for sampling the high current of efferent duct.
5. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: the third PMOS tube is big ruler
Very little PMOS tube can maintain output voltage stabilization in the case where large load current changes.
6. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: the first resistor, the second electricity
Resistance, 3rd resistor and the 4th resistance are polysilicon resistance, and the matching performance having had when domain is realized makes circuit generate one
Accurate burning voltage.
7. current limliting low-pressure linear pressure stabilizing source circuit as described in claim 1, it is characterised in that: the first capacitor is big outside piece
Capacitor is placed on chip exterior.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820727878.9U CN208224882U (en) | 2018-05-15 | 2018-05-15 | A kind of current limliting low-pressure linear pressure stabilizing source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820727878.9U CN208224882U (en) | 2018-05-15 | 2018-05-15 | A kind of current limliting low-pressure linear pressure stabilizing source circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208224882U true CN208224882U (en) | 2018-12-11 |
Family
ID=64508845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820727878.9U Expired - Fee Related CN208224882U (en) | 2018-05-15 | 2018-05-15 | A kind of current limliting low-pressure linear pressure stabilizing source circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208224882U (en) |
-
2018
- 2018-05-15 CN CN201820727878.9U patent/CN208224882U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181211 Termination date: 20190515 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |