CN208158591U - A kind of HD-SDI multi-service HD video optical transmitter and receiver - Google Patents
A kind of HD-SDI multi-service HD video optical transmitter and receiver Download PDFInfo
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- CN208158591U CN208158591U CN201820624324.6U CN201820624324U CN208158591U CN 208158591 U CN208158591 U CN 208158591U CN 201820624324 U CN201820624324 U CN 201820624324U CN 208158591 U CN208158591 U CN 208158591U
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- 230000003287 optical effect Effects 0.000 title claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 84
- 238000006243 chemical reaction Methods 0.000 claims description 44
- 230000000087 stabilizing effect Effects 0.000 claims description 31
- 230000005611 electricity Effects 0.000 claims description 11
- 230000003044 adaptive effect Effects 0.000 claims description 9
- 238000005303 weighing Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 5
- 230000006872 improvement Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
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- 230000008054 signal transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
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- 230000035772 mutation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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Abstract
The utility model discloses a kind of HD-SDI multi-service HD video optical transmitter and receivers.The advantages of the utility model：Whether re-clocking circuit detects the clock signal in signal abnormal, and abnormal signal is reset, the case where clock can not restore after situations such as avoiding the occurrence of power-off, clock can not restore that data transmission is made mistake occur, the case where can not even transmitting, improves stability of the signal in late-class circuit.
Description
Technical field
The utility model relates to signal transmission apparatus field, more particularly to a kind of HD-SDI multi-service high definition view
Frequency optical transmitter and receiver.
Background technique
HD-SDI optical transmitter and receiver is the equipment for converting sdi signal and optical signal mutually.The principle of SDI optical transmitter and receiver is transmitting terminal
Sdi signal is re-encoded by becoming optical signal, the data that receiving end receives laser diode after laser modulation as SDI letter
Number.
In existing HD-SDI optical transmitter and receiver use process, the case where clock can not restore after situations such as powering off, clock
The case where can not restoring that data transmission is made mistake occur, or even can not transmitting.
Utility model content
In view of the deficienciess of the prior art, the purpose of this utility model is to provide a kind of with clock weight timing function
HD-SDI multi-service HD video optical transmitter and receiver.
To achieve the above object, the utility model provides following technical solution：A kind of HD-SDI multi-service HD video
Optical transmitter and receiver includes：Power circuit, governor circuit and transmission circuit, the power circuit are connect with governor circuit, give master control electricity
Road power supply, the transmission circuit connection governor circuit and external interface, receive and send signal, the transmission circuit includes equal
Weigh circuit, re-clocking circuit, driving circuit and conversion circuit, when the equalizing circuit connection governor circuit and clock are reset
Circuit, the re-clocking circuit are connect with driving circuit and conversion circuit respectively, and the driving circuit and conversion circuit connect
It connects, the conversion circuit is connect with external interface, and the re-clocking circuit includes weight timing chip U9 and its periphery electricity
Road, the heavy timing chip U9 connection equalizing circuit, driving circuit and conversion circuit, receiver equalization circuitry output signal after it is defeated
Out.
The equalizing circuit includes adaptive chip U5 as a further improvement of the utility model, described adaptive
Chip U5 has input pin SDI, input pin/SDI, output pin SDO and output pin/SDO, and the input port SDI is coupled with capacitor
It is grounded after being coupled with resistance R5 after C4, the tie point of the capacitor C4 and resistance R5 are coupled with inductance L1 and resistance parallel with one another
Be coupled to governor circuit after R6, the input pin/SDI is coupled with after capacitor C10 be coupled with resistance R12 after be grounded, the output
Foot SDO is coupled to the input pin SDI of weight timing chip U9, and the output pin SDO, which is coupled with after resistance R29, to be coupled to when resetting
Input pin/SDI of chip U9, the output pin/SDO are coupled to input pin/SDI of weight timing chip U9.
The driving circuit includes driving chip M1, the driving chip as a further improvement of the utility model,
M1 has input pin TD, input pin/TD, output pin SD, output pin RD, output pin/RD, supply pin VCCTX and supply pin
VCCRX, the input pin TD are coupled to the output pin SDO, the input pin/TD for weighing timing chip U9 after being coupled with resistance R40
It is coupled with the output pin SDO that weight timing chip U9 is coupled to after resistance R41, the input pin TD is coupled after being coupled with resistance R48
To input pin/TD, the input pin TD is coupled to power supply VCC33_T after being coupled with resistance R3, is grounded after being coupled with resistance R8,
The input pin TD is coupled to power supply VCC33_T after being coupled with resistance R4, is grounded after being coupled with resistance R29, the supply pin
VCCTX is grounded after being coupled with capacitor C1, the supply pin VCCTX is coupled with after inductance L3 be coupled with capacitor C12 after be grounded, it is described
The tie point of inductance L3 and capacitor C12 is coupled to power supply VCC+3.3V, and the supply pin VCCRX is grounded after being coupled with capacitor C2,
The supply pin VCCRX is coupled with after inductance L4 be coupled with capacitor C13 after be grounded, the tie point of the inductance L4 and capacitor C13
It is coupled to power supply VCC+3.3V, the power supply VCC+3.3V is grounded after being coupled with electrolytic capacitor EC3, and the output pin SD is coupled with
It is exported after amplifying circuit.
The conversion circuit includes conversion chip U4, the conversion chip as a further improvement of the utility model,
The positive and negative anodes input pin of U4 is connect with the input pin TD of driving chip M1 and input pin/TD respectively, and the conversion chip U4 is just
Cathode output pin has been respectively coupled to be grounded after being coupled with capacitor C14 after being connected with each other after resistance R14 and resistance R15, the conversion
The positive output pin of chip U4 is coupled with after inductance L5 and resistance R16 parallel with one another be coupled with capacitor C15 after export.
The positive and negative anodes input pin of the conversion chip U4 and driving chip M1 as a further improvement of the utility model,
Input pin TD and input pin/TD between be in series with capacitor C17 and capacitor C16 respectively, the positive and negative anodes of the conversion chip U4 are defeated
Enter foot to be respectively coupled to be grounded after being coupled with capacitor C36 after being connected with each other after resistance R37 and resistance R38.
The power circuit includes voltage stabilizing chip U7, the voltage stabilizing chip as a further improvement of the utility model,
The input pin of U7 is coupled to power supply+24V after being coupled with switch 3F1, and the enabled foot of the voltage stabilizing chip U7 is coupled with resistance 3R23
After be coupled to input pin, the tie point of the switch 3F1 and power supply+24V is grounded after being coupled with diode 3DV1, the pressure stabilizing
The input pin of chip U7 is grounded after being coupled with electrolytic capacitor 3EC1, and the output pin of the voltage stabilizing chip U7 is coupled with defeated after inductance L6
Power supply VCC5 out, the power supply VCC5 are grounded after being coupled with capacitor 3C15 and electrolytic capacitor 3EC2 parallel with one another, the pressure stabilizing
The bootstrapping foot of chip U7 is coupled to output pin after being coupled with capacitor 3C14, and output pin is grounded after being coupled with diode 3ZD3, described
The tie point of inductance L6 and electrolytic capacitor 3EC2 is coupled with after resistance 3R19 be coupled with resistance 3R18 after be grounded, the resistance
3R19 is parallel with capacitor 3C11, and the feedback foot of the voltage stabilizing chip U7 is coupled to the tie point of resistance 3R19 Yu resistance 3R18.
Whether extremely the beneficial effects of the utility model, re-clocking circuit detect the clock signal in signal, and
The case where clock can not restore after situations such as resetting by abnormal signal, avoid the occurrence of power-off, clock can not restore
The case where making data transmission mistake occur, or even can not transmitting, improves stability of the signal in late-class circuit.
Detailed description of the invention
Fig. 1 is the flow diagram of the utility model；
Fig. 2 is the circuit diagram of equalizing circuit in Fig. 1；
Fig. 3 is the circuit diagram of re-clocking circuit in Fig. 1；
Fig. 4 is the circuit diagram of conversion circuit in Fig. 1；
Fig. 5 is the circuit diagram of driving circuit in Fig. 1；
Fig. 6 is the circuit diagram of power circuit in Fig. 1.
Detailed description of the invention：1, power circuit；2, governor circuit；3, transmission circuit；31, equalizing circuit；32, it is electric when clock is reset
Road；33, driving circuit；34, conversion circuit.
Specific embodiment
The utility model is described in further detail below in conjunction with embodiment given by attached drawing.
Referring to Fig.1, shown in Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6, a kind of HD-SDI multi-service HD video light of the present embodiment
Terminal includes：Power circuit 1, governor circuit 2 and transmission circuit 3, the power circuit 1 are connect with governor circuit 2, to master
It controls circuit 2 to power, the transmission circuit 3 connects governor circuit 2 and external interface, receives and send signal, the transmission circuit 3
It include equalizing circuit 31, re-clocking circuit 32, driving circuit 33 and conversion circuit 34, the connection of equalizing circuit 31 master
Control circuit 2 and re-clocking circuit 32, the re-clocking circuit 32 respectively with driving circuit 33 and conversion circuit 34
Connection, the driving circuit 33 are connect with conversion circuit 34, and the conversion circuit 34 is connect with external interface, and the clock is reset
When circuit 32 include weight timing chip U9 and its peripheral circuit, the heavy timing chip U9 connection equalizing circuit 31, driving are electric
Road 33 and conversion circuit 34, receiver equalization circuitry 31 export signal after export.
Through the above technical solutions, power circuit 1 works to the power supply of governor circuit 2, external signal is from external interface
Into, equalizing circuit 31 is first passed through, equalizing circuit 31 is promoted and is compensated to deamplification in corresponding frequency range, from
And last output and input is made to tend to be identical, signal enters re-clocking circuit 32 later, and weight timing chip U9 receives letter
Number detection signal in clock signal after and export, when the clock signal in signal is without exception, weight timing chip U9 receive letter
Number and export；When the clock signal exception in signal, after resetting clock to signal after weight timing chip U9 reception signal
Output, the crystal oscillator 7X1 of weight timing chip U9 connection give weight timing chip U9 to provide stable clock signal, and signal enters later
Driving circuit 33 and conversion circuit 34, driving circuit 33 receive signal after export, conversion circuit 34 receive signal after by signal into
Exported after row conversion, whether re-clocking circuit 32 detects the clock signal in signal abnormal, and by abnormal signal into
The case where clock can not restore after situations such as row is reset, and avoids the occurrence of power-off, clock can not restore data transmission occur
Mistake, or even the case where can not transmit, improve stability of the signal in late-class circuit.
As a kind of improved specific embodiment, the equalizing circuit 31 includes adaptive chip U5, described adaptive
Answer chip U5 that there is input pin SDI, input pin/SDI, output pin SDO and output pin/SDO, the input port SDI is coupled with electricity
Hold and be grounded after being coupled with resistance R5 after C4, the tie point of the capacitor C4 and resistance R5 be coupled with inductance L1 parallel with one another and
Be coupled to governor circuit 2 after resistance R6, the input pin/SDI is coupled with after capacitor C10 be coupled with resistance R12 after be grounded, institute
The input pin SDI that output pin SDO is coupled to weight timing chip U9 is stated, the output pin SDO is coupled to weight after being coupled with resistance R29
Input pin/SDI of timing chip U9, the output pin/SDO are coupled to input pin/SDI of weight timing chip U9.
Through the above technical solutions, adaptive chip U5 can be LMH0344, signal passes through after inductance L1 and resistance R6
It is input to adaptive chip U5 after crossing capacitor C4, adaptive chip U5 handles the signal of input, to corresponding frequency model
Enclose it is interior deamplification is promoted and is compensated after export, inductance L1 and resistance R6 screen signal, and inductance L1 and
The left and right, and Electromagnetic Interference always jointly resistance R6, further increases the effect of stabling current, and resistance R29 is arranged in data
Between line, the stability of improve data transfer, and input pin/SDI is coupled with after capacitor C10 after being coupled with resistance R12 and is grounded,
Keep input pin/SDI more stable, the surge that signal occurs in resistance R5 enters ground after too small resistance, further increases circuit
Stability.
As a kind of improved specific embodiment, the driving circuit 33 includes driving chip M1, the driving core
Piece M1 has input pin TD, input pin/TD, output pin SD, output pin RD, output pin/RD, supply pin VCCTX and supply pin
VCCRX, the input pin TD are coupled to the output pin SD0, the input pin/TD for weighing timing chip U9 after being coupled with resistance R40
It is coupled with the output pin SDO that weight timing chip U9 is coupled to after resistance R41, the input pin TD is coupled after being coupled with resistance R48
To input pin/TD, the input pin TD is coupled to power supply VCC33_T after being coupled with resistance R3, is grounded after being coupled with resistance R8, institute
It states after input pin TD is coupled with resistance R4 and is coupled to power supply VCC33_T, be grounded after being coupled with resistance R29, the supply pin
VCCTX is grounded after being coupled with capacitor C1, the supply pin VCCTX is coupled with after inductance L3 be coupled with capacitor C12 after be grounded, institute
The tie point for stating inductance L3 and capacitor C12 is coupled to power supply VCC+3.3V, and the supply pin VCCRX is coupled with capacitor C2 and is followed by
Ground, the supply pin VCCRX is coupled with after inductance L4 be coupled with capacitor C13 after be grounded, the connection of the inductance L4 and capacitor C13
Point is coupled to power supply VCC+3.3V, and the power supply VCC+3.3V is grounded after being coupled with electrolytic capacitor EC3, the output pin SD coupling
It is exported after having amplifying circuit.
Through the above technical solutions, driving chip M1 uses dual power supply, receives and output is all made of independently-powered, be
It receives and output is not interfere with each other, and inductance L3 and capacitor C1, electrolytic capacitor EC3 and capacitor C12 filter received power supply
Wave and inductance L4 and capacitor C2, electrolytic capacitor EC3 and capacitor C13 are filtered the power supply of output, use an electrolytic capacitor
EC3 reduces component use, reduces cost, reduce pcb board in the case where not reducing filter effect.
As a kind of improved specific embodiment, the conversion circuit 34 includes conversion chip U4, the conversion core
The positive and negative anodes input pin of piece U4 is connect with the input pin TD of driving chip M1 and input pin/TD respectively, the conversion chip U4's
Positive and negative anodes output pin has been respectively coupled to be grounded after being coupled with capacitor C14 after being connected with each other after resistance R14 and resistance R15, and described turn
The positive output pin for changing chip U4 is coupled with after inductance L5 and resistance R16 parallel with one another be coupled with capacitor C15 after export.
Through the above technical solutions, conversion chip U4 can be GV8500, conversion chip U4 is converted after receiving signal,
And export the signal after conversion, resistance R14 and capacitor C14, resistance R15 and capacitor C14 are respectively formed LC filter circuit, improve defeated
The stability of signal out, and connect after inductance L5 and resistance R16 parallel connection with capacitor C15, output signal is filtered same
When, the electromagnetic interference between late-class circuit and conversion circuit 34 is also reduced, the stability of output signal is improved.
As a kind of improved specific embodiment, the positive and negative anodes input pin of the conversion chip U4 is with driving chip M1's
The positive and negative anodes input of capacitor C17 and capacitor C16, the conversion chip U4 are in series between input pin TD and input pin/TD respectively
Foot has been respectively coupled to be grounded after being coupled with capacitor C36 after being connected with each other after resistance R37 and resistance R38.
Through the above technical solutions, capacitor C16 and capacitor C17 are filtered signal, the stability of signal transmission is improved,
And resistance R37 and capacitor C36, resistance R38 and capacitor C36 are respectively formed LC filter circuit, further increase signal between circuit
The stability of transmission, meanwhile, resistance R37 and resistance R38 share a capacitor C36, in the case where not reducing filter effect, into
One step reduces component use, reduces cost, reduces pcb board.
As a kind of improved specific embodiment, the power circuit 1 includes voltage stabilizing chip U7, the voltage stabilizing chip
The input pin of U7 is coupled to power supply+24V after being coupled with switch 3F1, and the enabled foot of the voltage stabilizing chip U7 is coupled with resistance 3R23
After be coupled to input pin, the tie point of the switch 3F1 and power supply+24V is grounded after being coupled with diode 3DV1, the pressure stabilizing core
The input pin of piece U7 is grounded after being coupled with electrolytic capacitor 3EC1, and the output pin of the voltage stabilizing chip U7 exports after being coupled with inductance L6
Power supply VCC5, the power supply VCC5 are grounded after being coupled with capacitor 3C15 and electrolytic capacitor 3EC2 parallel with one another, the pressure stabilizing core
The bootstrapping foot of piece U7 is coupled to output pin after being coupled with capacitor 3C14, and output pin is grounded after being coupled with diode 3ZD3, the electricity
The tie point of sense L6 and electrolytic capacitor 3EC2 is coupled with after resistance 3R19 be coupled with resistance 3R18 after be grounded, the resistance 3R19
It is parallel with capacitor 3C11, the feedback foot of the voltage stabilizing chip U7 is coupled to the tie point of resistance 3R19 Yu resistance 3R18.
Through the above technical solutions, voltage stabilizing chip U7 can be MP2494DS, power input to input pin, in diode
3DV1 is Transient Suppression Diode, and the input port that voltage stabilizing chip U7 is arranged in avoids the surge in circuit from damaging voltage stabilizing chip U7,
Electrolytic capacitor 3EC1 and diode 3DV1 are formed into a loop, and improve the stability for being input to the power supply of voltage stabilizing chip U7, electricity when power-off
Capacitor 3EC1 electric discharge is solved, resistance 3R23 carries out current limliting, protects enabled foot, and then improve the stability of voltage stabilizing chip U7, pressure stabilizing core
Piece U7 exports the power supply signal after pressure stabilizing, and capacitor 3C14 connection output pin and bootstrapping foot allow voltage stabilizing chip U7 to boot, improve
The stability of voltage stabilizing chip U7 work, is output to later on inductance L6, and inductance L6 stablizes the power supply signal of output, resistance 3R19
Output signal is divided with resistance 3R18, feedback foot is connected thereto acquisition signal, and then adjusts output signal, believes output
Number more stable, feedback foot receives the signal after partial pressure, avoids surge impact damage feedback foot, improves voltage stabilizing chip U7 work
Stability, when capacitor 3C11 is fluctuated suddenly primarily directed to input voltage or output loading is fluctuated suddenly, output voltage is generated
Increase feedback quantity (i.e. feedback intensity) when variation and reaches stable with timely adjustment output.Accelerate the dynamic response mistake of power supply
Journey avoids over control so that output pulsation range reduces when input voltage mutation or load sudden change, increases stability, output
Capacitor C15 and electrolytic capacitor 3EC2 parallel with one another are set on power supply VCC5, while improving output stability, after also avoiding
Parasitic couplings between grade circuit and power circuit 1 improve the stability of HD-SDI multi-service HD video optical transmitter and receiver work.
The above is only the preferred embodiment of the utility model, and the protection scope of the utility model is not limited merely to
Above-described embodiment, technical solution belonging to the idea of the present invention belong to the protection scope of the utility model.It should refer to
Out, for those skilled in the art, it is without departing from the principle of the utility model it is several improvement and
Retouching, these improvements and modifications also should be regarded as the protection scope of the utility model.
Claims (6)
1. a kind of HD-SDI multi-service HD video optical transmitter and receiver, includes：Power circuit (1), governor circuit (2) and transmission circuit
(3), the power circuit (1) connect with governor circuit (2), powers to governor circuit (2), transmission circuit (3) the connection master
Circuit (2) and external interface are controlled, receives and sends signal, it is characterised in that：The transmission circuit (3) includes equalizing circuit
(31), re-clocking circuit (32), driving circuit (33) and conversion circuit (34), equalizing circuit (31) the connection master control electricity
Road (2) and re-clocking circuit (32), the re-clocking circuit (32) respectively with driving circuit (33) and conversion circuit
(34) it connects, the driving circuit (33) connect with conversion circuit (34), and the conversion circuit (34) connect with external interface, institute
Stating re-clocking circuit (32) includes weight timing chip U9 and its peripheral circuit, the balanced electricity of heavy timing chip U9 connection
Road (31), driving circuit (33) and conversion circuit (34), receiver equalization circuitry (31) output signal after export.
2. HD-SDI multi-service HD video optical transmitter and receiver according to claim 1, it is characterised in that：The equalizing circuit
It (31) include adaptive chip U5, the adaptive chip U5 has input pin SDI, input pin/SDI, output pin SDO and defeated
Foot/SDO out, the input port SDI is coupled with after capacitor C4 be coupled with resistance R5 after be grounded, the company of the capacitor C4 and resistance R5
Contact is coupled to governor circuit (2) after being coupled with inductance L1 and resistance R6 parallel with one another, and the input pin/SDI is coupled with electricity
Hold and be grounded after being coupled with resistance R12 after C10, the output pin SDO is coupled to the input pin SDI of weight timing chip U9, described defeated
Foot SDO is coupled to the input pin/SDI for weighing timing chip U9 after being coupled with resistance R29 out, and the output pin/SDO, which is coupled to, to be reset
When chip U9 input pin/SDI.
3. HD-SDI multi-service HD video optical transmitter and receiver according to claim 2, it is characterised in that：The driving circuit
(33) include driving chip M1, the driving chip M1 have input pin TD, input pin/TD, output pin SD, output pin RD,
Output pin/RD, supply pin VCCTX and supply pin VCCRX, the input pin TD are coupled to core when resetting after being coupled with resistance R40
The output pin SDO, the input pin/TD of piece U9 is coupled to the output pin SDO for weighing timing chip U9, institute after being coupled with resistance R41
It states after input pin TD is coupled with resistance R48 and is coupled to input pin/TD, the input pin TD is coupled to power supply after being coupled with resistance R3
VCC33T is grounded after being coupled with resistance R8, and the input pin TD is coupled to power supply VCC33T after being coupled with resistance R4, is coupled with electricity
It is grounded after resistance R29, the supply pin VCCTX is grounded after being coupled with capacitor C1, and the supply pin VCCTX is coupled with coupling after inductance L3
It is grounded after being connected to capacitor C12, the tie point of the inductance L3 and capacitor C12 are coupled to power supply VCC+3.3V, the supply pin
VCCRX is grounded after being coupled with capacitor C2, the supply pin VCCRX is coupled with after inductance L4 be coupled with capacitor C13 after be grounded, it is described
The tie point of inductance L4 and capacitor C13 is coupled to power supply VCC+3.3V, after the power supply VCC+3.3V is coupled with electrolytic capacitor EC3
Ground connection, the output pin SD are exported after being coupled with amplifying circuit.
4. HD-SDI multi-service HD video optical transmitter and receiver according to claim 3, it is characterised in that：The conversion circuit
(34) include conversion chip U4, the positive and negative anodes input pin of the conversion chip U4 respectively with the input pin TD of driving chip M1 and
Input pin/TD connection, the positive and negative anodes output pin of the conversion chip U4 mutually interconnect after being respectively coupled to resistance R14 and resistance R15
It is grounded after being coupled with capacitor C14 after connecing, the positive output pin of the conversion chip U4 is coupled with inductance L5 and electricity parallel with one another
It is exported after being coupled with capacitor C15 after resistance R16.
5. HD-SDI multi-service HD video optical transmitter and receiver according to claim 4, it is characterised in that：The conversion chip U4
Positive and negative anodes input pin and driving chip M1 input pin TD and input pin/TD between be in series with capacitor C17 and capacitor respectively
C16, the positive and negative anodes input pin of the conversion chip U4 have been respectively coupled to be coupled with after being connected with each other after resistance R37 and resistance R38
It is grounded after capacitor C36.
6. according to claim 1 to HD-SDI multi-service HD video optical transmitter and receiver described in 5 any one, it is characterised in that：Institute
Stating power circuit (1) includes voltage stabilizing chip U7, and the input pin of the voltage stabilizing chip U7 is coupled to power supply after being coupled with switch 3F1
+ 24V, the enabled foot of the voltage stabilizing chip U7 are coupled to input pin, the switch 3F1 and power supply+24V after being coupled with resistance 3R23
Tie point be coupled with diode 3DV1 after be grounded, the input pin of the voltage stabilizing chip U7 is coupled with electrolytic capacitor 3EC1 and is followed by
Ground, the output pin of the voltage stabilizing chip U7 are coupled with out-put supply VCC5 after inductance L6, and the power supply VCC5 is coupled with mutually simultaneously
It is grounded after the capacitor 3C15 and electrolytic capacitor 3EC2 of connection, the bootstrapping foot of the voltage stabilizing chip U7 is coupled to after being coupled with capacitor 3C14
Output pin, output pin are grounded after being coupled with diode 3ZD3, and the tie point of the inductance L6 and electrolytic capacitor 3EC2 are coupled with electricity
It is grounded after being coupled with resistance 3R18 after resistance 3R19, the resistance 3R19 is parallel with capacitor 3C11, the feedback of the voltage stabilizing chip U7
Foot is coupled to the tie point of resistance 3R19 Yu resistance 3R18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820624324.6U CN208158591U (en) | 2018-04-27 | 2018-04-27 | A kind of HD-SDI multi-service HD video optical transmitter and receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820624324.6U CN208158591U (en) | 2018-04-27 | 2018-04-27 | A kind of HD-SDI multi-service HD video optical transmitter and receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208158591U true CN208158591U (en) | 2018-11-27 |
Family
ID=64377033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820624324.6U Withdrawn - After Issue CN208158591U (en) | 2018-04-27 | 2018-04-27 | A kind of HD-SDI multi-service HD video optical transmitter and receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208158591U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108390723A (en) * | 2018-04-27 | 2018-08-10 | 浙江恒捷通信科技有限公司 | A kind of HD-SDI multi-services HD video optical transmitter and receiver |
-
2018
- 2018-04-27 CN CN201820624324.6U patent/CN208158591U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108390723A (en) * | 2018-04-27 | 2018-08-10 | 浙江恒捷通信科技有限公司 | A kind of HD-SDI multi-services HD video optical transmitter and receiver |
| CN108390723B (en) * | 2018-04-27 | 2023-11-14 | 浙江恒捷通信科技有限公司 | HD-SDI multi-service high-definition video optical transmitter and receiver |
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