CN108390723B - HD-SDI multi-service high-definition video optical transmitter and receiver - Google Patents
HD-SDI multi-service high-definition video optical transmitter and receiver Download PDFInfo
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- CN108390723B CN108390723B CN201810391861.5A CN201810391861A CN108390723B CN 108390723 B CN108390723 B CN 108390723B CN 201810391861 A CN201810391861 A CN 201810391861A CN 108390723 B CN108390723 B CN 108390723B
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- 230000003287 optical effect Effects 0.000 title claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims description 80
- 238000006243 chemical reaction Methods 0.000 claims description 32
- 230000000087 stabilizing effect Effects 0.000 claims description 29
- 230000003044 adaptive effect Effects 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000001914 filtration Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
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Abstract
The invention discloses an HD-SDI multi-service high-definition video optical transceiver. The invention has the advantages that: the clock retiming circuit detects whether the clock signal in the signal is abnormal or not, resets the abnormal signal, avoids the situation that the clock cannot be recovered after power failure and the like, and improves the stability of the signal in the later-stage circuit even if the clock cannot be recovered to cause data transmission errors.
Description
Technical Field
The invention relates to the field of signal transmission equipment, in particular to an HD-SDI multi-service high-definition video optical transceiver.
Background
The HD-SDI optical transceiver is a device that converts an SDI signal and an optical signal to each other. The principle of the SDI optical terminal is that a transmitting end modulates an SDI signal through a laser to be changed into an optical signal, and a receiving end recodes data received by a laser diode into the SDI signal.
In the use process of the existing HD-SDI optical terminal, the clock cannot be recovered after the conditions such as power failure and the like, and the clock cannot be recovered to cause data transmission errors and even the condition that the data cannot be transmitted.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide an HD-SDI multi-service high-definition video optical transceiver with a clock retiming function.
In order to achieve the above purpose, the present invention provides the following technical solutions: an HD-SDI multi-service high definition video optical transmitter and receiver, comprising: the power supply circuit is connected with the main control circuit, supplies power to the main control circuit, the transmission circuit is connected with the main control circuit and an external interface, receives and transmits signals, the transmission circuit comprises an equalization circuit, a clock retiming circuit, a driving circuit and a conversion circuit, the equalization circuit is connected with the main control circuit and the clock retiming circuit, the clock retiming circuit is respectively connected with the driving circuit and the conversion circuit, the driving circuit is connected with the conversion circuit, the conversion circuit is connected with the external interface, the clock retiming circuit comprises a retiming chip U9 and a peripheral circuit thereof, and the retiming chip U9 is connected with the equalization circuit, the driving circuit and the conversion circuit and outputs signals output by the equalization circuit after receiving the signals.
As a further improvement of the present invention, the equalization circuit includes an adaptive chip U5, where the adaptive chip U5 has an input pin SDI, an input pin/SDI, an output pin SDO and an output pin/SDO, where the input pin SDI is coupled with a capacitor C4 and then coupled with a resistor R5 and then grounded, a connection point of the capacitor C4 and the resistor R5 is coupled with an inductance L1 and a resistor R6 that are parallel to each other and then coupled to the main control circuit, the input pin/SDI is coupled with a capacitor C10 and then coupled with a resistor R12 and then grounded, the output pin SDO is coupled with a resistor R29 and then coupled with the input pin/SDI of the retimer chip U9, and the output pin/SDO is coupled with the input pin/SDI of the retimer chip U9.
As a further development of the invention, the drive circuit comprises a drive chip M1, the drive chip M1 having an input pin TD, an input pin/TD, an output pin SD, an output pin RD, an output pin/RD, a power supply pin VCCTX and a power supply pin VCCRX, the input pin TD being coupled with a resistor R40 and then with an output pin SDO of a retimer chip U9, the input pin/TD being coupled with a resistor R41 and then with an output pin SDO of a retimer chip U9, the input pin TD being coupled with a resistor R48 and then with an input pin/TD, the input pin TD being coupled with a resistor R3 and then with a power supply VCC 33T, the input pin TD being coupled with a resistor R8 and then with a ground, the input pin/TD is coupled to the resistor R4 and then to the power VCC33_t, the resistor R9 and then to the ground, the power pin VCCTX is coupled to the capacitor C1 and then to the ground, the power pin VCCTX is coupled to the inductor L3 and then to the capacitor C12 and then to the ground, the connection point between the inductor L3 and the capacitor C12 is coupled to the power vcc+3.3v, the power pin VCCRX is coupled to the capacitor C2 and then to the ground, the power pin VCCRX is coupled to the inductor L4 and then to the capacitor C13 and then to the ground, the connection point between the inductor L4 and the capacitor C13 is coupled to the power vcc+3.3v, the power vcc+3.3v is coupled to the electrolytic capacitor EC3 and then to the ground, and the output pin SD is coupled to the amplifying circuit and then to the output.
As a further improvement of the invention, the conversion circuit comprises a conversion chip U4, wherein positive and negative input pins of the conversion chip U4 are respectively connected with an input pin TD and an input pin/TD of the driving chip M1, positive and negative output pins of the conversion chip U4 are respectively coupled with a resistor R14 and a resistor R15, then are mutually connected and are coupled with a capacitor C14 and then are grounded, and positive output pins of the conversion chip U4 are coupled with an inductor L5 and a resistor R16 which are mutually connected in parallel and then are coupled with a capacitor C15 and then are output.
As a further improvement of the present invention, a capacitor C17 and a capacitor C16 are respectively connected in series between the positive and negative input pins of the conversion chip U4 and the input pins TD and input pins/TD of the driving chip M1, and the positive and negative input pins of the conversion chip U4 are respectively coupled with a resistor R37 and a resistor R38, and then are connected with each other and then are coupled with a capacitor C36, and then are grounded.
As a further improvement of the present invention, the power supply circuit includes a voltage stabilizing chip U7, an input pin of the voltage stabilizing chip U7 is coupled with a switch 3F1 and then coupled to a power supply +24v, an enable pin of the voltage stabilizing chip U7 is coupled with a resistor 3R23 and then coupled to an input pin, a connection point of the switch 3F1 and the power supply +24v is coupled with a diode 3DV1 and then grounded, an input pin of the voltage stabilizing chip U7 is coupled with an electrolytic capacitor 3EC1 and then grounded, an output pin of the voltage stabilizing chip U7 is coupled with an inductor L6 and then an output power supply VCC5, the power supply VCC5 is coupled with a capacitor 3C15 and an electrolytic capacitor 3EC2 which are connected in parallel, a bootstrap pin of the voltage stabilizing chip U7 is coupled with a capacitor 3C14 and then coupled to an output pin, an output pin is coupled with a diode 3ZD3 and then grounded, a connection point of the inductor L6 and the electrolytic capacitor 3EC2 is coupled with a resistor 3R19 and then grounded, an output pin is coupled with a resistor 3R18, an output pin of the inductor L6 and then connected with the resistor 3C 2 and then grounded, and a connection point of the resistor 3C 19 is coupled with the resistor 3C 3R 11.
The clock retiming circuit has the beneficial effects that the clock retiming circuit detects whether the clock signal in the signal is abnormal or not, resets the abnormal signal, avoids the condition that the clock cannot be recovered after the power failure and the like occur, and improves the stability of the signal in the later-stage circuit even if the clock cannot be recovered to cause data transmission errors.
Drawings
FIG. 1 is a flow chart of the present invention;
fig. 2 is a circuit diagram of the equalization circuit of fig. 1;
FIG. 3 is a circuit diagram of the clock retiming circuit of FIG. 1;
FIG. 4 is a circuit diagram of the conversion circuit of FIG. 1;
FIG. 5 is a circuit diagram of the driving circuit of FIG. 1;
fig. 6 is a circuit diagram of the power supply circuit of fig. 1.
Description of the drawings: 1. a power supply circuit; 2. a main control circuit; 3. a transmission circuit; 31. an equalizing circuit; 32. a clock retiming circuit; 33. a driving circuit; 34. and a conversion circuit.
Detailed Description
The invention will be further described in detail with reference to examples of embodiments shown in the drawings.
Referring to fig. 1, 2, 3, 4, 5 and 6, an HD-SDI multi-service high definition video optical transceiver of the present embodiment includes: the power supply circuit 1, the main control circuit 2 and the transmission circuit 3, the power supply circuit 1 is connected with the main control circuit 2 to supply power to the main control circuit 2, the transmission circuit 3 is connected with the main control circuit 2 and an external interface to receive and send signals, the transmission circuit 3 comprises an equalizing circuit 31, a clock retiming circuit 32, a driving circuit 33 and a converting circuit 34, the equalizing circuit 31 is connected with the main control circuit 2 and the clock retiming circuit 32, the clock retiming circuit 32 is respectively connected with the driving circuit 33 and the converting circuit 34, the driving circuit 33 is connected with the converting circuit 34, the converting circuit 34 is connected with an external interface, the clock retiming circuit 32 comprises a retiming chip U9 and a peripheral circuit thereof, and the retiming chip U9 is connected with the equalizing circuit 31, the driving circuit 33 and the converting circuit 34 to receive signals output by the equalizing circuit 31 and output the signals.
Through the technical scheme, the power supply circuit 1 supplies power to the main control circuit 2 to work, external signals enter from an external interface, the external signals firstly pass through the equalizing circuit 31, the equalizing circuit 31 promotes and compensates attenuation signals in a corresponding frequency range, so that final output and input tend to be the same, then the signals enter the clock retiming circuit 32, the retiming chip U9 receives clock signals in signal detection signals and outputs the clock signals, and when the clock signals in the signals are not abnormal, the retiming chip U9 receives and outputs the signals; when the clock signal in the signal is abnormal, the retiming chip U9 receives the signal and then resets the clock for the signal and then outputs the signal, the crystal oscillator 7X1 connected with the retiming chip U9 provides a stable clock signal for the retiming chip U9, then the signal enters the driving circuit 33 and the converting circuit 34, the driving circuit 33 receives the signal and outputs the signal, the converting circuit 34 receives the signal and then converts the signal and outputs the signal, the clock retiming circuit 32 detects whether the clock signal in the signal is abnormal or not and resets the abnormal signal, the situation that the clock cannot be recovered after the power failure and the like occur is avoided, the clock cannot be recovered to cause data transmission to be wrong, even the situation that the data cannot be transmitted is avoided, and the stability of the signal in a later-stage circuit is improved.
As a modified embodiment, the equalizing circuit 31 includes an adaptive chip U5, where the adaptive chip U5 has an input pin SDI, an input pin/SDI, an output pin SDO, and an output pin/SDO, where the input pin SDI is coupled with a capacitor C4 and then coupled with a resistor R5 and then grounded, a connection point between the capacitor C4 and the resistor R5 is coupled with an inductor L1 and a resistor R6 that are parallel to each other and then coupled to the main control circuit 2, the input pin/SDI is coupled with a capacitor C10 and then coupled with a resistor R12 and then grounded, the output pin SDO is coupled to the input pin SDI of the retiming chip U9, the output pin SDO is coupled with a resistor R29 and then coupled to the input pin/SDI of the retiming chip U9, and the output pin/SDO is coupled to the input pin/SDI of the retiming chip U9.
Through the technical scheme, the self-adaptive chip U5 can be LMH0344, signals are input to the self-adaptive chip U5 after passing through the capacitor C4 after passing through the inductor L1 and the resistor R6, the self-adaptive chip U5 processes the input signals, the signals are output after being lifted and compensated in the corresponding frequency range, the signals are screened by the inductor L1 and the resistor R6, the inductor L1 and the resistor R6 are jointly left and right, the electromagnetic wave interference is always carried out, the effect of stabilizing current is further improved, the resistor R29 is arranged between data lines, the stability of data transmission is improved, the input pin/SDI is enabled to be more stable after being coupled with the resistor R12 after being coupled with the capacitor C10, and the surge appearing by the resistor R5 is enabled to enter the ground after passing through the small resistor, so that the stability of a circuit is further improved.
In an improved embodiment, the driving circuit 33 includes a driving chip M1, where the driving chip M1 has an input pin TD, an input pin/TD, an output pin SD, an output pin RD, an output pin/RD, a power pin VCCTX, and a power pin VCCRX, where the input pin TD is coupled with a resistor R40 and then coupled with an output pin SDO of the retiming chip U9, the input pin/TD is coupled with a resistor R41 and then coupled with an output pin SDO of the retiming chip U9, the input pin TD is coupled with a resistor R48 and then coupled with an input pin/TD, the input pin TD is coupled with a resistor R3 and then coupled with a power supply VCC33_t, the input pin/TD is coupled with a resistor R8 and then coupled with a power supply 33_t, the power pin VCCTX is coupled with a capacitor C1 and then coupled with a ground, the power pin VCCTX 3 is coupled with an inductor L12 and then coupled with a capacitor C3 and then coupled with a capacitor V3, and then coupled with a capacitor V3 and a capacitor V3, and a capacitor 3 are coupled with a capacitor and a capacitor 3.
Through above-mentioned technical scheme, driving chip M1 adopts dual supply power, receives and exports and all adopts independent power supply, is to receive and export mutually noninterfere to inductance L3 and electric capacity C1, electrolytic capacitor EC3 and electric capacity C12 carry out the wave filtering to the power of receiving, and inductance L4 and electric capacity C2, electrolytic capacitor EC3 and electric capacity C13 carry out the wave filtering to the power of output, use an electrolytic capacitor EC3, under the condition that does not reduce the filter effect, reduced components and parts use, reduced the cost, reduce the PCB board.
As an improved specific embodiment, the conversion circuit 34 includes a conversion chip U4, positive and negative input pins of the conversion chip U4 are respectively connected with the input pin TD and the input pin/TD of the driving chip M1, positive and negative output pins of the conversion chip U4 are respectively coupled with the resistor R14 and the resistor R15, and then are mutually connected and then are coupled with the capacitor C14 and then are grounded, and positive output pins of the conversion chip U4 are coupled with the inductor L5 and the resistor R16 which are mutually connected in parallel and then are coupled with the capacitor C15 and then are output.
Through the above technical scheme, the conversion chip U4 may be GV8500, and the conversion chip U4 receives signals and converts the signals after conversion, and outputs the converted signals, the resistor R14, the capacitor C14, the resistor R15 and the capacitor C14 all form an LC filter circuit, so as to improve stability of output signals, and the inductor L5 and the resistor R16 are connected in parallel and then connected in series with the capacitor C15, so that electromagnetic interference between the post-stage circuit and the conversion circuit 34 is reduced while filtering the output signals, and stability of the output signals is improved.
As an improved specific embodiment, a capacitor C17 and a capacitor C16 are respectively connected in series between the positive and negative input pins of the conversion chip U4 and the input pins TD and input pins/TD of the driving chip M1, and the positive and negative input pins of the conversion chip U4 are respectively coupled with a resistor R37 and a resistor R38, then are mutually connected and then are coupled with a capacitor C36, and finally are grounded.
Through the technical scheme, the capacitor C16 and the capacitor C17 are used for filtering signals, so that the stability of signal transmission is improved, the resistor R37, the capacitor C36, the resistor R38 and the capacitor C36 form an LC filter circuit, the stability of signal transmission between circuits is further improved, meanwhile, the resistor R37 and the resistor R38 share the capacitor C36, the use of components is further reduced under the condition that the filtering effect is not reduced, the cost is reduced, and the PCB is reduced.
As an improved embodiment, the power circuit 1 includes a voltage stabilizing chip U7, an input pin of the voltage stabilizing chip U7 is coupled with a switch 3F1 and then coupled to a power source +24v, an enable pin of the voltage stabilizing chip U7 is coupled with a resistor 3R23 and then coupled to an input pin, a connection point of the switch 3F1 and the power source +24v is coupled with a diode 3DV1 and then grounded, an input pin of the voltage stabilizing chip U7 is coupled with an electrolytic capacitor 3EC1 and then grounded, an output pin of the voltage stabilizing chip U7 is coupled with an inductor L6 and then outputs a power VCC5, the power VCC5 is coupled with a capacitor 3C15 and an electrolytic capacitor 3EC2 which are connected in parallel, a bootstrap pin of the voltage stabilizing chip U7 is coupled with a capacitor 3C14 and then coupled to an output pin, an output pin is coupled with a diode 3ZD3 and then grounded, a connection point of the inductor L6 and the electrolytic capacitor 3EC2 is coupled with a resistor 3R19 and then grounded, and then the capacitor 3C 19 is coupled with a resistor 3C11 and then connected to the resistor 3R 11.
Through the technical scheme, the voltage stabilizing chip U7 can be MP2494DS, the power supply is input to the input pin, the diode 3DV1 is a transient suppression diode, the surge arranged in the circuit is avoided from damaging the voltage stabilizing chip U7 at the input port of the voltage stabilizing chip U7, the electrolytic capacitor 3EC1 and the diode 3DV1 form a loop, the stability of the power supply input to the voltage stabilizing chip U7 is improved, the electrolytic capacitor 3EC1 discharges when the power is cut off, the resistor 3R23 is used for limiting current, the enabling pin is protected, the stability of the voltage stabilizing chip U7 is further improved, the voltage stabilizing chip U7 outputs a stabilized power supply signal, the capacitor 3C14 is connected with the output pin and the bootstrap pin to enable the voltage stabilizing chip U7 to bootstrap, the stability of the operation of the voltage stabilizing chip U7 is improved, then the voltage stabilizing chip U7 is output to the inductor L6, the power supply signal which is stably output by the inductor L6 is arranged, the resistor 3R19 and the resistor 3R18 divide the output signal, the feedback pin is connected with the acquisition signal, the output signal is further adjusted, the output signal is more stable, the feedback pin receives the signal after the voltage dividing, the surge is prevented from impacting the feedback pin, the stability of the work of the chip U7 is improved, the stability of the work is improved, the capacitor 3C11 is stable, and the output is stable when the surge voltage is suddenly and the output is stable when the surge voltage is changed when the load fluctuation is generated, or the surge voltage is suddenly changes, and the surge voltage is output and reaches the surge load output when the surge voltage is stable. The dynamic response process of the power supply is quickened, the output fluctuation range is reduced when the input voltage is suddenly changed or the load is suddenly changed, the overshoot phenomenon is avoided, the stability is improved, the capacitor C15 and the electrolytic capacitor 3EC2 which are mutually connected in parallel are arranged on the output power supply VCC5, the output stability is improved, meanwhile, parasitic coupling between a rear-stage circuit and the power supply circuit 1 is avoided, and the working stability of the HD-SDI multi-service high-definition video optical transmitter is improved.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (4)
1. An HD-SDI multi-service high definition video optical transmitter and receiver, comprising: the power supply circuit (1), main control circuit (2) and transmission circuit (3), power supply circuit (1) are connected with main control circuit (2), supply power for main control circuit (2), main control circuit (2) and external interface are connected to transmission circuit (3), receive and send signal, its characterized in that:
the transmission circuit (3) comprises an equalizing circuit (31), a clock re-timing circuit (32), a driving circuit (33) and a converting circuit (34), wherein the equalizing circuit (31) is connected with the main control circuit (2) and the clock re-timing circuit (32), the clock re-timing circuit (32) is respectively connected with the driving circuit (33) and the converting circuit (34), the driving circuit (33) is connected with the converting circuit (34), the converting circuit (34) is connected with an external interface, the clock re-timing circuit (32) comprises a re-timing chip U9 and a peripheral circuit thereof, and the re-timing chip U9 is connected with the equalizing circuit (31), the driving circuit (33) and the converting circuit (34) to receive signals output by the equalizing circuit (31) and output the signals;
the equalization circuit (31) comprises an adaptive chip U5, wherein the adaptive chip U5 is provided with an input pin SDI, an input pin/SDI, an output pin SDO and an output pin/SDO, the input pin SDI is coupled with a capacitor C4 and then is coupled with a resistor R5 and then is grounded, a connection point of the capacitor C4 and the resistor R5 is coupled with an inductor L1 and a resistor R6 which are mutually connected in parallel and then is coupled to a main control circuit (2), the input pin/SDI is coupled with a capacitor C10 and then is coupled with a resistor R12 and then is grounded, the output pin SDO is coupled with the input pin SDI of the retiming chip U9, the output pin SDO is coupled with a resistor R29 and then is coupled with the input pin/SDI of the retiming chip U9, and the output pin/SDO is coupled with the input pin/SDI of the retiming chip U9;
the driving circuit (33) comprises a driving chip M1, wherein the driving chip M1 comprises an input pin TD, an input pin/TD, an output pin SD, an output pin RD, an output pin/RD, a power pin VCCTX and a power pin VCCRX, the input pin TD is coupled with a resistor R40 and then is coupled with an output pin SDO of a retiming chip U9, the input pin/TD is coupled with a resistor R41 and then is coupled with an output pin SDO of the retiming chip U9, the input pin TD is coupled with a resistor R48 and then is coupled with an input pin/TD, the input pin TD is coupled with a resistor R3 and then is coupled with a power source VCC33_T, is coupled with a resistor R8 and then is coupled with a resistor R4 and then is coupled with a power source VCC33_T, the power supply pin VCCTX is coupled with a capacitor C1 and then grounded, the power supply pin VCCTX is coupled with an inductor L3 and then grounded, a connection point of the inductor L3 and the capacitor C12 is coupled with a power supply VCC+3.3V, the power supply pin VCCRX is coupled with a capacitor C2 and then grounded, the power supply pin VCCRX is coupled with an inductor L4 and then grounded, a connection point of the inductor L4 and the capacitor C13 is coupled with a power supply VCC+3.3V, the power supply VCC+3.3V is coupled with an electrolytic capacitor EC3 and then grounded, and the output pin SD is coupled with an amplifying circuit and then output.
2. The HD-SDI multi-service high definition video optical transmitter and receiver of claim 1 wherein:
the conversion circuit (34) comprises a conversion chip U4, positive and negative input pins of the conversion chip U4 are respectively connected with an input pin TD and an input pin/TD of the driving chip M1, positive and negative output pins of the conversion chip U4 are respectively coupled with a resistor R14 and a resistor R15, are mutually connected and then are coupled with a capacitor C14 and then are grounded, and positive output pins of the conversion chip U4 are coupled with an inductor L5 and a resistor R16 which are mutually connected in parallel and then are coupled with a capacitor C15 and then are output.
3. The HD-SDI multi-service high definition video optical transmitter and receiver of claim 2 wherein:
a capacitor C17 and a capacitor C16 are respectively connected in series between the positive and negative input pins of the conversion chip U4 and the input pins TD and input pins/TD of the driving chip M1, and the positive and negative input pins of the conversion chip U4 are respectively coupled with a resistor R37 and a resistor R38, then are mutually connected and then are coupled with a capacitor C36, and finally are grounded.
4. The HD-SDI multi-service high definition video optical transmitter and receiver of any one of claims 1 to 3, wherein:
the power circuit (1) comprises a voltage stabilizing chip U7, an input pin of the voltage stabilizing chip U7 is coupled with a switch 3F1 and then is coupled to a power supply +24V, an enabling pin of the voltage stabilizing chip U7 is coupled with a resistor 3R23 and then is coupled to an input pin, a connection point of the switch 3F1 and the power supply +24V is coupled with a diode 3DV1 and then is grounded, an input pin of the voltage stabilizing chip U7 is coupled with an electrolytic capacitor 3EC1 and then is grounded, an output pin of the voltage stabilizing chip U7 is coupled with an inductor L6 and then is grounded, the power supply VCC5 is coupled with a capacitor 3C15 and an electrolytic capacitor 3EC2 which are connected in parallel, a bootstrap pin of the voltage stabilizing chip U7 is coupled with a capacitor 3C14 and then is coupled to an output pin, an output pin is coupled with a diode 3ZD3 and then is grounded, a connection point of the inductor L6 and the electrolytic capacitor 3EC2 is coupled with a resistor 3R18 and then is grounded, and a connection point of the resistor 3R19 and the capacitor 3C11 and the voltage stabilizing chip 3C 2 are coupled with a resistor 19 and then is grounded.
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| CN201810391861.5A CN108390723B (en) | 2018-04-27 | 2018-04-27 | HD-SDI multi-service high-definition video optical transmitter and receiver |
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| CN201810391861.5A CN108390723B (en) | 2018-04-27 | 2018-04-27 | HD-SDI multi-service high-definition video optical transmitter and receiver |
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| CN108390723B true CN108390723B (en) | 2023-11-14 |
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| CN108390723A (en) | 2018-08-10 |
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