CN108390723A - A kind of HD-SDI multi-services HD video optical transmitter and receiver - Google Patents
A kind of HD-SDI multi-services HD video optical transmitter and receiver Download PDFInfo
- Publication number
- CN108390723A CN108390723A CN201810391861.5A CN201810391861A CN108390723A CN 108390723 A CN108390723 A CN 108390723A CN 201810391861 A CN201810391861 A CN 201810391861A CN 108390723 A CN108390723 A CN 108390723A
- Authority
- CN
- China
- Prior art keywords
- coupled
- circuit
- resistance
- chip
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims abstract description 16
- 238000006243 chemical reaction Methods 0.000 claims description 43
- 230000000087 stabilizing effect Effects 0.000 claims description 28
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000005611 electricity Effects 0.000 claims description 16
- 230000003044 adaptive effect Effects 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000005303 weighing Methods 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 230000006872 improvement Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000010349 pulsation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Computer Networks & Wireless Communication (AREA)
- Multimedia (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of HD SDI multi-services HD video optical transmitter and receivers.Advantages of the present invention：Whether re-clocking circuit detects the clock signal in signal abnormal, and abnormal signal is reset, the case where clock can not restore after situations such as avoiding the occurrence of power-off, clock can not restore that data transmission is made mistake occur, the case where can not even transmitting, improves stability of the signal in late-class circuit.
Description
Technical field
The present invention relates to signal transmission apparatus field, more particularly to a kind of HD-SDI multi-services HD video light
Terminal.
Background technology
HD-SDI optical transmitter and receivers are the equipment for converting sdi signal and optical signal mutually.The principle of SDI optical transmitter and receivers is transmitting terminal
By sdi signal by becoming optical signal after laser modulation, the data re-encoding that receiving terminal receives laser diode is that SDI believes
Number.
During existing HD-SDI optical transmitter and receivers use, the case where clock can not restore after situations such as powering off, clock
The case where can not restoring that data transmission is made mistake occur, or even can not transmitting.
Invention content
In view of the deficiencies of the prior art, the present invention intends to provide a kind of HD- with clock weight timing function
SDI multi-service HD video optical transmitter and receivers.
To achieve the above object, the present invention provides following technical solutions：A kind of HD-SDI multi-services HD video light end
Machine includes：Power circuit, governor circuit and transmission circuit, the power circuit are connect with governor circuit, are supplied to governor circuit
Electricity, the transmission circuit connection governor circuit and external interface, receive and send signal, and the transmission circuit includes balanced electricity
Road, re-clocking circuit, driving circuit and conversion circuit, electricity when the equalizing circuit connection governor circuit and clock are reset
Road, the re-clocking circuit are connect with driving circuit and conversion circuit respectively, and the driving circuit is connect with conversion circuit,
The conversion circuit is connect with external interface, and the re-clocking circuit includes to weigh timing chip U9 and its peripheral circuit,
The heavy timing chip U9 connections equalizing circuit, driving circuit and conversion circuit, receiver equalization circuitry output signal after export.
As a further improvement on the present invention, the equalizing circuit includes adaptive chip U5, the adaptive chip
U5 has input pin SDI, input pin/SDI, output pin SDO and output pin/SDO, after the input ports SDI are coupled with capacitance C4
It is grounded after being coupled with resistance R5, after the tie point of the capacitance C4 and resistance R5 is coupled with inductance L1 parallel with one another and resistance R6
Be coupled to governor circuit, the input pin/SDI is coupled with after capacitance C10 be coupled with resistance R12 after be grounded, the output pin SDO
The input pin SDI, the output pin SDO for being coupled to weight timing chip U9 are coupled to weight timing chip U9 after being coupled with resistance R29
Input pin/SDI, the output pin/SDO is coupled to input pin/SDI of weight timing chip U9.
As a further improvement on the present invention, the driving circuit includes driving chip M1, the driving chip M1 tools
There are input pin TD, input pin/TD, output pin SD, output pin RD, output pin/RD, supply pin VCCTX and supply pin VCCRX, institute
It states input pin TD and is coupled with and be coupled to the output pin SDO, the input pin/TD of weight timing chip U9 after resistance R40 and be coupled with electricity
Be coupled to the output pin SDO of weight timing chip U9 after resistance R41, the input pin TD be coupled with after resistance R48 be coupled to input pin/
TD, the input pin TD are coupled to power supply VCC33_T after being coupled with resistance R3, are grounded after being coupled with resistance R8, the output pin
TD is coupled to power supply VCC33_T after being coupled with resistance R4, is grounded after being coupled with resistance R29, and the supply pin VCCTX is coupled with electricity
Be grounded after holding C1, the supply pin VCCTX is coupled with after inductance L3 be coupled with capacitance C12 after be grounded, the inductance L3 and capacitance
The tie point of C12 is coupled to power supply VCC+3.3V, and the supply pin VCCRX is grounded after being coupled with capacitance C2, the supply pin RX
It is coupled with after inductance L4 after being coupled with capacitance C13 and is grounded, the tie point of the inductance L4 and capacitance C13 is coupled to power supply VCC+
3.3V, the power supply VCC+3.3V are grounded after being coupled with electrolytic capacitor EC3, and the output pin SD is coupled with defeated after amplifying circuit
Go out.
As a further improvement on the present invention, the conversion circuit includes conversion chip U4, the conversion chip U4's
Positive and negative anodes input pin is connect with the input pin TD of driving chip M1 and input pin/TD respectively, the positive and negative anodes of the conversion chip U4
Output pin has been respectively coupled to be grounded after being coupled with capacitance C14 after being connected with each other after resistance R14 and resistance R15, the conversion chip
The positive output pin of U4 is coupled with after inductance L5 parallel with one another and resistance R16 be coupled with capacitance C15 after export.
As a further improvement on the present invention, the input of the positive and negative anodes input pin and driving chip M1 of the conversion chip U4
The positive and negative anodes input pin point of capacitance C17 and capacitance C16, the conversion chip U4 are in series between foot TD and input pin/TD respectively
It is not coupled with after being coupled with capacitance C36 after being connected with each other after resistance R37 and resistance R38 and is grounded.
As a further improvement on the present invention, the power circuit includes voltage stabilizing chip U7, the voltage stabilizing chip U7's
Input pin is coupled to power supply+24V after being coupled with switch 3F1, and the enabled foot of the voltage stabilizing chip U7 is coupled with coupling after resistance 3R23
It is connected to input pin, the tie point of the switch 3F1 and power supply+24V is grounded after being coupled with diode 3DV1, the voltage stabilizing chip U7
Input pin be coupled with electrolytic capacitor 3EC1 after be grounded, the output pin of the power supply chip U7 is coupled with out-put supply after inductance L6
VCC5, the power supply VCC5 are grounded after being coupled with capacitance 3C15 parallel with one another and electrolytic capacitor 3EC2, the voltage stabilizing chip U7
Bootstrapping foot be coupled with capacitance 3C14 after be coupled to output pin, output pin is grounded after being coupled with diode 3ZD3, the inductance L6
It is coupled with after being coupled with resistance 3R18 after resistance 3R19 and is grounded with the tie point of electrolytic capacitor 3EC2, the resistance 3R19 is parallel with
The feedback foot of capacitance 3C11, the voltage stabilizing chip U7 are coupled to the tie point of resistance 3R19 and resistance 3R18.
Whether extremely beneficial effects of the present invention, re-clocking circuit detect the clock signal in signal, and will be different
The case where clock can not restore after situations such as normal signal is reset, avoids the occurrence of power-off, clock can not restore to make number
The case where mistake occur according to transmission, or even can not transmitting improves stability of the signal in late-class circuit.
Description of the drawings
Fig. 1 is the flow diagram of the present invention；
Fig. 2 is the circuit diagram of equalizing circuit in Fig. 1；
Fig. 3 is the circuit diagram of re-clocking circuit in Fig. 1；
Fig. 4 is the circuit diagram of conversion circuit in Fig. 1；
Fig. 5 is the circuit diagram of driving circuit in Fig. 1；
Fig. 6 is the circuit diagram of power circuit in Fig. 1.
Description of the drawings：1, power circuit；2, governor circuit；3, transmission circuit；31, equalizing circuit；32, it is electric when clock is reset
Road；33, driving circuit；34, conversion circuit.
Specific implementation mode
The present invention is described in further detail below in conjunction with the embodiment given by attached drawing.
Referring to Fig.1, shown in Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6, a kind of HD-SDI multi-services HD video light of the present embodiment
Terminal includes：Power circuit 1, governor circuit 2 and transmission circuit 3, the power circuit 1 are connect with governor circuit 2, to master
It controls circuit 2 to power, the transmission circuit 3 connects governor circuit 2 and external interface, receives and send signal, the transmission circuit 3
Include equalizing circuit 31, re-clocking circuit 32, driving circuit 33 and conversion circuit 34, the connection master of the equalizing circuit 31
Circuit 2 and re-clocking circuit 32 are controlled, the re-clocking circuit 32 connects with driving circuit 33 and conversion circuit 34 respectively
It connects, the driving circuit 33 is connect with conversion circuit 34, and the conversion circuit 34 is connect with external interface, when the clock is reset
Circuit 32 includes weight timing chip U9 and its peripheral circuit, the heavy timing chip U9 connections equalizing circuit 31, driving circuit
33 and conversion circuit 34, it exports after the signal that receiver equalization circuitry 31 exports.
Through the above technical solutions, power circuit 1 works to the power supply of governor circuit 2, external signal is from external interface
Into, equalizing circuit 31 is first passed through, equalizing circuit 31 is promoted and is compensated to deamplification in corresponding frequency range, from
And last output and input is made to tend to be identical, signal enters re-clocking circuit 32 later, and weight timing chip U9 receives letter
It after clock signal in number detection signal and exports, when the clock signal in signal is without exception, weight timing chip U9 receives letter
Number and export；When the clock signal exception in signal, after resetting clock to signal after weight timing chip U9 reception signals
The crystal oscillator 7X1 of output, weight timing chip U9 connections gives weight timing chip U9 to provide stable clock signal, and signal enters drive later
Dynamic circuit 33 and conversion circuit 34, driving circuit 33 export after receiving signal, and conversion circuit 34 carries out signal after receiving signal
It is exported after conversion, whether the clock signal in the detection signal of re-clocking circuit 32 is abnormal, and abnormal signal is carried out
The case where clock can not restore after situations such as resetting, avoiding the occurrence of power-off, clock can not restore that data transmission is made mistake occur
Accidentally, the case where or even can not transmitting, improves stability of the signal in late-class circuit.
As a kind of improved specific implementation mode, the equalizing circuit 31 includes adaptive chip U5, described adaptive
Answer chip U5 that there is input pin SDI, input pin/SDI, output pin SDO and output pin/SDO, the input ports SDI are coupled with electricity
It is grounded after being coupled with resistance R5 after appearance C4, the tie point of the capacitance C4 and resistance R5 is coupled with inductance L1 and electricity parallel with one another
Be coupled to governor circuit 2 after resistance R6, the input pin/SDI is coupled with after capacitance C10 be coupled with resistance R12 after be grounded, it is described defeated
Go out the input pin SDI that foot SDO is coupled to weight timing chip U9, the output pin SDO, which is coupled with after resistance R29, to be coupled to when resetting
Input pin/SDI of chip U9, the output pin/SDO are coupled to input pin/SDI of weight timing chip U9.
Through the above technical solutions, adaptive chip U5 can be LMH0344, signal passes through after inductance L1 and resistance R6
It is input to adaptive chip U5 after crossing capacitance C4, adaptive chip U5 handles the signal of input, to corresponding frequency model
Enclose it is interior deamplification is promoted and is compensated after export, inductance L1 and resistance R6 screen signal, and inductance L1 and
The left and right, and Electromagnetic Interference always jointly resistance R6, further increases the effect of stabling current, and resistance R29 is arranged in data
Between line, the stability of data transmission is improved, and input pin/SDI is coupled with after capacitance C10 after being coupled with resistance R12 and is grounded,
Input pin/SDI is set more to stablize, the surge that resistance R5 makes signal occur enters ground after low resistance, further increases circuit
Stability.
As a kind of improved specific implementation mode, the driving circuit 33 includes driving chip M1, the driving core
Piece M1 has input pin TD, input pin/TD, output pin SD, output pin RD, output pin/RD, supply pin VCCTX and supply pin
VCCRX, the input pin TD are coupled to the output pin SDO, the input pin/TD for weighing timing chip U9 after being coupled with resistance R40
It is coupled with the output pin SDO that weight timing chip U9 is coupled to after resistance R41, the input pin TD is coupled after being coupled with resistance R48
To input pin/TD, the input pin TD is coupled to power supply VCC33_T after being coupled with resistance R3, is grounded after being coupled with resistance R8, institute
It states after output pin TD is coupled with resistance R4 and is coupled to power supply VCC33_T, be grounded after being coupled with resistance R29, the supply pin VCCTX
Be grounded after being coupled with capacitance C1, the supply pin VCCTX is coupled with after inductance L3 be coupled with capacitance C12 after be grounded, the inductance
The tie point of L3 and capacitance C12 is coupled to power supply VCC+3.3V, and the supply pin VCCRX is grounded after being coupled with capacitance C2, described
Supply pin RX is coupled with after inductance L4 be coupled with capacitance C13 after be grounded, the tie point of the inductance L4 and capacitance C13 is coupled to electricity
Source VCC+3.3V, the power supply VCC+3.3V are grounded after being coupled with electrolytic capacitor EC3, and the output pin SD is coupled with amplifying circuit
After export.
Through the above technical solutions, driving chip M1 uses dual power supply, receives and output is all made of independently-powered, be
It receives and output is not interfere with each other, and inductance L3 and capacitance C1, electrolytic capacitor EC3 and capacitance C12 filter the power supply of reception
Wave and inductance L4 and capacitance C2, electrolytic capacitor EC3 and capacitance C13 are filtered the power supply of output, use an electrolytic capacitor
EC3 reduces component use, reduces cost, reduce pcb board in the case where not reducing filter effect.
As a kind of improved specific implementation mode, the conversion circuit 34 includes conversion chip U4, the conversion core
The positive and negative anodes input pin of piece U4 is connect with the input pin TD of driving chip M1 and input pin/TD respectively, the conversion chip U4's
Positive and negative anodes output pin has been respectively coupled to be grounded after being coupled with capacitance C14 after being connected with each other after resistance R14 and resistance R15, described turn
Change chip U4 positive output pin be coupled with after inductance L5 parallel with one another and resistance R16 be coupled with capacitance C15 after export.
Through the above technical solutions, conversion chip U4 can be GV8500, conversion chip U4 is converted after receiving signal,
And export transformed signal, resistance R14 and capacitance C14, resistance R15 and capacitance C14 are respectively formed LC filter circuits, improve defeated
Go out the stability of signal, and connect with capacitance C15 after inductance L5 and resistance R16 parallel connections, output signal is filtered same
When, the electromagnetic interference between late-class circuit and conversion circuit 34 is also reduced, the stability of output signal is improved.
As a kind of improved specific implementation mode, the positive and negative anodes input pin of the conversion chip U4 is with driving chip M1's
The positive and negative anodes input of capacitance C17 and capacitance C16, the conversion chip U4 are in series between input pin TD and input pin/TD respectively
Foot has been respectively coupled to be grounded after being coupled with capacitance C36 after being connected with each other after resistance R37 and resistance R38.
Through the above technical solutions, capacitance C16 and capacitance C17 are filtered signal, the stability of signal transmission is improved,
And resistance R37 and capacitance C36, resistance R38 and capacitance C36 are respectively formed LC filter circuits, further increase signal between circuit
The stability of transmission, meanwhile, resistance R37 and resistance R38 share a capacitance C36, in the case where not reducing filter effect, into
One step reduces component use, reduces cost, reduces pcb board.
As a kind of improved specific implementation mode, the power circuit 1 includes voltage stabilizing chip U7, the voltage stabilizing chip
The input pin of U7 is coupled to power supply+24V after being coupled with switch 3F1, and the enabled foot of the voltage stabilizing chip U7 is coupled with resistance 3R23
After be coupled to input pin, the tie point of the switch 3F1 and power supply+24V is grounded after being coupled with diode 3DV1, the voltage stabilizing core
The input pin of piece U7 is grounded after being coupled with electrolytic capacitor 3EC1, and the output pin of the power supply chip U7 exports after being coupled with inductance L6
Power supply VCC5, the power supply VCC5 are grounded after being coupled with capacitance 3C15 parallel with one another and electrolytic capacitor 3EC2, the voltage stabilizing core
The bootstrapping foot of piece U7 is coupled to output pin after being coupled with capacitance 3C14, and output pin is grounded after being coupled with diode 3ZD3, the electricity
The tie point of sense L6 and electrolytic capacitor 3EC2 is coupled with after resistance 3R19 be coupled with resistance 3R18 after be grounded, the resistance 3R19 is simultaneously
The feedback foot for being associated with capacitance 3C11, the voltage stabilizing chip U7 is coupled to the tie point of resistance 3R19 and resistance 3R18.
Through the above technical solutions, voltage stabilizing chip U7 can be MP2494DS, power input to input pin, in diode
3DV1 is Transient Suppression Diode, the surge damage voltage stabilizing chip U7 being arranged in the input port of voltage stabilizing chip U7 avoids circuit,
Electrolytic capacitor 3EC1 and diode 3DV1 is formed into a loop, and improves the stability for the power supply for being input to voltage stabilizing chip U7, electricity when power-off
Capacitance 3EC1 electric discharges are solved, resistance 3R23 carries out current limliting, protects and enables foot, and then improves the stability of voltage stabilizing chip U7, voltage stabilizing core
Power supply signal after piece U7 output voltage stabilizings, capacitance 3C14 connection output pins and bootstrapping foot allow voltage stabilizing chip U7 to boot, improve
The stability of voltage stabilizing chip U7 work, is output to later on inductance L6, and inductance L6 stablizes the power supply signal of output, resistance 3R19 and
Resistance 3R18 divides output signal, and feedback foot is connected thereto acquisition signal, and then adjusts output signal, makes output signal
More stablize, feedback foot receives the signal after partial pressure, avoids surge impact damage feedback foot, improves the steady of voltage stabilizing chip U7 work
Qualitative, when capacitance 3C11 is fluctuated suddenly primarily directed to input voltage or output loading is fluctuated suddenly, output voltage generates change
Increase feedback quantity (i.e. feedback intensity) when change and reaches stable with timely adjustment output.Accelerate the dynamic response mistake of power supply
Journey so that output pulsation range reduces when input voltage mutation or load sudden change, avoids over control, increases stability, output
Capacitance C15 parallel with one another and electrolytic capacitor 3EC2 is set on power supply VCC5, while improving output stability, also avoids rear class
Parasitic couplings between circuit and power circuit 1 improve the stability of HD-SDI multi-service HD video optical transmitter and receivers work.
The above is only a preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-mentioned implementation
Example, all technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
Those of ordinary skill for, several improvements and modifications without departing from the principles of the present invention, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of HD-SDI multi-services HD video optical transmitter and receiver, includes：Power circuit (1), governor circuit (2) and transmission circuit
(3), the power circuit (1) connect with governor circuit (2), powers to governor circuit (2), transmission circuit (3) the connection master
Circuit (2) and external interface are controlled, receives and sends signal, it is characterised in that：The transmission circuit (3) includes equalizing circuit
(31), re-clocking circuit (32), driving circuit (33) and conversion circuit (34), equalizing circuit (31) the connection master control electricity
Road (2) and re-clocking circuit (32), the re-clocking circuit (32) respectively with driving circuit (33) and conversion circuit
(34) it connects, the driving circuit (33) connect with conversion circuit (34), and the conversion circuit (34) connect with external interface, institute
It includes weight timing chip U9 and its peripheral circuit, the balanced electricity of heavy timing chip U9 connections to state re-clocking circuit (32)
Road (31), driving circuit (33) and conversion circuit (34), receiver equalization circuitry (31) output signal after export.
2. HD-SDI multi-services HD video optical transmitter and receiver according to claim 1, it is characterised in that：The equalizing circuit
(31) include adaptive chip U5, the adaptive chip U5 has input pin SDI, input pin/SDI, output pin SDO and defeated
Go out foot/SDO, the input ports SDI are coupled with after capacitance C4 be coupled with resistance R5 after be grounded, the company of the capacitance C4 and resistance R5
Contact is coupled to governor circuit (2) after being coupled with inductance L1 parallel with one another and resistance R6, and the input pin/SDI is coupled with electricity
Hold and be grounded after being coupled with resistance R12 after C10, the output pin SDO is coupled to the input pin SDI of weight timing chip U9, described defeated
Go out after foot SDO is coupled with resistance R29 and be coupled to the input pin/SDI for weighing timing chip U9, the output pin/SDO, which is coupled to, to be reset
When chip U9 input pin/SDI.
3. HD-SDI multi-services HD video optical transmitter and receiver according to claim 2, it is characterised in that：The driving circuit
(33) include driving chip M1, the driving chip M1 have input pin TD, input pin/TD, output pin SD, output pin RD,
Output pin/RD, supply pin VCCTX and supply pin VCCRX, the input pin TD are coupled to core when resetting after being coupled with resistance R40
The output pin SDO, the input pin/TD of piece U9 is coupled to the output pin SDO for weighing timing chip U9, institute after being coupled with resistance R41
It states after input pin TD is coupled with resistance R48 and is coupled to input pin/TD, the input pin TD is coupled to power supply after being coupled with resistance R3
VCC33_T is grounded after being coupled with resistance R8, and the output pin TD is coupled to power supply VCC33_T after being coupled with resistance R4, is coupled with
It is grounded after resistance R29, the supply pin VCCTX is grounded after being coupled with capacitance C1, after the supply pin VCCTX is coupled with inductance L3
It is grounded after being coupled with capacitance C12, the tie point of the inductance L3 and capacitance C12 is coupled to power supply VCC+3.3V, the supply pin
VCCRX is grounded after being coupled with capacitance C2, the supply pin RX is coupled with after inductance L4 be coupled with capacitance C13 after be grounded, the electricity
The tie point of sense L4 and capacitance C13 are coupled to power supply VCC+3.3V, and the power supply VCC+3.3V is coupled with electrolytic capacitor EC3 and is followed by
Ground, the output pin SD are exported after being coupled with amplifying circuit.
4. HD-SDI multi-services HD video optical transmitter and receiver according to claim 3, it is characterised in that：The conversion circuit
(34) include conversion chip U4, the positive and negative anodes input pin of the conversion chip U4 respectively with the input pin TD of driving chip M1 and
Input pin/TD connections, the positive and negative anodes output pin of the conversion chip U4 mutually interconnect after being respectively coupled to resistance R14 and resistance R15
It is grounded after being coupled with capacitance C14 after connecing, the positive output pin of the conversion chip U4 is coupled with inductance L5 and electricity parallel with one another
It is exported after being coupled with capacitance C15 after resistance R16.
5. HD-SDI multi-services HD video optical transmitter and receiver according to claim 4, it is characterised in that：The conversion chip U4
Positive and negative anodes input pin and the input pin TD and input pin/TD of driving chip M1 between be in series with capacitance C17 and capacitance respectively
The positive and negative anodes input pin of C16, the conversion chip U4 have been respectively coupled to be coupled with after being connected with each other after resistance R37 and resistance R38
It is grounded after capacitance C36.
6. the HD-SDI multi-service HD video optical transmitter and receivers according to claim 1 to 5 any one, it is characterised in that：Institute
It includes voltage stabilizing chip U7 to state power circuit (1), and the input pin of the voltage stabilizing chip U7 is coupled to power supply after being coupled with switch 3F1
The enabled foot of+24V, the voltage stabilizing chip U7 are coupled to input pin, the switch 3F1 and power supply+24V after being coupled with resistance 3R23
Tie point be coupled with diode 3DV1 after be grounded, the input pin of the voltage stabilizing chip U7 is coupled with electrolytic capacitor 3EC1 and is followed by
Ground, the output pin of the power supply chip U7 are coupled with out-put supply VCC5, the power supply VCC5 after inductance L6 and are coupled with mutually simultaneously
It is grounded after the capacitance 3C15 and electrolytic capacitor 3EC2 of connection, the bootstrapping foot of the voltage stabilizing chip U7 is coupled to after being coupled with capacitance 3C14
Output pin, output pin are grounded after being coupled with diode 3ZD3, and the tie point of the inductance L6 and electrolytic capacitor 3EC2 is coupled with electricity
It is grounded after being coupled with resistance 3R18 after resistance 3R19, the resistance 3R19 is parallel with capacitance 3C11, the feedback of the voltage stabilizing chip U7
Foot is coupled to the tie point of resistance 3R19 and resistance 3R18.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810391861.5A CN108390723B (en) | 2018-04-27 | 2018-04-27 | HD-SDI multi-service high-definition video optical transmitter and receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810391861.5A CN108390723B (en) | 2018-04-27 | 2018-04-27 | HD-SDI multi-service high-definition video optical transmitter and receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108390723A true CN108390723A (en) | 2018-08-10 |
| CN108390723B CN108390723B (en) | 2023-11-14 |
Family
ID=63065694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810391861.5A Active CN108390723B (en) | 2018-04-27 | 2018-04-27 | HD-SDI multi-service high-definition video optical transmitter and receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108390723B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156369A (en) * | 1995-11-07 | 1997-08-06 | 三菱电机株式会社 | Timing playback device and diversity communication device |
| CN101783969A (en) * | 2009-09-30 | 2010-07-21 | 西安交通大学 | Comprehensive monitoring device of signal quality of digital television |
| CN202475622U (en) * | 2012-02-23 | 2012-10-03 | 深圳市高视数字技术有限公司 | Automatic SDI video signal recognition system of coding front end |
| CN103188450A (en) * | 2011-12-30 | 2013-07-03 | 北京同步科技有限公司 | Digital video distributor and processing method of the same |
| CN104639899A (en) * | 2015-01-30 | 2015-05-20 | 上海电控研究所 | High-definition SDI (Serial Digital Interface) digital video signal optical fiber transparent transmission device |
| CN208158591U (en) * | 2018-04-27 | 2018-11-27 | 浙江恒捷通信科技有限公司 | A kind of HD-SDI multi-service HD video optical transmitter and receiver |
-
2018
- 2018-04-27 CN CN201810391861.5A patent/CN108390723B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1156369A (en) * | 1995-11-07 | 1997-08-06 | 三菱电机株式会社 | Timing playback device and diversity communication device |
| CN101783969A (en) * | 2009-09-30 | 2010-07-21 | 西安交通大学 | Comprehensive monitoring device of signal quality of digital television |
| CN103188450A (en) * | 2011-12-30 | 2013-07-03 | 北京同步科技有限公司 | Digital video distributor and processing method of the same |
| CN202475622U (en) * | 2012-02-23 | 2012-10-03 | 深圳市高视数字技术有限公司 | Automatic SDI video signal recognition system of coding front end |
| CN104639899A (en) * | 2015-01-30 | 2015-05-20 | 上海电控研究所 | High-definition SDI (Serial Digital Interface) digital video signal optical fiber transparent transmission device |
| CN208158591U (en) * | 2018-04-27 | 2018-11-27 | 浙江恒捷通信科技有限公司 | A kind of HD-SDI multi-service HD video optical transmitter and receiver |
Non-Patent Citations (3)
| Title |
|---|
| 周弟伟;段明玮;王振;: "数字高清视频传输与视频接口的转换设计研究", 电子世界, no. 15 * |
| 朱超;刘艳滢;董月芳;: "基于FPGA的SDI到Camera Link视频接口转换系统设计", 测控技术, no. 02 * |
| 李鸿强;苗长云;: "高清晰度数字视频SDI卡的设计", 电子器件, no. 03 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108390723B (en) | 2023-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109150551B (en) | Non-standard POE power supply circuit, power supply equipment and power supply method for network port | |
| CN106208708B (en) | Power adapter and its control circuit and standby energy-saving method | |
| US8521031B2 (en) | Optical transceiver modules and systems and optical transceiving methods | |
| CN110018726A (en) | The main website machine device for providing power supply simultaneously using two lines bus and being communicated | |
| CN208158591U (en) | A kind of HD-SDI multi-service HD video optical transmitter and receiver | |
| CN208239974U (en) | The main website machine device for providing power supply simultaneously using two lines bus and being communicated | |
| US20220394363A1 (en) | Optical line terminal line card and method compatible with pon function | |
| WO2017004798A1 (en) | A multifunctional laser diode driving circuit, a module comprising the same, and a method using the same | |
| CN108390723A (en) | A kind of HD-SDI multi-services HD video optical transmitter and receiver | |
| CN109144929A (en) | A kind of RS232 communication interface circuit for supporting hot plug | |
| CN112583682A (en) | Bus communication circuit and device | |
| EP3694119B1 (en) | Optical module | |
| CN111625491A (en) | Multi-machine serial communication device and method | |
| CN204086381U (en) | Train power supply monitoring subsystem leakage current test module | |
| US20210375335A1 (en) | Data writing method and apparatus | |
| CN110515875A (en) | A kind of Power supply circuit and method | |
| CN213906694U (en) | Bus communication circuit and device | |
| CN114003046A (en) | Positioning circuit supporting debugging, debugging control method, electronic device and vehicle | |
| CN106533403A (en) | High-performance isolation, distribution and amplification equipment | |
| CN209930254U (en) | Serial port self-sending and self-receiving control circuit | |
| CN209982499U (en) | 25G optical module | |
| CN208190831U (en) | A kind of high definition HDMI optical transmitter and receiver | |
| CN219513850U (en) | Photovoltaic grid-connected switch based on Bluetooth communication | |
| US20160335212A1 (en) | Device for switching between communication modes | |
| CN110018974A (en) | The slave station machine device for providing power supply simultaneously using two lines bus and being communicated |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |