CN208143194U - Inductor with ESD defencive function - Google Patents
Inductor with ESD defencive function Download PDFInfo
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- CN208143194U CN208143194U CN201790000576.5U CN201790000576U CN208143194U CN 208143194 U CN208143194 U CN 208143194U CN 201790000576 U CN201790000576 U CN 201790000576U CN 208143194 U CN208143194 U CN 208143194U
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- 239000000758 substrate Substances 0.000 claims abstract description 116
- 239000004020 conductor Substances 0.000 claims description 90
- 239000011229 interlayer Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000010410 layer Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 29
- 230000005611 electricity Effects 0.000 claims description 13
- 239000004615 ingredient Substances 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims 1
- 238000009434 installation Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 102100027417 Cytochrome P450 1B1 Human genes 0.000 description 7
- 101000725164 Homo sapiens Cytochrome P450 1B1 Proteins 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000002002 slurry Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910000859 α-Fe Inorganic materials 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000004043 responsiveness Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- BGOFCVIGEYGEOF-UJPOAAIJSA-N helicin Chemical compound O[C@@H]1[C@@H](O)[C@H](O)[C@@H](CO)O[C@H]1OC1=CC=CC=C1C=O BGOFCVIGEYGEOF-UJPOAAIJSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to a kind of inductors with ESD defencive function, should have LGA type SMT Inductor (1) and diode chip for backlight unit (2) with the inductor (101) of ESD defencive function.LGA type SMT Inductor (1) has：Substrate (10) with the first interarea (VS1) as mounting surface；It is formed in the coil of substrate；The first input and output electrode (P1) and the second input and output electrode (P2) being connect with coil；Grounding electrode (GP)；The first connection electrode (CP1) being connect with coil；The second connection electrode (CP2) being connect with grounding electrode.First input and output electrode (P1), the second input and output electrode (P2) and ground wire electrode are formed in the first interarea.Diode chip for backlight unit (2) is equipped on LGA type SMT Inductor, and the first connection electrode and the second connection electrode of LGA type SMT Inductor are connect with the diode functioned as ESD protection device respectively.
Description
Technical field
The utility model relates to the inductors with ESD defencive function, more particularly to have the band of inductor and diode
There is the inductor of ESD defencive function.
Background technique
In the past, it is based on ESD (Electro-Static Discharge in order to prevent；Static discharge) electronic equipment
Damage, malfunction etc., and utilize various esd protection circuits.Esd protection circuit is protected for ESD to be discharged into ground wire etc.
The circuit that the electronic circuit of rear class is influenced from ESD, such as configuration is between signal line and ground wire (ground connection).
For example, in patent document 1, disclosing one kind and being provided near antenna terminal for ESD conservation measures
The electronic equipment of filter circuit with ESD defencive function.
Patent document 1：Japanese Unexamined Patent Publication 2008-54055 bulletin
But if in order to constitute the circuit with ESD defencive function as shown in Patent Document 1, and by multiple discrete portions
Part configures on installation base plate, then there are problems that mounting area increase.In addition, due to the wiring that will be used to connect discrete parts
It is formed in installation base plate, it is also possible to cause length of arrangement wire elongated and cannot get necessary characteristic.
Utility model content
The purpose of this utility model is to provide one kind can reduce required mounting area, and inhibits electrical characteristics
The inductor with ESD defencive function changed.
(1) inductor with ESD defencive function of the utility model is characterized in that,
Have LGA type SMT Inductor and diode chip for backlight unit,
Above-mentioned LGA type SMT Inductor has：Substrate with the first interarea as mounting surface；It is formed in above-mentioned substrate
Coil；It is formed in above-mentioned first interarea, and the first input and output electrode connecting with the first end of above-mentioned coil；It is formed in
State the first interarea, and the second input and output electrode connecting with the second end of above-mentioned coil；It is formed in connecing for above-mentioned first interarea
Ground electrode；The first connection electrode being connect with above-mentioned coil；And the second connection electrode being connect with above-mentioned grounding electrode；With
Above-mentioned diode chip for backlight unit has：Semiconductor substrate；It is formed in above-mentioned semiconductor substrate, and as ESD protection device
The diode functioned；And the first terminal electrode and second being separately connected with the first end and second end of above-mentioned diode
Terminal electrode,
Above-mentioned diode chip for backlight unit is equipped on above-mentioned LGA type SMT Inductor,
The above-mentioned first terminal electrode and above-mentioned second terminal electrode of above-mentioned diode chip for backlight unit respectively with above-mentioned LGA type patch
Above-mentioned first connection electrode of inductor is connected with above-mentioned second connection electrode.
According to this structure, installation base plate etc. is equipped on by the inductor chip and diode chip for backlight unit that are used as discrete parts
Situation is compared, and mounting area required for circuit structure can be reduced.In addition, according to this structure, being equipped on by discrete parts
The situation of installation base plate etc. is compared, and the length of arrangement wire between diode and coil can be shortened.Therefore, can be realized diode with
The conductor resistance in wiring, parasitic inductance between coil reduce, and ESD inhibits voltage is lower and responsiveness is higher to have ESD
The inductor of defencive function.
(2) in above-mentioned (1), preferably above-mentioned substrate have second interarea opposed with above-mentioned first interarea, above-mentioned first
Connection electrode and above-mentioned second connection electrode are formed in above-mentioned second interarea, and above-mentioned diode chip for backlight unit is equipped on the upper of above-mentioned substrate
State the second interarea.According to this structure, compared with the case where being equipped with diode chip for backlight unit in the end face etc. of substrate, it can reduce and have
The mounting area (area especially in plane) of the inductor of ESD defencive function.
(3) in above-mentioned (2), preferably when overlooking above-mentioned first interarea and above-mentioned second interarea, above-mentioned diode chip for backlight unit
It is Chong Die with above-mentioned coil.In this configuration, with overlook the first interarea and diode chip for backlight unit is not Chong Die with coil when the second interarea
Structure compare, due to diode chip for backlight unit and coil in the plane at a distance from shorten, so the wiring between diode and coil
Length further shortens.Therefore, conductor resistance, the parasitic electricity in the wiring between diode and coil can be further decreased
Sense.
(4) in any one of above-mentioned (1)~(3), above-mentioned substrate is also possible to the laminated body of multiple insulated base material layers.
It (5), can also be by the inductance ingredient of above-mentioned LGA type SMT Inductor and upper in any one of above-mentioned (1)~(4)
It states capacitive component possessed by diode and constitutes low-pass filter.
(6) in any one of above-mentioned (1)~(5), can also have be formed in above-mentioned substrate the first interlayer connection lead
Body, above-mentioned first connection electrode are connect via above-mentioned first interlayer connection conductor with above-mentioned coil.
(7) in any one of above-mentioned (1)~(6), preferably above-mentioned substrate is magnetic body component, above-mentioned to protect with ESD
The inductor of function has the conductor introduction for the outer surface for being formed in above-mentioned substrate, and above-mentioned grounding electrode is via above-mentioned conductor introduction
It is connect with above-mentioned second connection electrode.According to this structure, magnetic substance is formed in by the wiring between diode and grounding electrode
The situation of the inside of component is compared, and the parasitic inductor generated in the wiring between diode and grounding electrode is able to suppress.
Therefore, ESD defencive function (removal function), the attenuation characteristic of filter of the inductor with ESD defencive function are improved.
According to the utility model, can be realized can reduce required mounting area, and inhibit the variation of electrical characteristics
The inductor with ESD defencive function.
Detailed description of the invention
(A) of Fig. 1 is the perspective view of the inductor 101 involved in first embodiment with ESD defencive function, Fig. 1
(B) be LGA type SMT Inductor 1 perspective view.
(A) of Fig. 2 is the main view of the inductor 101 with ESD defencive function, and (B) of Fig. 2 is to protect function with ESD
The top view of the inductor 101 of energy.
(A) of Fig. 3 is the top view of LGA type SMT Inductor 1, and (B) of Fig. 3 is the A-A cross-sectional view of Fig. 2 (A), figure
3 (C) is the bottom view of LGA type SMT Inductor 1.
Fig. 4 is the perspective view for indicating conductor possessed by LGA type SMT Inductor 1 and electrode.
(A) of Fig. 5 is the bottom view of diode chip for backlight unit 2, and (B) of Fig. 5 is the longitudinal section view of diode chip for backlight unit 2.
Fig. 6 is the circuit diagram of the inductor 101 with ESD defencive function.
(A) of Fig. 7 is the perspective view of the inductor 102 involved in second embodiment with ESD defencive function, Fig. 7
(B) be with ESD defencive function inductor 102 main view.
(A) of Fig. 8 is the top view of LGA type SMT Inductor 1A, and (B) of Fig. 8 is the B-B cross-sectional view of Fig. 7 (B),
(C) of Fig. 8 is the bottom view of LGA type SMT Inductor 1A.
Fig. 9 is the perspective view for indicating conductor possessed by LGA type SMT Inductor 1A and electrode.
Figure 10 is the circuit diagram of the inductor 102 with ESD defencive function.
(A) of Figure 11 is the perspective view of the inductor 103 involved in third embodiment with ESD defencive function, figure
11 (B) is the main view of the inductor 103 with ESD defencive function.
(A) of Figure 12 is the top view of LGA type SMT Inductor 1B, and (B) of Figure 12 is the C-C section view of Figure 11 (B)
Figure, (C) of Figure 12 is the bottom view of LGA type SMT Inductor 1B.
Figure 13 is the perspective view for indicating conductor and electrode possessed by LGA type SMT Inductor 1B.
Figure 14 is the circuit diagram of the inductor 103 with ESD defencive function.
Figure 15 is the perspective view of the inductor 104 involved in the 4th embodiment with ESD defencive function.
(A) of Figure 16 is the perspective view of LGA type SMT Inductor 1C, and (B) of Figure 16 is to indicate LGA type SMT Inductor 1C
The perspective view of possessed conductor and electrode.
Figure 17 is the circuit diagram of the inductor 104 with ESD defencive function.
Description of symbols
L1, L2, L3 ... coil；D1, D1A, D1B ... diode；1,1A, 1B, 1C ... LGA type SMT Inductor；10,
10A, 10B, 10C ... substrate；First interarea of VS1 ... substrate；Second interarea of VS2 ... substrate；GP ... grounding electrode；P1…
First input and output electrode；The second input and output electrode of P2 ...；The first connection electrode of CP1, CP1A, CP1B ...；CP2 ... second connects
Receiving electrode；V1, V2, V3, V4, V5 ... interlayer connection conductor；V3P ... conductor introduction；31,32, 32A,32B,32C,33,33A,
33B, 33C ... coil；The first end of E1 ... coil；The second end of E2 ... coil；The third end of E3 ... coil；The of E4 ... coil
Four ends；41 ... conductors；2,2A, 2B ... diode chip for backlight unit；EP1 ... first terminal electrode；EP2 ... second terminal electrode；20 ... half
Conductor substrate；21 ... semiconductor element portions；The element forming face of S1 ... semiconductor substrate；3,4 ... insulating layers；51,52 ... electrodes；
101,102,103,104 ... the inductor with ESD defencive function.
Specific embodiment
Hereinafter, enumerating several specific examples referring to attached drawing to indicate multiple modes for implementing the utility model.?
Identical appended drawing reference is labelled with mutually existing together in each figure.In view of the explanation of main points or the easiness of understanding, for convenience
For the sake of, embodiment, which is split, to be indicated, but is able to carry out the partial replacement or group of structure shown in different embodiments
It closes.The description with the common item of first embodiment is omitted after second embodiment, and only difference is illustrated.Especially
It is that identical function and effect caused by identical structure will not successively be referred in each embodiment.
《First embodiment》
(A) of Fig. 1 is the perspective view of the inductor 101 with ESD defencive function of first embodiment, and (B) of Fig. 1 is
The perspective view of LGA type SMT Inductor 1.(A) of Fig. 2 is the main view of the inductor 101 with ESD defencive function, Fig. 2's
It (B) is the top view for having the inductor 101 of ESD defencive function.In (B) of Fig. 1, the first input and output electricity is represented by dashed line
Pole P1, the second input and output electrode P2 and grounding electrode GP.In addition, being represented by dashed line in (A) of Fig. 2 and (B) of Fig. 2
Coil 31, conductor 41 and interlayer connection conductor V1, V2, V5.
Inductor 101 with ESD defencive function has LGA type SMT Inductor 1, is equipped on LGA type SMT Inductor
1 diode chip for backlight unit 2.
" LGA type SMT Inductor " in the utility model refers to only in the mounting surface (" substrate being described in more detail below
The first interarea ") have installation electrode (" the first input and output being described in more detail below to installations such as installation base plates
Electrode, the second input and output electrode and grounding electrode "), and do not have the patch electricity of installation electrode in end face and top surface
Sensor.
(A) of Fig. 3 is the top view of LGA type SMT Inductor 1, and (B) of Fig. 3 is the A-A cross-sectional view of Fig. 2 (A), figure
3 (C) is the bottom view of LGA type SMT Inductor 1.Fig. 4 is to indicate conductor and electricity possessed by LGA type SMT Inductor 1
The perspective view of pole.
There is LGA type SMT Inductor 1 substrate 10, the coil 31 for the inside for being formed in substrate 10, conductor 41, first to input
Output electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode CP1, the second connection electrode CP2 and
Interlayer connection conductor V1, V2, V3, V4, V5.
Substrate 10 is that have mutually opposed the first interarea VS1 and the second interarea VS2 and longitudinal direction is consistent with X-direction
Cube insulator plate.First interarea VS1 and the second interarea VS2 are orthogonal with Z-direction and are parallel to X/Y plane
Face.Substrate 10 involved in present embodiment is the laminated body of multiple insulated base material layers.First interarea VS1 of substrate 10 is
To the mounting surface of the installations such as installation base plate.Substrate 10 is, for example, as low-temperature co-fired ceramics (LTCC：Low Temperature Co-
Fired Ceramics) as dielectric ceramics.
The conductor for the spiral form (spiral) that 2 circles that coil 31 is formed at the inside of substrate 10 are had a surplus, in thickness direction
There is wireline reel in (Z-direction).Coil 31 constitutes the structure as Cu slurry of the insulated base material layer of substrate 10 such as being formed at
At conductive pattern.It has a surplus in addition, the number of turns of coil 31 is not limited to 2 circles, can be 1 circle, be also possible to 3 circles or more.
Conductor 41 is formed at the conductor of the L-shaped of the inside of substrate 10.Conductor 41 is for example formed at insulated base material layer
The conductive pattern being made of Cu slurry etc. of (insulated base material layers different from the insulated base material layer for being formed with coil 31).
First input and output electrode P1, the second input and output electrode P2 and grounding electrode GP are formed at the of substrate 10
The conductor of one interarea VS1.First input and output electrode P1, the second input and output electrode P2 and grounding electrode GP are longitudinal directions
With the conductor of the consistent rectangle of Y direction, the second input and output electrode P2, grounding electrode GP, the first input and output electrode P1 are pressed
Sequence configures side by side along X axis direction.First input and output electrode P1, the second input and output electrode P2 and grounding electrode GP
The conductive pattern of Cu slurry in this way etc..
First connection electrode CP1 and the second connection electrode CP2 is formed at the rectangle of the second interarea VS2 of substrate 10
Conductor.First connection electrode CP1 and the second connection electrode CP2 is near the center of the X-direction of the second interarea VS2 along Y-axis side
To configuration arranged side by side.First connection electrode CP1 and the second connection electrode CP2 is, for example, the conductive pattern of Cu slurry etc..
Interlayer connection conductor V1, V2, V3, V4, V5 are formed at the columned conductor of the inside of substrate 10.Interlayer connection
Conductor V1, V2, V3, V4, V5 are, for example, the through hole filling electric conductivity slurry to through-thickness (Z axis direction) perforation substrate 10
Via hole conductor or through-hole made of material etc..In the present embodiment, interlayer connection conductor V4, V5 is equivalent in the utility model
" the first interlayer connection conductor ".
As shown in figure 4, the first input and output electrode P1 connects via the first end E1 of interlayer connection conductor V1 and coil 31
It connects.Second input and output electrode P2 is connected via the second end of conductor 41 and interlayer connection conductor V2, V5 and coil 31.In addition,
First connection electrode CP1 via conductor 41 and interlayer connection conductor V4, V5 and coil 31 second end E2 connection.In addition, second
Connection electrode CP2 is connect via interlayer connection conductor V3 with grounding electrode GP.
(A) of Fig. 5 is the bottom view of diode chip for backlight unit 2, and (B) of Fig. 5 is the longitudinal section view of diode chip for backlight unit 2.
The diode that diode chip for backlight unit 2 has semiconductor substrate 20, is formed in semiconductor substrate 20 (is retouched in detail below
It states.), first terminal electrode EP1 and second terminal electrode EP2.
Semiconductor substrate 20 is the semiconductor with element forming face S1 and longitudinal direction and the consistent cube of Y direction
Substrate.Semiconductor substrate 20 is, for example, Si substrate.
As shown in (B) of Fig. 5, semiconductor element portion is formed in the region of the side element forming face S1 of semiconductor substrate 20
21.In semiconductor element portion 21, the n-type semiconductor of defined depth is formed in the side element forming face S1 of semiconductor substrate 20
Layer (N-shaped trap), has been formed separately 2 p-type semiconductor portions in the n-type semiconductor.2 p-type semiconductor portions are formed in element
Face S1 exposes.2 p-type semiconductor portions are formed at semiconductor element portion 21 in the part that element forming face S1 exposes and (partly lead
Structure base board 20) diode first end and second end.According to this structure, anode is respectively in element forming face S1 exposing, yin
2 pn-junction diodes extremely interconnected have Zener characteristic, and are formed in semiconductor element portion 21 (semiconductor substrate 20).Cause
This, which functions as ESD protection device.
Insulating layer 3,4 and electrode 51,52 are formed in the element forming face S1 of semiconductor substrate 20.Insulating layer 4 and insulation
Layer 3 is sequentially formed from the side element forming face S1.As shown in (B) of Fig. 5, the electrode 51 and p exposed in element forming face S1
The connection of type semiconductor portion.In addition, a part of electrode 51 is exposed to outside from the hole for being formed in insulating layer 3.Electrode 52 in member
Another p-type semiconductor portion connection that part forming face S1 exposes.In addition, a part of electrode 52 is from the hole for being formed in insulating layer 3
It is exposed to outside.Electrode 51,52 is, for example, Al film, and insulating layer 3 is, for example, SiO2Film.
The part that the electrode 51 exposes is the first terminal electrode EP1 of diode chip for backlight unit 2, and the part that electrode 52 exposes is
The second terminal electrode EP2 of diode chip for backlight unit 2.In this way, first terminal electrode EP1 and second terminal electrode EP2 are formed in half
The element forming face S1 of conductor substrate 20, respectively with the of the diode for being formed in semiconductor element portion 21 (semiconductor substrate 20)
One end is connected with second end.
In addition it is also possible to the exposed surface (first terminal electrode EP1 and second terminal electrode EP2) of electrode 51 and electrode 52
Implement plating processing.For example, being able to use using Ni as plating Au of substrate etc..
As shown in (A) of Fig. 2, diode chip for backlight unit 2 is equipped on the second interarea VS2 of substrate 10, so that the second of substrate 10
The element forming face S1 of interarea VS2 and semiconductor substrate 20 is opposed.The first terminal electrode EP1 of diode chip for backlight unit 2 and as a result,
Two-terminal electrode EP2 is connect with the first connection electrode CP1 of LGA type SMT Inductor 1 and the second connection electrode CP2 respectively.
In addition, as shown in (B) of Fig. 2, when overlooking the first interarea VS1 and the second interarea VS2 (from Z-direction
When), diode chip for backlight unit 2 is Chong Die with coil 31.
Fig. 6 is the circuit diagram of the inductor 101 with ESD defencive function.In Fig. 6, coil 31 is indicated with coil L1, is used
Diode D1 indicates the Zener diode that semiconductor substrate 20 is formed in shown in (B) of Fig. 5.
As shown in fig. 6, the inductor 101 with ESD defencive function is inputted in the first input and output electrode P1 and second
It is connected with coil L1 between output electrode P2 and is connected with diode between the second input and output electrode P2 and grounding electrode GP
The circuit of D1.First input and output electrode P1 is connect with the first end of coil L1, the second input and output electrode P2 and coil L1's
Second end connection.In addition, the second input and output electrode P2 is via the first connection electrode CP1 and first terminal electrode EP1 and two poles
The first end of pipe connects.Grounding electrode GP is via the second of the second connection electrode CP2 and second terminal electrode EP2 and diode D1
End connection.As shown in fig. 6, grounding electrode GP is connect with ground wire.As shown in fig. 6, grounding electrode GP is connect with ground wire.
In the present embodiment, electricity possessed by the inductance ingredient (coil L1) and diode D1 of LGA type SMT Inductor 1
Rongcheng divides composition low-pass filter.
The inductor 101 that ESD defencive function is had involved according to the present embodiment, has the following effect.
(a) inductor 101 with ESD defencive function is the knot that diode chip for backlight unit 2 is equipped on LGA type SMT Inductor 1
Structure.Therefore, compared with the inductor chip and diode chip for backlight unit that are used as discrete parts are equipped on the situation of installation base plate etc., energy
Enough reduce mounting area required for circuit structure.In addition, according to this structure, being equipped on installation base plate etc. with by discrete parts
Situation is compared, and the length of arrangement wire between diode and coil can be shortened.Therefore, it can be realized the cloth between diode and coil
Conductor resistance, parasitic inductance on line become smaller, and ESD inhibits voltage lower and the higher electricity with ESD defencive function of responsiveness
Sensor.
(b) in addition, in the present embodiment, diode chip for backlight unit 2 is equipped on the second interarea VS2 of substrate 10.According to the knot
Structure can reduce the electricity with ESD defencive function compared with the situation of the end face that diode chip for backlight unit 2 is equipped on to substrate 10 etc.
The mounting area (area especially in XY plane) of sensor 101.
When further, in the present embodiment, from Z-direction, diode chip for backlight unit 2 is Chong Die with coil 31.In the knot
In structure, with diode chip for backlight unit 2 is not compared with the structure that coil 31 is overlapped from Z-direction, due to diode chip for backlight unit 2 and coil
31 distance on plane (X/Y plane) shortens, so the length of arrangement wire between diode and coil further shortens.Therefore, energy
Enough further decrease conductor resistance in the wiring between diode and coil, parasitic inductance.
Inductor 101 with ESD defencive function is for example manufactured according to process described in following (1)~(5).
(1) firstly, preparing to be formed with coil 31, conductor 41, the first input and output electrode P1, the second input and output electrode
P2, grounding electrode GP, the first connection electrode CP1, the second connection electrode CP2 and interlayer connection conductor V1, V2, V3, V4, V5
Substrate 10.It is formed with coil 31 by stacking to wait, after multiple insulated base material layers of interlayer connection conductor and pressure welding, with 800 DEG C
Above temperature firing obtains substrate 10.Insulated base material layer before firing is, for example, that low-temperature co-fired ceramics (LTCC) is such
The raw cooks such as nonmagnetic material ferrite.
(2) next, in the first connection electrode CP1 of substrate 10 and leading for the second connection electrode CP2 printing slurry shape
Electrical grafting material.To conductive bonding material using in the case where solder, the of the second interarea VS2 for being formed in substrate 10
One connection electrode CP1 and the second connection electrode CP2 Printing Paste.
(3) next, preparing diode chip for backlight unit 2, and diode chip for backlight unit 2 is configured at substrate 10.Specifically, passing through patch
Piece machine configures diode chip for backlight unit 2 on the second interarea VS2, so that the first terminal electrode EP1 and second end of diode chip for backlight unit 2
Sub-electrode EP2 CP2 pairs of the first connection electrode CP1 and the second connection electrode with the second interarea VS2 for being formed in substrate 10 respectively
It sets.In addition it is also possible on first terminal electrode EP1 and second terminal electrode EP2, preparatory Printing Paste, and make its semi-solid preparation.
(4) next, by reflux technique, using conductive bonding material by the first connection electrode CP1 and first terminal
Electrode EP1 connection is connected the second connection electrode CP2 with second terminal electrode EP2 using conductive bonding material.
(5) in addition, above-mentioned operation is keeping the assembly substrate for being formed with multiple inductors 101 with ESD defencive function
It is handled under state.It is finally cut, it is single to be separated into each inductor 101 with ESD defencive function from assembly substrate
Position (monolithic).
《Second embodiment》
In this second embodiment, the structure for being formed in the coil of substrate is shown and circuit is different from the first embodiment
Example.
(A) of Fig. 7 is the perspective view of the inductor 102 involved in second embodiment with ESD defencive function, Fig. 7
(B) be with ESD defencive function inductor 102 main view.In (B) of Fig. 7, in order to be readily appreciated that structure, use
Dotted line indicates coil 32 and interlayer connection conductor V1, V2, V3.
Inductor 102 with ESD defencive function has LGA type SMT Inductor 1A and is equipped on LGA type chip inductor
The diode chip for backlight unit 2 of device 1A.
Involved by the structure and first embodiment of the LGA type SMT Inductor 1A of inductor 102 with ESD defencive function
And the inductor 101 with ESD defencive function it is different, other structures are identical.Hereinafter, to involved in first embodiment
It is illustrated with the different part of the inductor 101 of ESD defencive function.
(A) of Fig. 8 is the top view of LGA type SMT Inductor 1A, and (B) of Fig. 8 is the B-B section view in Fig. 7 (B)
Figure, (C) of Fig. 8 is the bottom view of LGA type SMT Inductor 1A.Fig. 9 is to show conductor possessed by LGA type SMT Inductor 1A
With the perspective view of electrode.
LGA type SMT Inductor 1A has substrate 10A, the coil 32 for the inside for being formed in substrate 10A, the first input and output
Electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode CP1, the second connection electrode CP2 and interlayer
Connect conductor V1, V2, V3, V4, V5.
Substrate 10A is that have mutually opposed the first interarea VS1 and the second interarea VS2 and longitudinal direction and X-direction
The insulator plate of consistent cube.Substrate 10A involved in present embodiment is the laminated body of multiple insulated base material layers.
Coil 32 is formed at the cricoid conductor of about 1 circle of the inside of substrate 10, in thickness direction (Z-direction)
With wireline reel.Coil 32A, 32C of insulated base material layer, to be formed in insulated base material layer (wired with being formed by being formed in for coil 32
Enclose the different insulated base material layer of insulated base material layer of 32A, 32C) coil 32B etc. constitute.Coil 32A, 32B, 32C are via formation
It is connected with each other in the interlayer connection conductor of insulated base material layer.In addition, the number of turns of coil 32 is not limited to about 1 circle, it is also possible to more
Circle.In addition, coil 32 is not limited to ring-type, it is also possible to helical form (helical) or spiral form.
For the first input and output electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode CP1
And second connection electrode CP2 structure, it is substantially identical with first embodiment.
As shown in figure 9, the first input and output electrode P1 connects via the first end E1 of interlayer connection conductor V1 and coil 32
It connects.Second input and output electrode P2 is connect via interlayer connection conductor V2 with the second end E2 of coil 32.First connection electrode
CP1 is connect via interlayer connection conductor V5 with the third end E3 near the center for the ring for being formed in coil 32.In addition, the second connection
Electrode CP2 is connect via interlayer connection conductor V3 with grounding electrode GP.
Figure 10 is the circuit diagram of the inductor 102 with ESD defencive function.In Figure 10, coil 32 is indicated with coil L2,
Diode chip for backlight unit 2 shown in (A) of Fig. 7 and (B) of Fig. 7 is indicated with diode D1.
As shown in Figure 10, the inductor 102 with ESD defencive function is inputted in the first input and output electrode P1 and second
It is connected with coil L2 between output electrode P2 and is connected with the electricity of diode D1 between the center of coil L2 and grounding electrode GP
Road.First input and output electrode P1 is connect with the first end of coil L2, the second end of the second input and output electrode P2 and coil L2
Connection.The first end of diode D1 is connect via the first connection electrode CP1 and first terminal electrode EP1 with the center of coil L2.
The second end of diode D1 is connect via the second connection electrode CP2 and second terminal electrode EP2 with grounding electrode GP.Such as Figure 10
Shown, grounding electrode GP is connect with ground wire.
According to this structure, diode D1 is connected to ground wire from the center of coil L2, and constituting has symmetry to input and output
T-type low-pass filter.That is, even if reversely installing input and output electrode, (input of the first input and output electrode P1 and second is defeated
Electrode P2 out) it also can be realized the inductor with the same characteristics with ESD defencive function.
As shown in the embodiment, diode can also be connect with the midway of coil.Although in addition, in present embodiment
In, the circuit that diode D1 is connected to ground wire from the center of coil L2 is shown, but it is not limited to this structure.Diode D1 can also
The position other than center to be connected to coil L2 and between ground wire.
《Third embodiment》
In the third embodiment, it shows and carries the example of 2 diode chip for backlight unit in LGA type SMT Inductor.
(A) of Figure 11 is the perspective view of the inductor 103 involved in third embodiment with ESD defencive function, figure
11 (B) is the main view of the inductor 103 with ESD defencive function.In (B) of Figure 11, be represented by dashed line coil 33 with
And interlayer connection conductor V1, V2, V3, V4, V5.
Inductor 103 with ESD defencive function has LGA type SMT Inductor 1B and is equipped on LGA type chip inductor
2 diode chip for backlight unit 2A, 2B of device 1B.
Diode chip for backlight unit 2A, 2B are identical as the diode chip for backlight unit 2 shown in the first embodiment.Hereinafter, to first
The different part of the related inductor 101 with ESD defencive function of embodiment is illustrated.
(A) of Figure 12 is the top view of LGA type SMT Inductor 1B, and (B) of Figure 12 is the C-C section view in Figure 11 (B)
Figure, (C) of Figure 12 is the bottom view of LGA type SMT Inductor 1B.Figure 13 is indicated possessed by LGA type SMT Inductor 1B
The perspective view of conductor and electrode.
LGA type SMT Inductor 1B has the input of coil 33, first of substrate 10B, the inside for being formed in substrate 10B defeated
Electrode P1, the second input and output electrode P2, grounding electrode GP, first connection electrode CP1A, CP1B, the second connection electrode CP2 out
And interlayer connection conductor V1, V2, V3, V4, V5.
Substrate 10B is that have mutually opposed the first interarea VS1 and the second interarea VS2 and longitudinal direction and X-direction one
The insulator plate of the cube of cause.Substrate 10B involved in present embodiment is the laminated body of multiple insulated base material layers.
Coil 33 is formed at the cricoid conductor of about 1 circle of the inside of substrate 10B.Coil 33 is by being formed in insulation base
Coil 33A, 33C of material layer, it is formed in the insulated base material layer (insulation different from the insulated base material layer for being formed with coil 33A, 33C
Substrate layer) coil 33B etc. constitute.Coil 33A, 33B, 33C are mutual via the interlayer connection conductor for being formed in insulated base material layer
Connection.In addition, the number of turns of coil 33 is not limited to about 1 circle, it is also possible to multiturn.In addition, coil 33 is not limited to ring-type, it can also
Spirally or spiral form.
First input and output electrode P1, the second input and output electrode P2 and grounding electrode GP are formed at substrate 10B's
The conductor of first interarea VS1.First input and output electrode P1, the second input and output electrode P2 and grounding electrode GP are long side sides
To the conductor with the consistent rectangle of Y direction, the second input and output electrode P2, grounding electrode GP, the first input and output electrode P1
Successively configuration side by side along the x axis.As shown in (C) of Figure 12, it is defeated that the width of the X-direction of grounding electrode GP is greater than the first input
The width of the X-direction of electrode P1 and the second input and output electrode P2 out.
First connection electrode CP1A, CP1B is arranged in the first side of the second interarea VS2 of substrate 10B (in (C) of Figure 12
Substrate 10B top) neighbouring rectangle conductor.X-direction of first connection electrode CP1A, CP1B in the second interarea VS2
Center nearby along the x axis side by side configuration.Second connection electrode CP2 is arranged in the second of the second interarea VS2 of substrate 10B
The conductor of the rectangle of side (substrate 10B following) in (C) of Figure 12 nearby.Second connection electrode CP2 is along the second interarea VS2's
X-direction configuration.
As shown in figure 13, the first input and output electrode P1 connects via the first end E1 of interlayer connection conductor V1 and coil 33
It connects.Second input and output electrode P2 is connect via interlayer connection conductor V2 with the second end E2 of coil 33.First connection electrode
CP1A is connect via interlayer connection conductor V4 with the third end E3 of coil 33.First connection electrode CP1B is led via interlayer connection
Body V5 is connect with the 4th end E4 of coil 33.In addition, the second connection electrode CP2 is via interlayer connection conductor V3 and grounding electrode
GP connection.
As shown in figure 11, diode chip for backlight unit 2A, 2B are equipped on to the second interarea VS2 of substrate 10B, so that substrate 10B
Second interarea VS2 is opposed with the element forming face S1 of semiconductor substrate 20.The first terminal electrode of diode chip for backlight unit 2A as a result,
(EP1) and second terminal electrode (EP2) connect electricity with the first connection electrode CP1A and second of LGA type SMT Inductor 1B respectively
Pole CP2 connection.In addition, the first terminal electrode (EP1) and second terminal electrode (EP2) of diode chip for backlight unit 2B respectively with LGA
The first connection electrode CP1B of type SMT Inductor 1B and the second connection electrode CP2 connection.
Figure 14 is the circuit diagram of the inductor 103 with ESD defencive function.In Figure 14, coil 33 is indicated with coil L3,
The diode that semiconductor substrate 20 is formed in shown in (A) of Figure 11 and (B) of Figure 11 is indicated with diode D1A, D1B.
As shown in figure 14, the inductor 103 with ESD defencive function is inputted in the first input and output electrode P1 and second
It is connected with coil L3 between output electrode P2 and connects respectively between the first end of coil L3 and second end and grounding electrode GP
It is connected to the circuit of diode D1A, D1B.First input and output electrode P1 is connect with the first end of coil L3, the second input and output electricity
Pole P2 is connect with the second end of coil L3.The first end of diode D1A is via the first connection electrode CP1A and first terminal electrode
EP1 is connect with the first end of coil L3.The second end of diode D1A is via the second connection electrode CP2 and second terminal electrode EP2
It is connect with grounding electrode GP.The first end of diode D1B is via the first connection electrode CP1B and first terminal electrode EP1 and coil
The second end of L3 connects.The second end of diode D1B is via the second connection electrode CP2 and second terminal electrode EP2 and ground connection electricity
Pole GP connection.As shown in figure 14, grounding electrode GP is connect with ground wire.
According to this structure, the low-pass filter that diode D1A, D1B are connected to ground wire from the both ends of coil L3 respectively is constituted.
In addition, according to this structure, the inductance with ESD defencive function for the circuit structure that there is symmetry to input and output can be obtained
Device.
As shown in the embodiment, be equipped on the diode chip for backlight unit of LGA type SMT Inductor quantity be also possible to it is multiple.
《4th embodiment》
In the fourth embodiment, showing substrate is magnetic body component, between grounding electrode and the second connection electrode CP2
It is routed the example different from first~third embodiment.
Figure 15 is the perspective view of the inductor 104 involved in the 4th embodiment with ESD defencive function.
Inductor 104 with ESD defencive function has LGA type SMT Inductor 1C, is equipped on LGA type SMT Inductor
The diode chip for backlight unit 2 of 1C.
Involved by the structure and first embodiment of the LGA type SMT Inductor 1C of inductor 104 with ESD defencive function
And the inductor 101 with ESD defencive function it is different, other structures are identical.Hereinafter, for involved by first embodiment
The different part of the inductor 101 with ESD defencive function be illustrated.
(A) of Figure 16 is the perspective view of LGA type SMT Inductor 1C, and (B) of Figure 16 is to show LGA type SMT Inductor 1C
The perspective view of possessed conductor and electrode.
LGA type SMT Inductor 1C has the input of coil 31, first of substrate 10C, the inside for being formed in substrate 10C defeated
Electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode CP1, the second connection electrode CP2 and layer out
Between connect conductor V1, V2, V4, V5 and conductor introduction V3P.
Substrate 10C is that have mutually opposed the first interarea VS1 and the second interarea VS2 and longitudinal direction and X-direction one
The insulator plate of the cube of cause.In the present embodiment, substrate 10C is, for example, magnetic body component (magnetic substance ferrite),
It and is the laminated body for the multiple insulated base material layers being made of magnetic substance ferrite.
Coil 31, the first input and output electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode
The structure and first embodiment of CP1, the second connection electrode CP2 and interlayer connection conductor V1, V2, V4, V5 are substantially identical.
Conductor introduction V3P is formed at the conductor of the semi-cylindrical of the outer surface of substrate 10C.Conductor introduction V3P is, for example,
With the line in the center of the columned via hole conductor, through hole etc. that are extended through through-thickness (Z-direction) by entire base
Conductor made of material through-thickness (Z-direction) cutting.
As shown in (B) of Figure 16, the first input and output electrode P1 via interlayer connection conductor V1 and coil 31 first end
E1 connection.Second input and output electrode P2 is connected via the second end of conductor 41 and interlayer connection conductor V2, V5 and coil 31.Separately
Outside, the first connection electrode CP1 via conductor 41 and interlayer connection conductor V4, V5 and coil 31 second end E2 connection.In addition,
Second connection electrode CP2 is connect via conductor introduction V3P with grounding electrode GP.
As shown in figure 15, diode chip for backlight unit 2 is equipped on the second interarea VS2 of substrate 10C.The of diode chip for backlight unit 2 as a result,
One terminal electrode (EP1) and second terminal electrode (EP2) respectively with the first connection electrode CP1 of LGA type SMT Inductor 1C and
Second connection electrode CP2 connection.
Figure 17 is the circuit diagram of the inductor 104 with ESD defencive function.In Figure 17, coil 31 is indicated with coil L1,
The diode that semiconductor substrate 20 is formed in shown in (A) of Figure 16 and (B) of Figure 16 is indicated with diode D1.
In this way, identical with first embodiment, inductance ingredient (coil L1) and two poles by LGA type SMT Inductor 1C
Capacitive component possessed by pipe D1 constitutes low-pass filter.
The inductor 104 that ESD defencive function is had involved according to the present embodiment, in addition to being retouched in first embodiment
Other than the effect stated, following effect is also acted as.
(c) in the present embodiment, substrate 10C is magnetic body component.According to this structure, do not made coil 31 enlarged
With the SMT Inductor of defined inductance value (or the number of turns not increasing coil 31).
(d) in the present embodiment, the wiring between diode D1 shown in Figure 17 and grounding electrode GP (ground wire) that is,
Conductor introduction V3P is formed in the outer surface of the substrate 10C as magnetic body component.According to this structure, with by diode D1 and connect
The situation that wiring between ground electrode GP is formed in the inside of magnetic body component (substrate) is compared, be able to suppress diode D1 with
The parasitic inductor generated in wiring between grounding electrode GP.Therefore, according to this structure, improve with ESD defencive function
The ESD defencive function (removal function) of inductor 104, the attenuation characteristic of filter.In addition, the effect is especially aobvious in high frequency
It writes.
In addition, in the present embodiment, showing the conductor introduction V3P of semi-cylindrical, but conductor introduction is not limited to this
Structure.Conductor introduction is also possible to be formed in the conductive pattern etc. of the outer surface of substrate.
《Other embodiments》
In each embodiment illustrated above, show substrate flat shape be rectangle cube example, but
It is not limited to this structure.The shape of substrate can suitably change in the range of playing the role of the utility model/effect.
The flat shape of substrate is for example also possible to polygon, circle, ellipse, L-shaped, crank shape, T-shaped, Y-shaped etc..
In each embodiment illustrated above, the example that substrate is the laminated body of multiple insulated base material layers is shown, but
It is not limited to this structure.Substrate is also possible to single layer.In addition, it is low for showing substrate in each embodiment illustrated above
Dielectric ceramics as warm common burning porcelain (LTCC) or the ferritic example of magnetic substance, but it is not limited to this structure.Substrate
Such as it is also possible to the resin-formed body being made of heat-curing resin.
In each embodiment illustrated above, about 1 circle in thickness direction (Z-direction) with wireline reel is shown
Ring-type or about 2 circles spiral form coil example, but it is not limited to this structure.The shape of coil, winding number can be
Play the role of suitably changing in the range of the utility model/effect.Coil is for example also possible to spiral helicine conductor.Separately
Outside, the wireline reel of coil also can suitably change in the range of playing the role of the utility model/effect, can also be along
X-direction or Y direction.In addition, showing in each embodiment illustrated above and forming coil in the inside of substrate
Example, but such as can also be some or all end faces (surface) for being formed in substrate by coil.
In addition, show composition low-pass filter has ESD defencive function in each embodiment illustrated above
Inductor example, but it is not limited to this structure.The circuit for being configured to the inductor with ESD defencive function can be suitably
Change.In addition, the component for being equipped on LGA type SMT Inductor can be according to being configured to the inductor with ESD defencive function
Circuit changes.For example, chip capacitor etc. can also be equipped on to LGA type SMT Inductor other than diode chip for backlight unit.
In each embodiment illustrated above, the second interarea VS2 that diode chip for backlight unit is equipped on to substrate is shown
Example, but it is not limited to this structure.The component for being equipped on LGA type SMT Inductor can also be formed in the first interarea VS1 and
Part other than two interarea VS2, such as end face can also be equipped on etc..Similarly, the connection of the first connection electrode CP1 and second electricity
Pole CP2 can also be formed in the part other than the first interarea VS1 and the second interarea VS2.
In each embodiment illustrated above, show the first input and output electrode P1, the second input and output electrode P2,
Grounding electrode GP, the first connection electrode CP1 and the second connection electrode CP2 are the example of the conductor of rectangle, but are not limited to this
Structure.First input and output electrode P1, the second input and output electrode P2, grounding electrode GP, the first connection electrode CP1 and second
The shape of connection electrode CP2 can be changed suitably.In addition, the first input and output electrode P1, the second input and output electrode P2,
Configuration/number of grounding electrode GP, the first connection electrode CP1 and the second connection electrode CP2 can also be protected according to ESD
The circuit structure of the inductor of function suitably changes.
In each embodiment illustrated above, leading by the element forming face S1 that is formed in semiconductor substrate 20 is shown
Body pattern constitutes the example of the first terminal electrode EP1 and second terminal electrode EP2 of diode chip for backlight unit, but is not limited to the knot
Structure.First terminal electrode EP1 and second terminal electrode EP2 can also pass through the element forming face S1 shape in semiconductor substrate 20
It is constituted at wiring layer again.
In each embodiment illustrated above, show in the first interarea VS1 and the second interarea VS2 for overlooking substrate
When, the diode chip for backlight unit configuration example Chong Die with coil, but it is not limited to this.It is main in the first interarea VS1 and second for overlooking substrate
When the VS2 of face, diode chip for backlight unit can not also be Chong Die with coil.
Finally, the explanation of above-mentioned embodiment is to illustrate in all respects, it is not restrictive content.For this
It can be appropriately deformed and change for the technical staff of field.The scope of the utility model is not above-mentioned embodiment,
But it is indicated by claims.Further, the scope of the utility model includes according to the model being equal with claims
The change of embodiment in enclosing.
Claims (7)
1. a kind of inductor with ESD defencive function, which is characterized in that
The inductor with ESD defencive function has LGA type SMT Inductor and diode chip for backlight unit,
The LGA type SMT Inductor has：Substrate with the first interarea as mounting surface；It is formed in the line of the substrate
Circle；It is formed in first interarea, and the first input and output electrode connecting with the first end of the coil；It is formed in described
One interarea, and the second input and output electrode being connect with the second end of the coil；It is formed in the ground connection electricity of first interarea
Pole；The first connection electrode being connect with the coil；And the second connection electrode being connect with the grounding electrode,
The diode chip for backlight unit has：Semiconductor substrate；It is formed in the semiconductor substrate, and is played as ESD protection device
The diode of function；And the first terminal electrode and Second terminal being connect respectively with the first end and second end of the diode
Electrode,
The diode chip for backlight unit is equipped on the LGA type SMT Inductor,
The first terminal electrode and the second terminal electrode of the diode chip for backlight unit respectively with the LGA type chip inductor
First connection electrode of device is connected with second connection electrode,
When looking down, grounding electrode configuration first input and output electrode and second input and output electrode it
Between.
2. the inductor according to claim 1 with ESD defencive function, which is characterized in that
The substrate has second interarea opposed with first interarea,
First connection electrode and second connection electrode are formed in second interarea,
The diode chip for backlight unit is equipped on second interarea of the substrate.
3. the inductor according to claim 2 with ESD defencive function, which is characterized in that
When overlooking first interarea and second interarea, the diode chip for backlight unit is Chong Die with the coil.
4. the inductor described in any one of claim 1 to 3 with ESD defencive function, which is characterized in that
The substrate is the laminated body of multiple insulated base material layers.
5. the inductor described in any one of claim 1 to 3 with ESD defencive function, which is characterized in that
The capacitive component possessed by the inductance ingredient of the LGA type SMT Inductor and the diode constitutes low-pass filtering
Device.
6. the inductor described in any one of claim 1 to 3 with ESD defencive function, which is characterized in that
The inductor with ESD defencive function has the first interlayer connection conductor for being formed in the substrate,
First connection electrode is connect via first interlayer connection conductor with the coil.
7. the inductor described in any one of claim 1 to 3 with ESD defencive function, which is characterized in that
The substrate is magnetic body component,
The inductor with ESD defencive function has the conductor introduction for the outer surface for being formed in the substrate,
The grounding electrode is connect via the conductor introduction with second connection electrode.
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| JP2016-133867 | 2016-07-06 | ||
| JP2016133867 | 2016-07-06 | ||
| PCT/JP2017/023067 WO2018008422A1 (en) | 2016-07-06 | 2017-06-22 | Inductor with esd protection function |
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| JP6536768B1 (en) | 2018-04-16 | 2019-07-03 | 株式会社村田製作所 | ESD protection element |
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| JP4910513B2 (en) * | 2005-07-25 | 2012-04-04 | Ｔｄｋ株式会社 | Surge absorption circuit |
| JP4829890B2 (en) * | 2005-09-07 | 2011-12-07 | パナソニック株式会社 | Composite electronic components |
| JP5310768B2 (en) * | 2011-03-30 | 2013-10-09 | Ｔｄｋ株式会社 | Multilayer bandpass filter |
| JP6097921B2 (en) * | 2012-07-13 | 2017-03-22 | パナソニックＩｐマネジメント株式会社 | Multilayer inductor |
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