CN208093592U - A kind of filter chip encapsulating structure - Google Patents
A kind of filter chip encapsulating structure Download PDFInfo
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- CN208093592U CN208093592U CN201820677459.9U CN201820677459U CN208093592U CN 208093592 U CN208093592 U CN 208093592U CN 201820677459 U CN201820677459 U CN 201820677459U CN 208093592 U CN208093592 U CN 208093592U
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- 238000001914 filtration Methods 0.000 claims abstract description 139
- 239000002184 metal Substances 0.000 claims abstract description 131
- 229910052751 metal Inorganic materials 0.000 claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 238000002161 passivation Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 27
- 238000004806 packaging method and process Methods 0.000 abstract description 21
- 239000010410 layer Substances 0.000 description 61
- 238000000034 method Methods 0.000 description 31
- 238000010586 diagram Methods 0.000 description 10
- 239000000047 product Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 however Polymers 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
The utility model discloses a kind of filter chip encapsulating structures.The chip-packaging structure includes the filtering wafer and substrate of contraposition fitting；Filtering on filtering wafer is interdigital in the space surrounded by filtering wafer, metal pad and substrate；Substrate is equipped with multiple the first grooves through substrate, and the first groove exposes the metal pad of corresponding filtering wafer；Surface of the substrate far from filtering wafer side is equipped with metal layer, is electrically connected with metal pad by the first groove；Surface of the metal layer far from filtering wafer side is equipped with soldermask layer, and the second groove of soldermask layer is provided through on soldermask layer, is provided with solder ball in the second groove, solder ball is electrically connected with metal pattern.Filter chip encapsulating structure provided by the utility model realizes effective encapsulation of filtering wafer; the phase can protect the filtering inter-digital area filtered on wafer before packaging; so that it is reduced the probability of damage and pollution, ensure that the product yield of the filtering wafer of encapsulation.
Description
Technical field
The utility model embodiment is related to technical field of manufacturing semiconductors more particularly to a kind of filter chip encapsulation knot
Structure.
Background technology
Crystal wafer chip dimension encapsulation (Wafer Level Chip Size Packaging, WLCSP) technology is to wafer
It cuts to obtain the technology of single finished product chip again after being packaged test, the chip size after encapsulation and bare die are completely the same.It is brilliant
Circle level chip scale package technology has thoroughly overturned conventional package, and it is increasingly light to microelectronic product, small, short, thin to have complied with market
Change the requirement with low priceization.
For the wafer level packaging of filter chip, generally use will filter wafer and be welded by metal pad and substrate, filter
Wave wafer carries out cutting gradation, after forming single filtering chip, then is closed with substrate by resin protecting frame or resin plate,
To which filtering chip is encapsulated.Wherein, the interdigital final step in encapsulation step of filtering in filtering chip is just protected
Shield, i.e., in encapsulation process, the interdigital possibility that can exist by dust pollution, damage etc. of filtering, and then influence the filter after encapsulation
The function of wave chip.
Utility model content
The utility model provides a kind of filter chip encapsulating structure, can will filter wafer in the first time of encapsulation
On filtering inter-digital area protected, make its reduce damage and pollution probability.
In a first aspect, the utility model embodiment provides a kind of filter chip encapsulating structure, including align fitting
Filter wafer and substrate；
It is provided with multiple metal pads on the filtering wafer and multiple filtering are interdigital, the multiple metal pad and described
Multiple filtering are interdigital to be respectively positioned on the filtering wafer close to the surface of the substrate, the metal pad of the filtering wafer and
The substrate offsets, it is described filtering wafer on the filtering it is interdigital in by the filtering wafer, the metal pad with
And in the space that surrounds of the substrate；
The substrate is equipped with multiple the first grooves through the substrate, and first groove exposes corresponding institute
State the metal pad of filtering wafer；
Surface of the substrate far from the filtering wafer side is equipped with metal layer, the metal layer include it is multiple each other
The metal pattern of insulation, the metal that the metal pattern passes through first groove and the corresponding filtering wafer
Pad is electrically connected；
Surface of the metal layer far from the filtering wafer side is equipped with soldermask layer, and the soldermask layer covers the gold
Belong to layer and the substrate, the second groove of the soldermask layer is provided through on the soldermask layer, second groove exposes institute
State metal pattern；
Solder ball is provided in second groove, the solder ball is electrically connected with the metal pattern.
Optionally, the substrate is provided with multiple protrusions on the surface of the filtering wafer；
The protrusion and the metal pad of the filtering wafer offset.
Optionally, described raised and interdigital more than the filtering with the sum of its thickness of the metal pad to offset
Thickness.
Optionally, the substrate is glass substrate or silicon substrate.
Optionally, further include passivation layer；
The passivation layer is set between the substrate and the metal layer；
First groove runs through the substrate and the passivation layer.
Optionally, the material of the passivation layer is silicon nitride.
The utility model embodiment makes the interdigital place of filtering on filtering wafer by aligning the filtering wafer and substrate that are bonded
In the space surrounded by filtering wafer, metal pad and substrate, while passing through the first groove and substrate table through substrate
Metal layer on face is electrically connected with the metal pad of corresponding filtering wafer；Again on the soldermask layer by covering metal layer
The solder ball being arranged in second groove, is electrically connected with metal pattern；To protect the filtering of filtering chip is interdigital, and it is same
When the metal pad of filtering chip is drawn.The encapsulating structure for the filter chip that the utility model embodiment provides realizes filter
Effective encapsulation of wave wafer can at the first time protect the filtering inter-digital area filtered on wafer in encapsulation process,
It avoids filtering the interdigital exposed time in encapsulation process, so that it is reduced the probability of damage and pollution, ensure that the filtering of encapsulation
The product yield of wafer.
Description of the drawings
Fig. 1 is a kind of encapsulating structure schematic diagram of filter chip in the prior art；
Fig. 2 is a kind of filter chip encapsulating structure schematic diagram that the utility model embodiment provides；
Fig. 3 is another filter chip encapsulating structure schematic diagram that the utility model embodiment one provides；
Fig. 4 is the schematic diagram of the encapsulating structure for another filter chip that the utility model embodiment one provides；
Fig. 5 is a kind of flow chart for filter chip packaging method that the utility model embodiment provides；
Fig. 6 is the flow chart for another filter chip packaging method that the utility model embodiment provides；
Fig. 7 is the flow chart for another filter chip packaging method that the utility model embodiment provides；
Fig. 8 is the semi-finished product structure schematic diagram of Fig. 4 median filter chip-packaging structures.
Specific implementation mode
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, it illustrates only for ease of description, in attached drawing and the relevant part of the utility model rather than entire infrastructure.
Fig. 1 is a kind of encapsulating structure schematic diagram of filter chip in the prior art, with reference to figure 1, filter in the prior art
Wave device chip-packaging structure includes：Align the filtering wafer 11 and substrate 12 of fitting, wherein filtering wafer 11 faces substrate 12 1
Side is provided with multiple metal pads 111 and filtering interdigital 112, and substrate 12 is provided with pad 120 in face of 11 side of filtering wafer, filters
The pad 120 on metal pad 111 and substrate 12 on wave wafer 11 carries out wielding neck by solder ball 100 and forms fitting,
Protecting frame 10 and 12 seal bond of substrate, form encapsulated space protecting filter chip.In addition to this, filtering in the prior art
Device chip-packaging structure there may also be more variant, such as substrate 12 uses groove type, filtering wafer 11 to be integrally located at substrate 12
Groove in, similarly, by solder ball 100 carry out wielding neck, protecting frame 10 be a slab construction, by the substrate of groove type
12 lids, which close, forms encapsulated space.It is above-mentioned that the step of forming protecting frame 10, is carried out in the final step of encapsulation in the prior art,
Phase before packaging welds solder ball 100 on the metal pad 111 of filtering wafer 11, and by the pad 120 on substrate 12
During being welded with solder ball 100, what all can be damaged and pollute in the presence of the filtering interdigital 112 on filtering wafer 11 can
Can, so as to influence the function of the chip after encapsulation, reduce product yield.
Fig. 2 is a kind of filter chip encapsulating structure schematic diagram that the utility model embodiment provides, with reference to figure 2, the filter
Wave device chip-packaging structure includes the filtering wafer 11 and substrate 12 of contraposition fitting；It is provided with multiple metal weldings on filtering wafer 11
Disk 111 and multiple filtering interdigital 112, multiple metal pads 111 and multiple filtering interdigital 112 are respectively positioned on filtering wafer 11 close to base
The metal pad 111 on the surface of plate 12, filtering wafer 11 offsets with substrate 12, filters at the filtering interdigital 112 on wafer 11
In the space surrounded by filtering wafer 11, metal pad 111 and substrate 12；Substrate 12 is equipped with multiple through substrate 12
First groove 121, the first groove 121 expose the metal pad 111 of corresponding filtering wafer 11；Substrate 12 is brilliant far from filtering
The surface of 11 sides of circle is equipped with metal layer 13, and metal layer 13 includes multiple metal patterns insulated from each other, and metal pattern passes through
First groove 121 is electrically connected with the metal pad 111 of corresponding filtering wafer 11；Metal layer 13 is far from filtering wafer 11 1
The surface of side is equipped with soldermask layer 14, and soldermask layer 14 covers metal layer 13 and substrate 12, is provided through on soldermask layer 14 anti-welding
Second groove 141 of layer 14, the second groove 141 expose metal pattern；It is provided with solder ball 15, solder ball in second groove 141
15 are electrically connected with metal pattern.
Wherein, it in order to draw the metal pad 1 filtered in wafer 11, needs to realize passing through for interlayer by metal layer 13
Wear, also, due in filtering wafer 11 arrangement of metal pad 111 be not fixed, and in order to by each metal pad 111 by with
The single corresponding metal wire 13 of metal pad 111 is drawn, that is, the metal pattern of metal wire 13 is provided with, to ensure solder ball 15
Electrical connection corresponding with single metal pad 111.The conductive metallic materials such as titanium, copper, gold can be selected in metal layer material, pass through magnetic control
The metal coatings techniques such as sputtering are formed.
The encapsulation process of the filter chip is introduced below with reference to Fig. 2, the step of the encapsulation of the filter chip
Include mainly：Substrate 12 is bonded with the filtering contraposition of wafer 11, the metal pad 111 of filtering wafer 11 is made to offset with substrate 12
It holds, filters the filtering interdigital 112 on wafer 11 in the space surrounded by filtering wafer 11, metal pad 111 and substrate 12
In；Then multiple the first grooves 121 through substrate 12 are formed in substrate 12 successively；In substrate 12 far from 11 side of filtering wafer
Surface on form metal layer 13, be formed with soldermask layer 14 on surface of the metal layer 13 far from filtering wafer 11 side, it is anti-welding
Solder ball 15 is formed on second groove 141 of layer 14, is realized finally by solder ball 15 and filters the metal pad on wafer 11
111 electrical connection；
The utility model embodiment one provide filter chip encapsulating structure, by align fitting filtering wafer and
Substrate keeps the filtering on filtering wafer interdigital in the space surrounded by filtering wafer, metal pad and substrate, leads to simultaneously
The metal layer on the first groove and substrate surface of substrate is crossed, is electrically connected with the metal pad of corresponding filtering wafer
It connects；The solder ball being arranged in the second groove on the soldermask layer by covering metal layer again, is electrically connected with metal pattern；To filter
The filtering of wave chip is interdigital to be protected, and simultaneously draws the metal pad of filtering chip.The utility model embodiment provides
Filter chip encapsulating structure realize filtering wafer effective encapsulation, in encapsulation process, can at the first time will filter
Filtering inter-digital area on wave wafer is protected, and avoids filtering the interdigital exposed time in encapsulation process, it is made to reduce damage
The probability of wound and pollution ensure that the product yield of the filtering wafer of encapsulation.
It should be noted that through substrate 12 the first groove 121 its object is to which metal pad 111 is exposed,
Purpose through the second groove 141 of soldermask layer 14 is to expose metal wire 13, so that the gold in metal wire 13
Metal patterns realize the electrical connection of metal pad 111 and solder ball 15, and the first groove 121 and the second groove 141 can pass through cutting
The modes such as grooving processes, etch process or the making of laser boring technique are formed.In addition, the shape of the first groove and the second groove is not
It is limited to trapezoidal, can is triangle, U-shaped etc., those skilled in the art can form the first groove according to actual conditions or technique
With the second groove.
Fig. 3 is that another filter chip encapsulating structure schematic diagram that the utility model embodiment provides can with reference to figure 3
Selection of land further includes in the filter chip encapsulating structure：Substrate 12 is provided with multiple protrusions on the surface of filtering wafer 11
16；Protrusion 16 and the metal pad 111 of filtering wafer 11 offset.According to actual conditions by the way that certain thickness is arranged on the substrate 12
The protrusion 16 of degree increases the height between filtering wafer 11 and substrate 12, to form the space for accommodating filtering interdigital 112.
Currently, the height of the metal pad 111 filtered on wafer 11 and filtering interdigital 112 in filter chip is not solid
Set pattern rule, it is understood that there may be filtering interdigital 112 be higher than metal pad 111 the case where, so need pass through substrate 12 close to filtering
The mode of protrusion 16 is set on the surface of wafer 11, to ensure that substrate 12 and filtering wafer 11 and metal pad 111 form space,
It is interdigital to surround filtering.
Optionally, protrusion 16 is more than the thickness of filtering interdigital 112 with the sum of the thickness of metal pad 111 to offset with it
Degree.The thickness range of choice of protrusion 16 can be 5-50 μm.
Fig. 4 is the schematic diagram of the encapsulating structure for another filter chip that the utility model embodiment provides, reference chart
4, optionally, substrate 12 is glass substrate or silicon substrate.
Wherein, when substrate 12 is silicon substrate, to avoid being electrically connected between metal layer 13 and silicon substrate 12, with reference to figure 3, the filter
It can also include passivation layer 17 in the encapsulating structure of wave device chip；Passivation layer 17 is set between substrate 12 and metal layer 13；The
One groove 121 runs through substrate 12 and passivation layer 17.In addition, passivation layer 17 is also used as metal layer 13 and glass substrate 12 is bonded
Middle layer ensures the adhesiving effect of metal layer 13.
Wherein, the material of passivation layer 17 can select organic material such as epoxy resin, however, epoxy resin etc. is organic
Optionally, passivation layer 17 can also select inorganic material such as silicon nitride for material and filter,
Need the depth of the first groove 121 illustrated that can be designed according to actual conditions, such as in order to which guarantee fund belongs to
The contact area bigger of metal pattern and metal pad 111 in line 13 so that the signal transmission of filter chip is more preferable, can be with
First groove 121 is set across substrate 12 and deeply to the bottom and bottom in metal pad 111, making the first groove 121
Side wall has exposed metal pad 111, to increase the contact area of metal wire 13 and metal pad 111.Further, also
Can multiple sub- grooves be set in the bottom of the first groove, each sub- groove leaks out the metal pad of corresponding filtering wafer,
To ensure that the metal layer formed in the first bottom portion of groove can cover each sub- groove, to the contact area with metal pad
Increase.Its neutron groove can be formed by techniques such as laser borings.
The utility model embodiment additionally provides a kind of filter chip packaging method.Fig. 5 is the utility model embodiment
A kind of flow chart of the filter chip packaging method provided, with reference to figure 5, which includes：
S210, filtering wafer and substrate are provided, multiple metal pads is provided on filtering wafer and multiple filtering are interdigital；
S220, substrate is bonded with filtering Wafer alignment, so that the metal pad of filtering wafer is offseted with substrate, filtering is brilliant
Filtering on circle is interdigital in the space surrounded by filtering wafer, metal pad and substrate；
S230, multiple the first grooves through substrate are formed in substrate, the first groove exposes corresponding filtering wafer
Metal pad；
S240, metal layer is formed on surface of the substrate far from filtering wafer side, metal layer includes multiple insulated from each other
Metal pattern, metal pattern is electrically connected by the first groove with the metal pad of corresponding filtering wafer；
S250, be formed with soldermask layer on surface of the metal layer far from filtering wafer side, soldermask layer cover metal layer and
Substrate, the second groove of soldermask layer is provided through on soldermask layer, and the second groove exposes metal pattern；
S260, solder ball is formed in the second groove, solder ball is electrically connected with metal pattern.
The utility model embodiment makes the interdigital place of filtering on filtering wafer by aligning the filtering wafer and substrate that are bonded
In the space surrounded by filtering wafer, metal pad and substrate, while passing through the first groove and substrate table through substrate
Metal layer on face is electrically connected with the metal pad of corresponding filtering wafer；Again on the soldermask layer by covering metal layer
The solder ball being arranged in second groove, is electrically connected with metal pattern；To protect the filtering of filtering chip is interdigital, and it is same
When the metal pad of filtering chip is drawn.The encapsulating structure for the filter chip that the utility model embodiment provides and encapsulation side
Method realizes effective encapsulation of filtering wafer, in encapsulation process, will can filter the interdigital area of filtering on wafer at the first time
Domain is protected, and avoids filtering the interdigital exposed time in encapsulation process, so that it is reduced the probability of damage and pollution, be ensure that
The product yield of the filtering wafer of encapsulation.
Fig. 6 is the flow chart for another filter chip packaging method that the utility model embodiment provides.The filter
Chip packaging method is corresponding with the filter chip encapsulating structure in Fig. 3, is sealed with the filter chip provided described in Fig. 2
Dress method, which differs only in, improves step 210 and step 220.With reference to figure 3 and Fig. 6, optionally, in step 210, carry
For filtering wafer 11 and substrate 12, wherein substrate 12 is provided with multiple raised 16 on the surface of filtering wafer 11；This time step
Rapid 220 include：
The metal pad for filtering wafer is corresponded with the protrusion of substrate and is bonded, so that the metal of protrusion and filtering wafer
Pad offsets, and the filtering filtered on wafer is interdigital in the space surrounded by filtering wafer, metal pad, protrusion and substrate
In.
Fig. 7 is the flow chart for another filter chip packaging method that the utility model embodiment provides, the encapsulation side
Relative to packaging method shown in fig. 6, it differs only in and is improved step 230 method；Fig. 8 in Fig. 7 using providing
During filter chip packaging method makes filter chip encapsulating structure as shown in Figure 4, after completing step S232, the filter
Structural schematic diagram when wave device chip packaging structure semi-finished product state, the packaging method are sealed with the filter chip in Fig. 4 and Fig. 8
Assembling structure is corresponding.With reference to figure 4, Fig. 7 and Fig. 8, wherein step 230 forms multiple the first grooves through substrate in substrate,
First groove exposes the metal pad of corresponding filtering wafer, including：
S231, multiple third grooves 122 through substrate 12 are formed in substrate 12, third groove 122 exposes corresponding
Protrusion 16；
S232, passivation layer 17 is formed on the surface of filtering wafer in substrate, passivation layer 17 covers substrate 12 and the
The bottom surface of three grooves 122 and side wall；
S233, the first groove 121 is formed on the passivation layer, the first groove 121 is located in third groove 122, the first groove
121 run through passivation layer 17, and expose the metal pad 111 of corresponding filtering wafer 11.
Optionally, the first groove 121 makes and to be formed using cutting grooving processes, etch process or laser boring technique.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various bright
Aobvious variation is readjusted and is substituted without departing from the scope of protection of the utility model.Therefore, although passing through above example
The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from
Can also include other more equivalent embodiments in the case that the utility model is conceived, and the scope of the utility model is by appended
Right determine.
Claims (6)
1. a kind of filter chip encapsulating structure, which is characterized in that include the filtering wafer and substrate of contraposition fitting；
It is provided with multiple metal pads on the filtering wafer and multiple filtering are interdigital, the multiple metal pad and the multiple
Filter it is interdigital be respectively positioned on the filtering wafer close to the surface of the substrate, the metal pad of the filtering wafer with it is described
Substrate offsets, and the filtering on the filtering wafer is interdigital in by the filtering wafer, the metal pad and institute
It states in the space that substrate surrounds；
The substrate is equipped with multiple the first grooves through the substrate, and first groove exposes the corresponding filter
The metal pad of wave wafer；
Surface of the substrate far from the filtering wafer side is equipped with metal layer, and the metal layer includes multiple insulated from each other
Metal pattern, the metal pad that the metal pattern passes through first groove and the corresponding filtering wafer
Electrical connection；
Surface of the metal layer far from the filtering wafer side is equipped with soldermask layer, and the soldermask layer covers the metal layer
With the substrate, the second groove of the soldermask layer is provided through on the soldermask layer, second groove exposes the gold
Metal patterns；
Solder ball is provided in second groove, the solder ball is electrically connected with the metal pattern.
2. filter chip encapsulating structure according to claim 1, which is characterized in that the substrate is close to filtering crystalline substance
Multiple protrusions are provided on round surface；
The protrusion and the metal pad of the filtering wafer offset.
3. filter chip encapsulating structure according to claim 2, which is characterized in that the protrusion offsets with it
The sum of thickness of the metal pad is more than the interdigital thickness of the filtering.
4. filter chip encapsulating structure according to claim 1, which is characterized in that the substrate is glass substrate or silicon
Substrate.
5. filter chip encapsulating structure according to claim 4, which is characterized in that further include passivation layer；
The passivation layer is set between the substrate and the metal layer；
First groove runs through the substrate and the passivation layer.
6. filter chip encapsulating structure according to claim 5, which is characterized in that the material of the passivation layer is nitridation
Silicon.
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| CN201820677459.9U CN208093592U (en) | 2018-05-08 | 2018-05-08 | A kind of filter chip encapsulating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108389957A (en) * | 2018-05-08 | 2018-08-10 | 苏州科阳光电科技有限公司 | A kind of filter chip encapsulating structure and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389957A (en) * | 2018-05-08 | 2018-08-10 | 苏州科阳光电科技有限公司 | A kind of filter chip encapsulating structure and packaging method |
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Address after: 215143, Jiangsu, Suzhou province Xiangcheng District Lake Industrial Park Road, No. 568 square bridge Patentee after: Suzhou Keyang Semiconductor Co., Ltd Address before: 215143, Jiangsu, Suzhou province Xiangcheng District Lake Industrial Park Road, No. 568 square bridge Patentee before: SUZHOU KEYANG PHOTOELECTRIC TECHNOLOGY CO., LTD. |
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