CN207986671U - A kind of all standing getter wafer scale electronic component - Google Patents
A kind of all standing getter wafer scale electronic component Download PDFInfo
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- CN207986671U CN207986671U CN201721421917.4U CN201721421917U CN207986671U CN 207986671 U CN207986671 U CN 207986671U CN 201721421917 U CN201721421917 U CN 201721421917U CN 207986671 U CN207986671 U CN 207986671U
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Abstract
A kind of all standing getter wafer scale electronic component, basic Component units include following several parts：Device wafers (1), cavity wafer (2)；The two makes two wafer bondings be integrally formed by bonding technology, and bonding technology is realized by bonded layer (5), is additionally provided with cavity (3) between；Cavity wafer (2) inner surface in cavity (3) or it is covered with one layer of active coating i.e. gettering layer structure (4) on device wafers (1) surface；The ingredient of gettering layer structure (4) is one or a combination set of following several elements and its oxide：Ti, Co, Zr, Fe；The thickness range of gettering layer structure (4) is in 500nm 2um.The application and preparation physical gas-phase deposition of gettering layer structure (4)：Sputtering or evaporation or combination.The utility model structure and technique are relatively easy, at low cost.Technique effect is excellent；It is with expected more huge economic value and social value.
Description
Technical field
The utility model is related to vacuum wafer-level packagings and the structure design and application technology of relative electronic components to lead
Domain specifically provides a kind of all standing getter wafer scale electronic component.
Background technology
Vacuum Package is an essential link for MEMS, and MEMS device usually has mobilizable portion
Part needs to allow these sensing units and movable member to ensure these sensitive movable members and sensing unit mechanical performance
It is operated in vacuum environment, needs the movable member that will be machined and sensing unit Vacuum Package that can connect with the external world thus
Shell inside, here it is Vacuum Packages, however if carry out Vacuum Package one by one, from cost, time for all
MEMS high-volume is not met, low cost requires, so wafer-level packaging is imperative, it is entire brilliant that primary encapsulation can encapsulate completion
All devices on circle.In addition to the vacuum degree of Vacuum Package is kept to remain unchanged, reliable a condition of high vacuum degree cavity is obtained,
Getter is essential.By getter layer and air molecule react and suction-operated, keep vacuum in vacuum cavity
Degree remains unchanged.Improve performance and the service life of MEMS device.
People are highly desirable to obtain a kind of all standing getter wafer scale electronic component that technique effect is excellent.
Utility model content
The purpose of this utility model is to provide a kind of all standing getter wafer scale electronic component that technique effect is excellent.
The utility model provides a kind of all standing getter wafer scale electronic component, and basic Component units include following
Several parts：Device wafers 1, cavity wafer 2；The two is integrally formed by bonding technology bonding, and bonding technology passes through bonding
Layer 5 is realized；It is additionally provided with cavity 3 therebetween in device wafers 1, cavity wafer 2；It is characterized in that：In cavity 3
2 inner surface of cavity wafer or all it is covered with one layer of active coating i.e. gettering layer structure 4 on 1 surface of device wafers；
The ingredient of gettering layer structure 4 one or a combination set of includes and is not limited to following several elements and its oxide：Ti, Co, Zr,
Fe；The thickness range of gettering layer structure 4 is in 500nm-2um；
Following physical vapour deposition (PVD) (PVD) technique of the application and preparation of gettering layer structure 4：Sputtering or the group of evaporation or the two
It closes.
Evaporation refer to the process of semiconductor devices production in vacuum evaporation, so-called vacuum evaporation be exactly set material to be plated and
By plated substrate in vacuum chamber, material to be plated is heated using resistance heating or electron beam, is allowed to evaporate or distil, and fly and arrive quilt
The technique of plated substrate surface aggregation film forming.Film forming can reduce the atom of evaporation material, molecule in flight substrate under vacuum
Collision between gas molecule in the process, the chemistry for reducing the bioactive molecule in gas and evaporating material and evaporation source material key are anti-
It answers and (such as aoxidizes), and reduce gas molecule in film forming procedure and enter in film the amount for becoming impurity, to improve film
Consistency, purity, deposition rate and the adhesive force with substrate.Sputtering refers to using high energy particle (typically just by electric field acceleration
Ion) the bombardment surface of solids, the atom of the surface of solids, molecule exchange kinetic energy with incident high energy particle after from surface of solids splashing
Out the phenomenon that, is known as sputtering.The atom (or atomic group) sputtered out has certain energy, they can be with redeposited solidifying
Gather and form film on solid substrate surface, referred to as sputtered film.Usually gas ionization, cation are generated using gas discharge
The high velocity bombardment cathode targets under electric field action hit the atom or molecule of cathode targets, fly to plated substrate surface and are deposited into
Film.Sputtering mode generally has d.c. sputtering；Magnetron sputtering；Radio-frequency sputtering；Reactive sputtering etc..
Different devices has different requirements to the vacuum degree (air pressure) of dual cavity or multi-chamber.Described in the utility model
Gettering layer structure 4 is whole cover types, according to the design requirement of different components, can choose whether there is bonding gold in the chamber
Belong to layer 5, for example, dual cavity design in Inertial Measurement Unit device primarily directed to what is designed, Inertial Measurement Unit is by 3 axis gyros
Instrument and 3 axis accelerometers composition, wherein gyroscope part needs condition of high vacuum degree chamber, and accelerometer part does not need high vacuum
Degree, so this patent first deposits the getter layer 4 of all standing, but when depositing bonded layer 5, by bonded layer 5 as resistance
Barrier has blocked the getter layer in high pressure (rough vacuum) chamber so that accelerometer chamber has rough vacuum；In this way
It avoids to remove the getter layer in high pressure chest (rough vacuum) also needing to photoetching process after depositing getter layer.Letter
Change technological process, saved cost, provides yield.
The deposition position of getter layer includes but not limited to 2 internal layer surface of cavity wafer, and different devices is needed not
Same position, such as：Inertial Measurement Unit is mainly the deposited inside in cavity wafer 2, and pressure sensor (Fig. 2), infrared biography
Sensor (Fig. 3) is deposited in non-device wafer segment.
And sealant is not gettering layer structure and sealing ring belongs to likewise, belonging to bonded layer 5.
The vacuum wafer-level packaging electronic component with getter, it is characterised in that：Cavity 3 is specially in cavity crystalline substance
Corrode the single-chamber body of formation either dual chamber or Multicarity on circle 2；Each cavity 3 can be with when for dual chamber or Multicarity
For same depth cavity or different depth cavity；Caustic solution is using wet etching, dry etching either the two combined method
Etching.
Silicon Wafer, due to different crystal orientations corrosion resistance difference, can form different etching pattern in KOH or TMAH solution.
The MEMS cavity wafer finished products formed after corrosion, the requirement covered before gettering layer is that surface is substantially smooth, through over cleaning.
Wet etching mainly utilizes the anisotropic properties of silicon, and being that a kind of body silicon of common manufacture micro mechanical structure is micro- adds
Work technology, because it realizes relatively easy, cost also relative moderate.Anisotropy refers to corrosion of all alkaline etchings to silicon
All it is anisotropic, etch-rate depends on crystal orientation.Most fast erosional surface is typically (100), and (111) rate of corrosion is most
Low, decomposition rate is limited to Chemical Kinetics.For isotropic etchant, decompose by reacted with semiconductor from
The diffusion rate of son determines.Anisotropy can be clearly viewed by surface profile.If silicon wafer surface (100) is by etching
Mask patterning, erosional surface are limited by (111), and the shape of final eroded crater is a V-shaped slot or an inverted pyramid.Corrosion
Side is aligned with (110), unrelated with the original shape of etching mask.
Due to anisotropy, the structure size on (100) silicon is always limited by minimum dimension.<100>With<111>It
Between angle be 54.74 °.Therefore, its minimum widith of dell depth A of an etching is 2A/tan (54.74 °).It uses (110)
Silicon Wafer may can improve the low depth-width ratio of wet etching.Since (111) face to provide constraints is perpendicular to (110) face.Cause
This, the angle between the side wall and surface of etch pit is 90 °.Most common corrosive agent be ethylene diamine pyrocatechol (EDP), hydrazine,
KOH solution and tetramethylammonium hydroxide (TMAH).The above two are hypertoxic, are needed in processing procedure especially careful.In contrast, after
The two is more favourable.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is one of the following or a combination thereof：Metal eutectic bonding, sun
Pole be bonded, high temperature bonding, low-temperature bonding, metal solder bonds, glass paste bonding, bond wire be gold, chromium, aluminium, tin, indium,
One of aluminium, germanium etc. or combinations thereof.
Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber, is inhaled for being covered in low vacuum chamber
Gas oxidant layer 4, rough vacuum in holding chamber body.
Bonding technology refers to utilizing pressure, temperature, electrostatic or chemical method so that the skill that two wafers are bonded together
Art.Wafer scale bonding techniques refer to by chemically and physically acting on that silicon chip and silicon chip, silicon chip and glass or other materials is close
The method that ground combines.Wafer bonding is often combined with surface silicon processing and silicon bulk fabrication, is used in the processing technology of MEMS
In.Common wafer scale bonding techniques include anode linkage, metal bonding and glass solder sintering etc..Anode linkage technology can be with
Glass any binder is not had into together with metal, alloy or bonding semiconductor.This bonding temperature is low, bonded interface is firm
Gu, long-time stability it is good.Metal bonding technology can generally be divided into two classes：Non-melt type diffusion method and self-planarization are (molten
Change) eutectic reaction.When with both technologies, it can be suitble to according to desirable technical parameter and requirement, respectively selection
Metal system.
In all standing getter wafer scale electronic component, cavity 3 is specially pair for forming the corrosion of cavity wafer 2
Cavity；Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；The cavity wafer 2 of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of inside cavity first, 4 outside of gettering layer structure is additionally provided with bonded layer 5.Low pressure chamber is used
In arrangement MEMS gyroscope, high pressure chest is for arranging mems accelerometer；Dedicated Inertial Measurement Unit is collectively formed.
In all standing getter wafer scale electronic component, using the method or two of grinding chemical machinery polishing
The method of person's combination, deep top of chamber is removed, and forms opening 12, exposes wire bond pads 13.Different height is used herein
Cavity design, it is during thinned that solder tray local is exposed.(this way saves technological process, and common practices needs first to subtract
It is thin, then pad portion is opened by way of cutting, we use the cavity design of different height, will during thinned
Pad exposes, and pad is centainly to need to expose, and needs to do technique again on pad.)
The utility model uses reduction process while reducing integral device thickness, by using the two-chamber of different depth
Chamber opening is exposed bonding region metal by room or multiple chamber design to realize, and other products are cut together by increasing
Technique, it would be desirable to which the chamber roof of opening is opened.In contrast, we (thinned die is necessary work while thinned die
Skill), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, dicing lane etching
The problem of.Improve the yield rate of product.This patent can be with simplification of flowsheet, and reducing photoetching number, (photoetching process is micro- electricity
Most crucial technique in sub- technique, and most complicated technique generally indicate complex process degree with photoetching number, reduce together
Photoetching means to reduce many techniques, gluing, and front baking exposes, development, post bake, and etching is removed photoresist, cleaning etc.), simplify work
Cost (including Master Cost, machine loss, labour cost etc.) is decreased while skill flow, reducing flow can also accelerate
Product manufacturing speed so that monthly output increases, and monthly income also increases, in electronics market with keen competition, cost
It is particularly important.
It is additionally provided with key between device wafers 1 and cavity wafer 2 in all standing getter wafer scale electronic component
Close layer 5, concrete application bond wire or welding compound；Bond wire is one of the following or a combination thereof：Gold, chromium, aluminium,
Tin, indium, aluminium, germanium, copper；Use low-temperature bonding；Welding compound is specially photoetching welding compound；Cavity wafer 2 is specifically infrared fileter；
Its material is the combination of silicon, germanium or the two.
The vacuum packaging method of all standing getter wafer scale electronic component described in the utility model：
The basic Component units of all standing getter wafer scale electronic component include following several parts：Device wafers
1, cavity wafer 2；The two fixing assembling is integrated, and is additionally provided with cavity 3 between；It is characterized in that：In cavity 3
2 surface of cavity wafer cover one layer of active coating, that is, gettering layer structure 4；The ingredient of gettering layer structure 4 is following several
One or a combination set of kind element：Ti, Co, Zr, Fe；The thickness range of gettering layer structure 4 is in 500nm-2um.
The vacuum packaging method of all standing getter wafer scale electronic component, it is characterised in that：Gettering layer structure 4
The following physical vapour deposition (PVD) PVD process of application and preparation：Sputtering or evaporation or combination；Specifically electron beam is utilized to heat
Or electron beam deflects bombardment target under magnetic field, by evaporation of metal or pounds, is attached to crystal column surface.Sputtering is steamed
Hair belongs to physical vapour deposition (PVD) PVD methods.
Cavity 3 is specially that cavity wafer 2 is corroded to the single-chamber body formed either dual chamber or Multicarity.For cavity 3
Caustic solution specifically use wet etching, dry etching either both combined method etching.Silicon Wafer is molten in KOH or TMAH
Liquid can form different etching pattern since different crystal orientations corrosion resistance is different.The MEMS cavitys wafer formed after corrosion at
Product, the requirement covered before gettering layer is that surface is substantially smooth, through over cleaning.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is metal eutectic bonding, anode linkage, high temperature bonding, low temperature
Bonding, metal solder bonds, glass paste bonding one of them or combinations thereof, bond wire include and be not limited to it is following it is several it
One or combinations thereof：Gold, chromium, aluminium, tin, indium, aluminium, germanium.Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber,
For covering getter layer 4 in low vacuum chamber, rough vacuum in holding chamber body.
In all standing getter wafer scale electronic component, cavity 3 is preferably pair for forming the corrosion of cavity wafer 2
Cavity；Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；The cavity wafer 2 of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of inside cavity first, 4 outside of gettering layer structure is additionally provided with anti-reflection layer 5.
The vacuum packaging method of all standing getter wafer scale electronic component requires as follows：Device wafers 1, cavity are brilliant
Circle 2；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer 5；In device wafers 1, cavity
Wafer 2 is additionally provided with therebetween cavity 3；2 inner surface of cavity wafer in cavity 3 or in 1 surface of device wafers whole
It is covered with one layer of active coating i.e. gettering layer structure 4；By being thinned or chemical machinery polishing technique removes deep top of chamber
Fall, opening 12 is formed, to exposing outside the partial structurtes of wire bond pads 13；Wire bond pads 13 pass through lead key closing process
Plain conductor is drawn, is connected with other component.
The method that the utility model can use grinding opens the cavity with gettering layer, this is that skill is thinned using wafer
Art opens cavity 3, exposes inside cavity 3, what this was mainly determined by device architecture.
The general the relevant technologies that can apply the utility model for requiring device to have Vacuum Package.Such as：MEMS inertia
Sensor, infrared sensor, absolute pressure pressure sensor, FBAR etc..
The additional explanation of the utility model related content is described as follows：
The application of gettering layer can reduce sluggishness.Appropriate packaged type can reduce temperature drift and time drift.
One of innovation key of the utility model is：Gettering layer structure (4) be continuous layer structure (that is, completely
Cover getter layer) and uninterrupted structure.Other packaging methods with getter layer are all with figure in the prior art
The getter layer of shape.The utility model simplifies getter deposit technique from technique, reduces one of photoetching process, cost drop
It is low.In two-chamber encapsulation, since different chamber requires different air pressures (vacuum degree), the utility model is used to be bonded in deposited metal
While layer, the getter layer in the chamber for not needing high vacuum is hidden using metal bonding layer as barrier layer (bonding metal layer)
It blocks, realizes hyperbar (rough vacuum), can equally reduce by one layer of photolithography plate, reduce photoetching, etch process flow, simplify
Technological process reduces production cost；We use reduction process while reducing integral device thickness, by using different depths
Chamber opening is exposed bonding region metal by the dual cavity or multiple chamber design of degree to realize, and other products are all to pass through increase
One of cutting technique, it would be desirable to which the chamber roof of opening is opened.In contrast, our (thinned dies while thinned die
It is necessary technique), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, is drawn
The problem of film channel etches.
Description of the drawings
Below in conjunction with the accompanying drawings and embodiment is described in further detail the utility model：
Fig. 1 is typical dual cavity difference vacuum degree wafer-level vacuum packaged electronic component structure simplified schematic diagram；
Fig. 2 is absolute pressure pressure sensor (all standing getter wafer-level vacuum packaged) structure schematic diagram；
Fig. 3 is infrared sensor (all standing getter wafer-level vacuum packaged) structure schematic diagram；
Fig. 4 is different depth two-chamber all standing getter wafer-level vacuum packaged structure schematic diagram；
Fig. 5 is different depth two-chamber all standing getter wafer-level vacuum packaged structure schematic diagram.
Specific implementation mode
Reference numeral meaning is as follows：Device wafers 1, cavity wafer 2, cavity 3, gettering layer structure 4, anti-reflection layer 5, sealing ring
6。
In Fig. 4, pad has to expose, and using different depth chamber design, while doing chip thinning, will weld
The chamber of disk top is opened, and technological process is reduced, and is opened with the mode cut avoiding after, and it is winged chipping, offset, chip occur
Go out, the defects of blue film is cut through, can effectively improve yield rate.Fig. 5 is different depth two-chamber all standing getter wafer scale vacuum
Encapsulating structure simplified schematic diagram opens high chamber, exposed pad by reduction process.
Embodiment 1
A kind of all standing getter wafer scale electronic component, basic Component units include following several parts：Device is brilliant
Circle 1, cavity wafer 2；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer 5；In device
Wafer 1, cavity wafer 2 are additionally provided with therebetween cavity 3；2 inner surface of cavity wafer in cavity 3 or in device wafers
1 surface is all covered with one layer of active coating i.e. gettering layer structure 4；The ingredient of gettering layer structure 4 includes and is not limited to
The combination of following several elements and its oxide：Ti, Co, Zr, Fe；The thickness range of gettering layer structure 4 is in 500nm-2um；
Following physical vapour deposition (PVD) (PVD) technique of the application and preparation of gettering layer structure 4：Sputtering, the combination evaporated.Evaporation
Refer to the process of the vacuum evaporation in semiconductor devices production, so-called vacuum evaporation is exactly to set material to be plated and by plated substrate in true
In empty room, material to be plated is heated using resistance heating or electron beam, is allowed to evaporate or distil, and it is solidifying to plated substrate surface to fly
It is polymerized to the technique of film.Film forming can reduce the evaporation atom of material, molecule during flight substrate and gas under vacuum
Intermolecular collision, the bioactive molecule and evaporation material and the chemical reaction of evaporation source material key reduced in gas (such as aoxidize
Deng), and reduce gas molecule in film forming procedure and enter in film the amount for becoming impurity, to improve the consistency, pure of film
Degree, deposition rate and the adhesive force with substrate.Sputtering refers to high energy particle (being typically the cation by electric field acceleration) bombardment
The surface of solids, the atom of the surface of solids, molecule show after exchanging kinetic energy with incident high energy particle from what the surface of solids sputtered
As being known as sputtering.The atom (or atomic group) sputtered out has certain energy, they redeposited can condense upon solid
Film, referred to as sputtered film are formed on substrate surface.Gas ionization usually is generated using gas discharge, cation is made in electric field
With lower high velocity bombardment cathode targets, the atom or molecule of cathode targets are hit, plated substrate surface is flown to and is deposited into film.Sputtering
Mode generally has d.c. sputtering；Magnetron sputtering；Radio-frequency sputtering；Reactive sputtering etc..
Different devices has different requirements to the vacuum degree (air pressure) of dual cavity or multi-chamber.Described in the utility model
Gettering layer structure 4 is whole cover types, according to the design requirement of different components, can choose whether there is bonding gold in the chamber
Belong to layer 5, for example, dual cavity design in Inertial Measurement Unit device primarily directed to what is designed, Inertial Measurement Unit is by 3 axis gyros
Instrument and 3 axis accelerometers composition, wherein gyroscope part needs condition of high vacuum degree chamber, and accelerometer part does not need high vacuum
Degree, so this patent first deposits the getter layer 4 of all standing, but when depositing bonded layer 5, by bonded layer 5 as resistance
Barrier has blocked the getter layer in high pressure (rough vacuum) chamber so that accelerometer chamber has rough vacuum；In this way
It avoids to remove the getter layer in high pressure chest (rough vacuum) also needing to photoetching process after depositing getter layer.Letter
Change technological process, saved cost, provides yield.
The deposition position of getter layer includes but not limited to 2 internal layer surface of cavity wafer, and different devices is needed not
Same position, such as：Inertial Measurement Unit is mainly the deposited inside in cavity wafer 2, and pressure sensor (Fig. 2), infrared biography
Sensor (Fig. 3) is deposited in non-device wafer segment.
And sealant is not gettering layer structure and sealing ring belongs to likewise, belonging to bonded layer 5.
Cavity 3 is specially to corrode the single-chamber body of formation either dual chamber or Multicarity on cavity wafer 2；When for two-chamber
Each cavity 3 can be same depth cavity or different depth cavity when body or Multicarity；Caustic solution using wet etching,
Both dry etchings combined method etches.
Silicon Wafer, due to different crystal orientations corrosion resistance difference, can form different etching pattern in KOH or TMAH solution.
The MEMS cavity wafer finished products formed after corrosion, the requirement covered before gettering layer is that surface is substantially smooth, through over cleaning.
Wet etching mainly utilizes the anisotropic properties of silicon, and being that a kind of body silicon of common manufacture micro mechanical structure is micro- adds
Work technology, because it realizes relatively easy, cost also relative moderate.Anisotropy refers to corrosion of all alkaline etchings to silicon
All it is anisotropic, etch-rate depends on crystal orientation.Most fast erosional surface is typically (100), and (111) rate of corrosion is most
Low, decomposition rate is limited to Chemical Kinetics.For isotropic etchant, decompose by reacted with semiconductor from
The diffusion rate of son determines.Anisotropy can be clearly viewed by surface profile.If silicon wafer surface (100) is by etching
Mask patterning, erosional surface are limited by (111), and the shape of final eroded crater is a V-shaped slot or an inverted pyramid.Corrosion
Side is aligned with (110), unrelated with the original shape of etching mask.
Due to anisotropy, the structure size on (100) silicon is always limited by minimum dimension.<100>With<111>It
Between angle be 54.74 °.Therefore, its minimum widith of dell depth A of an etching is 2A/tan (54.74 °).It uses (110)
Silicon Wafer may can improve the low depth-width ratio of wet etching.Since (111) face to provide constraints is perpendicular to (110) face.Cause
This, the angle between the side wall and surface of etch pit is 90 °.Most common corrosive agent be ethylene diamine pyrocatechol (EDP), hydrazine,
KOH solution and tetramethylammonium hydroxide (TMAH).The above two are hypertoxic, are needed in processing procedure especially careful.In contrast, after
The two is more favourable.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is one of the following or a combination thereof：Metal eutectic bonding, sun
Pole be bonded, high temperature bonding, low-temperature bonding, metal solder bonds, glass paste bonding, bond wire be gold, chromium, aluminium, tin, indium,
Two combination at least within such as aluminium, germanium.
Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber, is inhaled for being covered in low vacuum chamber
Gas oxidant layer 4, rough vacuum in holding chamber body.
Bonding technology refers to utilizing pressure, temperature, electrostatic or chemical method so that the skill that two wafers are bonded together
Art.Wafer scale bonding techniques refer to by chemically and physically acting on that silicon chip and silicon chip, silicon chip and glass or other materials is close
The method that ground combines.Wafer bonding is often combined with surface silicon processing and silicon bulk fabrication, is used in the processing technology of MEMS
In.Common wafer scale bonding techniques include anode linkage, metal bonding and glass solder sintering etc..Anode linkage technology can be with
Glass any binder is not had into together with metal, alloy or bonding semiconductor.This bonding temperature is low, bonded interface is firm
Gu, long-time stability it is good.Metal bonding technology can generally be divided into two classes：Non-melt type diffusion method and self-planarization are (molten
Change) eutectic reaction.When with both technologies, it can be suitble to according to desirable technical parameter and requirement, respectively selection
Metal system.
In all standing getter wafer scale electronic component, cavity 3 is specially pair for forming the corrosion of cavity wafer 2
Cavity；Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；The cavity wafer 2 of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of inside cavity first, 4 outside of gettering layer structure is additionally provided with bonded layer 5.Low pressure chamber is used
In arrangement MEMS gyroscope, high pressure chest is for arranging mems accelerometer；Dedicated Inertial Measurement Unit is collectively formed.
In all standing getter wafer scale electronic component, using the method or two of grinding chemical machinery polishing
The method of person's combination, deep top of chamber is removed, and forms opening 12, exposes wire bond pads 13.Different height is used herein
Cavity design, it is during thinned that solder tray local is exposed.(this way saves technological process, and common practices needs first to subtract
It is thin, then pad portion is opened by way of cutting, we use the cavity design of different height, will during thinned
Pad exposes, and pad is centainly to need to expose, and needs to do technique again on pad.)
The present embodiment uses reduction process while reducing integral device thickness, by using the dual cavity of different depth
Or multiple chamber design, chamber opening is exposed into bonding region metal to realize, and other products are all by increasing by one of cutter
Skill, it would be desirable to which the chamber roof of opening is opened.In contrast, (thinned die is necessary to the present embodiment while thinned die
Technique), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, dicing lane is carved
The problem of erosion.Improve the yield rate of product.This patent can be with simplification of flowsheet, and reducing photoetching number, (photoetching process is micro-
Most crucial technique in electronic technology, and most complicated technique generally indicate complex process degree with photoetching number, reduce one
Road photoetching means to reduce many techniques, gluing, and front baking exposes, development, post bake, and etching is removed photoresist, cleaning etc.), it simplifies
Cost (including Master Cost, machine loss, labour cost etc.) is decreased while technological process, reducing flow can also add
Fast product manufacturing speed so that monthly output increases, and monthly income also increases, in electronics market with keen competition, at
This is particularly important.
It is additionally provided with key between device wafers 1 and cavity wafer 2 in all standing getter wafer scale electronic component
Close layer 5, concrete application bond wire or welding compound；Bond wire is one of the following or a combination thereof：Gold, chromium, aluminium,
Tin, indium, aluminium, germanium, copper；Use low-temperature bonding；Welding compound is specially photoetching welding compound；Cavity wafer 2 is specifically infrared fileter；
Its material is the combination of silicon, germanium or the two.
The vacuum packaging method of all standing getter wafer scale electronic component as described above.
The basic Component units of all standing getter wafer scale electronic component include following several parts：Device wafers
1, cavity wafer 2；The two fixing assembling is integrated, and is additionally provided with cavity 3 between；Cavity wafer 2 in cavity 3
Surface covers one layer of active coating, that is, gettering layer structure 4；The ingredient of gettering layer structure 4 is certain of following several elements
Combination：Ti, Co, Zr, Fe；The thickness range of gettering layer structure 4 is in 500nm-2um.
The following physical vapour deposition (PVD) PVD process of the application and preparation of gettering layer structure 4：Sputtering or the group of evaporation or the two
It closes；It specifically utilizes electron beam heating or electron beam to deflect bombardment target under magnetic field, by evaporation of metal or pounds,
It is attached to crystal column surface.Sputtering, evaporation belong to physical vapour deposition (PVD) PVD methods.
Cavity 3 is specially that cavity wafer 2 is corroded to the single-chamber body formed either dual chamber or Multicarity.For cavity 3
Caustic solution specifically use wet etching, dry etching either both combined method etching.Silicon Wafer is molten in KOH or TMAH
Liquid can form different etching pattern since different crystal orientations corrosion resistance is different.The MEMS cavitys wafer formed after corrosion at
Product, the requirement covered before gettering layer is that surface is substantially smooth, through over cleaning.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is metal eutectic bonding, anode linkage, high temperature bonding, low temperature
Bonding, metal solder bonds, glass paste bonding one of them or combinations thereof, bond wire include and be not limited to it is following it is several it
One or combinations thereof：Gold, chromium, aluminium, tin, indium, aluminium, germanium.Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber,
For covering getter layer 4 in low vacuum chamber, rough vacuum in holding chamber body.
In all standing getter wafer scale electronic component, cavity 3 is the dual chamber for forming the corrosion of cavity wafer 2；
Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；2 inside of cavity wafer of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of cavity first, 4 outside of gettering layer structure is additionally provided with anti-reflection layer 5.
The vacuum packaging method of all standing getter wafer scale electronic component requires as follows：Device wafers 1, cavity are brilliant
Circle 2；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer 5；In device wafers 1, cavity
Wafer 2 is additionally provided with therebetween cavity 3；2 inner surface of cavity wafer in cavity 3 or in 1 surface of device wafers whole
It is covered with one layer of active coating i.e. gettering layer structure 4；By being thinned or chemical machinery polishing technique removes deep top of chamber
Fall, opening 12 is formed, to exposing outside the partial structurtes of wire bond pads 13；Wire bond pads 13 pass through lead key closing process
Plain conductor is drawn, is connected with other component.
The method that the present embodiment can use grinding opens the cavity with gettering layer, this is to utilize wafer thinning technique,
Cavity 3 is opened, is exposed inside cavity 3, what this was mainly determined by device architecture.
The general the relevant technologies that can apply the utility model for requiring device to have Vacuum Package.Such as：MEMS inertia
Sensor, infrared sensor, absolute pressure pressure sensor, FBAR etc..
The additional explanation of the present embodiment related content is described as follows：
The application of gettering layer can reduce sluggishness.Appropriate packaged type can reduce temperature drift and time drift.
One of innovation key of the present embodiment is：Gettering layer structure 4 is continuous layer structure and (that is, suction is completely covered
Gas oxidant layer) and uninterrupted structure.Other packaging methods with getter layer are all with the suction with figure in the prior art
Gas oxidant layer.The present embodiment simplifies getter deposit technique from technique, reduces one of photoetching process, cost reduction.Double
In chamber encapsulation, since different chamber requires different air pressures (vacuum degree), the present embodiment to use while deposited metal bonded layer,
The getter layer in the chamber for not needing high vacuum is sheltered from using metal bonding layer as barrier layer (bonding metal layer), is realized
Hyperbar (rough vacuum) can equally reduce by one layer of photolithography plate, reduce photoetching, etch process flow, simplification of flowsheet,
Reduce production cost；Using reduction process while reducing integral device thickness, by using different depth dual cavity or
Multiple chamber design, by chamber opening come realize expose bonding region metal, and other products be all by increasing by one of cutting technique,
The chamber roof being open will be needed to open.In contrast, (thinned die is necessary work to the present embodiment while thinned die
Skill), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, dicing lane etching
The problem of.
Embodiment 2
A kind of all standing getter wafer scale electronic component, basic Component units include following several parts：Device is brilliant
Circle 1, cavity wafer 2；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer 5；In device
Wafer 1, cavity wafer 2 are additionally provided with therebetween cavity 3；It is characterized in that：2 inner surface of cavity wafer in cavity 3 or
It is all to be covered with one layer of active coating i.e. gettering layer structure 4 on 1 surface of device wafers；The ingredient of gettering layer structure 4
Including and one of be not limited to following several elements：Ti, Co, Zr, Fe；The thickness range of gettering layer structure 4 is in 500nm-2um；It inhales
Following physical vapour deposition (PVD) (PVD) technique of the application and preparation of gas-bearing formation structure 4：Sputtering or evaporation.
The deposition position of getter layer includes but not limited to 2 internal layer surface of cavity wafer, and different devices is needed not
Same position, such as：Inertial Measurement Unit is mainly the deposited inside in cavity wafer 2, and pressure sensor (Fig. 2), infrared biography
Sensor (Fig. 3) is deposited in non-device wafer segment.
And sealant is not gettering layer structure and sealing ring belongs to likewise, belonging to bonded layer 5.
Cavity 3 is specially to corrode the single-chamber body of formation either dual chamber or Multicarity on cavity wafer 2；When for two-chamber
Each cavity 3 can be same depth cavity or different depth cavity when body or Multicarity；Caustic solution using wet etching,
Dry etching either the two combined method etching.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is following one of several：Metal eutectic bonding, anode linkage,
High temperature is bonded, low-temperature bonding, metal solder bonds, and glass paste bonding, bond wire is gold, chromium, aluminium, tin, indium, aluminium, germanium etc.
One of them.
Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber, in low vacuum
Getter layer 4 is covered in chamber, rough vacuum in holding chamber body.
Bonding technology refers to utilizing pressure, temperature, electrostatic or chemical method so that the skill that two wafers are bonded together
Art.Wafer scale bonding techniques refer to by chemically and physically acting on that silicon chip and silicon chip, silicon chip and glass or other materials is close
The method that ground combines.Wafer bonding is often combined with surface silicon processing and silicon bulk fabrication, is used in the processing technology of MEMS
In.Common wafer scale bonding techniques include anode linkage, metal bonding and glass solder sintering etc..Anode linkage technology can be with
Glass any binder is not had into together with metal, alloy or bonding semiconductor.This bonding temperature is low, bonded interface is firm
Gu, long-time stability it is good.Metal bonding technology can generally be divided into two classes：Non-melt type diffusion method and self-planarization are (molten
Change) eutectic reaction.When with both technologies, it can be suitble to according to desirable technical parameter and requirement, respectively selection
Metal system.
In all standing getter wafer scale electronic component, cavity 3 is specially pair for forming the corrosion of cavity wafer 2
Cavity；Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；The cavity wafer 2 of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of inside cavity first, 4 outside of gettering layer structure is additionally provided with bonded layer 5.Low pressure chamber is used
In arrangement MEMS gyroscope, high pressure chest is for arranging mems accelerometer；Dedicated Inertial Measurement Unit is collectively formed.
In all standing getter wafer scale electronic component, using the method or two of grinding chemical machinery polishing
The method of person's combination, deep top of chamber is removed, and forms opening 12, exposes wire bond pads 13.Different height is used herein
Cavity design, it is during thinned that solder tray local is exposed.(this way saves technological process, and common practices needs first to subtract
It is thin, then pad portion is opened by way of cutting, we use the cavity design of different height, will during thinned
Pad exposes, and pad is centainly to need to expose, and needs to do technique again on pad.)
The present embodiment uses reduction process while reducing integral device thickness, by using the dual cavity of different depth
Or multiple chamber design, chamber opening is exposed into bonding region metal to realize, and other products are all by increasing by one of cutter
Skill, it would be desirable to which the chamber roof of opening is opened.In contrast, (thinned die is necessary to the present embodiment while thinned die
Technique), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, dicing lane is carved
The problem of erosion.Improve the yield rate of product.The present embodiment can be with simplification of flowsheet, and reducing photoetching number, (photoetching process is
Most crucial technique in microelectronic technique, and most complicated technique generally indicate complex process degree with photoetching number, reduce
One of photoetching means to reduce many techniques, gluing, and front baking exposes, development, post bake, and etching is removed photoresist, cleaning etc.), simplify
Cost (including Master Cost, machine loss, labour cost etc.) is decreased while technological process, reducing flow can also
Accelerate product manufacturing speed so that monthly output increases, and monthly income also increases, in electronics market with keen competition,
Cost is particularly important.
It is additionally provided with key between device wafers 1 and cavity wafer 2 in all standing getter wafer scale electronic component
Close layer 5, concrete application bond wire or welding compound；Bond wire is one of the following or a combination thereof：Gold, chromium, aluminium,
Tin, indium, aluminium, germanium, copper；Use low-temperature bonding；Welding compound is specially photoetching welding compound；Cavity wafer 2 is specifically infrared fileter；
Its material is the combination of silicon, germanium or the two.
The present embodiment further relates to the vacuum packaging method of all standing getter wafer scale electronic component, all standing air-breathing
The basic Component units of agent wafer scale electronic component include following several parts：Device wafers 1, cavity wafer 2；The two is fixed
Assembly is integrated, and is additionally provided with cavity 3 between；It is characterized in that：2 surface of cavity wafer covering one in cavity 3
Active coating, that is, gettering layer the structure 4 of layer；The ingredient of gettering layer structure 4 is one or a combination set of following several elements：Ti,
Co, Zr, Fe；The thickness range of gettering layer structure 4 is in 500nm-2um.
The following physical vapour deposition (PVD) PVD process of the application and preparation of gettering layer structure 4：Sputtering or evaporation；Specifically utilize
Electron beam heats or electron beam deflects bombardment target under magnetic field, by evaporation of metal or pounds, is attached to wafer table
Face.Sputtering, evaporation belong to physical vapour deposition (PVD) PVD methods.
Cavity 3 is specially that cavity wafer 2 is corroded to the single-chamber body formed either dual chamber or Multicarity.For cavity 3
Caustic solution specifically use wet etching, dry etching either both combined method etching.Silicon Wafer is molten in KOH or TMAH
Liquid can form different etching pattern since different crystal orientations corrosion resistance is different.The MEMS cavitys wafer formed after corrosion at
Product, the requirement covered before gettering layer is that surface is substantially smooth, through over cleaning.
The gettering layer structure 4 of 2 inner surface of cavity wafer or the covering of 1 surface of device wafers in cavity 3, cavity wafer 2
There are bonded layers 5 between device wafers 1；Its bonding technology is metal eutectic bonding, anode linkage, high temperature bonding, low temperature
Bonding, metal solder bonds, glass paste bonding one of them, bond wire includes and is not limited to following one of several：Gold,
Chromium, aluminium, tin, indium, aluminium, germanium.Bonded layer 5 is also used as barrier layer, in the design of two-chamber or multi-chamber, in low vacuum chamber
Getter layer 4 is covered in room, rough vacuum in holding chamber body.
In all standing getter wafer scale electronic component, cavity 3 is preferably pair for forming the corrosion of cavity wafer 2
Cavity；Wherein：It is provided with gettering layer structure 4 on 2 inside cavity of cavity wafer, 3 inner wall of low pressure chamber；The cavity wafer 2 of high pressure chest
Gettering layer structure 4 is provided on 3 inner wall of inside cavity first, 4 outside of gettering layer structure is additionally provided with anti-reflection layer 5.
The vacuum packaging method of all standing getter wafer scale electronic component requires as follows：Device wafers 1, cavity are brilliant
Circle 2；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer 5；In device wafers 1, cavity
Wafer 2 is additionally provided with therebetween cavity 3；2 inner surface of cavity wafer in cavity 3 or in 1 surface of device wafers whole
It is covered with one layer of active coating i.e. gettering layer structure 4；By being thinned or chemical machinery polishing technique removes deep top of chamber
Fall, opening 12 is formed, to exposing outside the partial structurtes of wire bond pads 13；Wire bond pads 13 pass through lead key closing process
Plain conductor is drawn, is connected with other component.
The method that the present embodiment can use grinding opens the cavity with gettering layer, this is to utilize wafer
Thinning technique opens cavity 3, exposes inside cavity 3, what this was mainly determined by device architecture.
The general the relevant technologies that can apply the utility model for requiring device to have Vacuum Package.Such as：MEMS inertia
Sensor, infrared sensor, absolute pressure pressure sensor, FBAR etc..
The additional explanation of the present embodiment related content is described as follows：
The application of gettering layer can reduce sluggishness.Appropriate packaged type can reduce temperature drift and time drift.
One of innovation key of the present embodiment is：Gettering layer structure (4) is continuous layer structure and (that is, is completely covered
Getter layer) and uninterrupted structure.Other packaging methods with getter layer are all with figure in the prior art
Getter layer.The present embodiment simplifies getter deposit technique from technique, reduces one of photoetching process, cost reduction.
In two-chamber encapsulation, since different chamber requires different air pressures (vacuum degree), the present embodiment to use in the same of deposited metal bonded layer
When, the getter layer in the chamber for not needing high vacuum is sheltered from using metal bonding layer as barrier layer (bonding metal layer),
It realizes hyperbar (rough vacuum), can equally reduce by one layer of photolithography plate, reduce photoetching, etch process flow, simplify technique
Flow reduces production cost；We use reduction process while reducing integral device thickness, by using different depth
Chamber opening is exposed bonding region metal by dual cavity or multiple chamber design to realize, and other products are all by increasing together
Cutting technique, it would be desirable to which the chamber roof of opening is opened.In contrast, we (thinned die is must while thinned die
Want technique), just bonding region metal is exposed, reduces technological process, avoids some chippings in cutting process, dicing lane
The problem of etching.
Claims (5)
1. a kind of all standing getter wafer scale electronic component, basic Component units include following several parts：Device wafers
(1), cavity wafer (2)；The two is integrally formed by bonding technology bonding, and bonding technology is realized by bonded layer (5)；
Device wafers (1), cavity wafer (2) are additionally provided with therebetween cavity (3)；It is characterized in that：Cavity in cavity (3) is brilliant
Justify (2) inner surface or is all covered with one layer of active coating i.e. gettering layer structure (4) on device wafers (1) surface；
The thickness range of gettering layer structure (4) is in 500nm-2um.
2. according to all standing getter wafer scale electronic component described in claim 1, it is characterised in that：Cavity (3) specially exists
Corrode the single-chamber body of formation either dual chamber or Multicarity on cavity wafer (2)；It is each when for dual chamber or Multicarity
Cavity (3) is same depth cavity or different depth cavity.
3. according to all standing getter wafer scale electronic component described in claims 1 or 2, it is characterised in that：Chamber in cavity (3)
Body wafer (2) inner surface or the gettering layer structure (4) of device wafers (1) surface covering, cavity wafer (2) and device wafers
(1) there are bonded layer (5) between.
4. according to all standing getter wafer scale electronic component described in claim 3, it is characterised in that：The all standing getter
In wafer scale electronic component, cavity (3) is specially the dual chamber for forming cavity wafer (2) corrosion；Wherein：The cavity of low pressure chamber
On the inside of wafer (2) gettering layer structure (4) is provided on cavity (3) inner wall；On the inside of the cavity wafer (2) of high pressure chest in cavity (3)
Gettering layer structure (4) is provided on wall first, bonded layer (5) is additionally provided on the outside of gettering layer structure (4).
5. according to all standing getter wafer scale electronic component described in claim 4, it is characterised in that：The all standing getter
In wafer scale electronic component, deep top of chamber forms opening (12), exposes wire bond pads (13)；Using the chamber of different height
Body designs, and exposes pad during thinned；
It is additionally provided with key between device wafers (1) and cavity wafer (2) in all standing getter wafer scale electronic component
Close layer (5)；Cavity wafer (2) is specifically infrared fileter.
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