CN207895834U - A kind of display panel and display device - Google Patents
A kind of display panel and display device Download PDFInfo
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- CN207895834U CN207895834U CN201820284922.3U CN201820284922U CN207895834U CN 207895834 U CN207895834 U CN 207895834U CN 201820284922 U CN201820284922 U CN 201820284922U CN 207895834 U CN207895834 U CN 207895834U
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- power supply
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Abstract
The utility model embodiment provides a kind of display panel and display device, is related to display technology field, to solve the problems, such as by the picture brightness unevenness caused by data voltage signal delay write-in.Display panel includes：Multiple data lines positioned at viewing area；Control switch correspondingly positioned at the driving chip of non-display area and with multiple data lines；Wherein, the first end of data line is connected with driving chip, and the second end of data line is connected with the second end of corresponding control switch, and the first end for controlling switch is connected with power supply signal line, and the control terminal for controlling switch is connected with driving chip.Above-mentioned display panel shows for realizing picture.
Description
【Technical field】
The utility model is related to display technology field more particularly to a kind of display panel and display devices.
【Background technology】
Currently, with the development of display technology, pixel density (Pixels Per Inch, abbreviation of the user to display panel
PPI requirement) is also higher and higher.
In order to drive more pixel light emissions, more grid lines and data line need to be just set in display panel.When grid line and
When the quantity of data line increases, on the one hand, the parasitic capacitance between trace resistances and cabling just will increase, on the other hand,
In the display time of each frame, distributing to the sweep time of each grid line will reduce, that is, sweeping in each grid line
It retouches in the time, the time of data voltage signal write-in data line will reduce.
In general, data voltage signal is written after driving chip output data voltage, on data line can exist centainly
Delay.For the display panel of high pixel density, due to being influenced by larger trace resistances and parasitic capacitance, number
It is just unable to fully in a short time according to voltage signal in write-in data line, and then the brightness of pixel is caused to deviate its standard value, gone out
The problem of picture brightness unevenness shown by existing display panel.
【Utility model content】
In view of this, the utility model embodiment provides a kind of display panel and display device, to solve by data
The problem of picture brightness unevenness caused by voltage signal delay write-in.
On the one hand, the utility model embodiment provides a kind of display panel, and the display panel includes：
Multiple data lines positioned at viewing area；
Switch is controlled correspondingly positioned at the driving chip of non-display area and with a plurality of data line；
Wherein, the first end of the data line is connected with the driving chip, the second end of the data line with it is corresponding
The second end of control switch is connected, and the first end of the control switch is connected with power supply signal line, the control of the control switch
End is connected with the driving chip.
On the other hand, the utility model embodiment provides a kind of display device, and the display device includes above-mentioned display
Panel.
A technical solution in above-mentioned technical proposal has the advantages that：
Compared with prior art, in the present embodiment, based on the connection between data line, control switch and power supply signal line
Relationship can be shortened on data line by carrying out both end power supplying to data line in the first sub-period of each display time interval
The whole write time of voltage signal ensures that the voltage signal on data line is fully written within a short period of time, makes sub-pixel all
Can under the driving for the first voltage signal that driving chip is exported normal luminous, avoid the occurrence of the problem of picture brightness unevenness.
Therefore, the technical solution provided using the present embodiment ensures the electricity on data line in the display time interval that can be grown when shorter
Pressure signal is fully written, to preferably be suitable for the display device of high pixel density.
【Description of the drawings】
It, below will be to required use in embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the utility model, right
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings
Its attached drawing.
Fig. 1 is the structural schematic diagram for the display panel that the utility model embodiment is provided；
Fig. 2 is the signal timing diagram of the driving method for the display panel that the utility model embodiment is provided；
Fig. 3 is another structural schematic diagram for the display panel that the utility model embodiment is provided；
Fig. 4 is another structural schematic diagram for the display panel that the utility model embodiment is provided；
Fig. 5 is the yet another construction schematic diagram for the display panel that the utility model embodiment is provided.
【Specific implementation mode】
In order to be better understood from the technical solution of the utility model, the utility model embodiment is carried out below in conjunction with the accompanying drawings
Detailed description.
It will be appreciated that the described embodiments are only a part of the embodiments of the utility model, rather than whole implementation
Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The all other embodiment obtained, shall fall within the protection scope of the present invention.
The term used in the utility model embodiment is the purpose only merely for description specific embodiment, and is not intended to
Limit the utility model.The utility model embodiment and the "an" of singulative used in the attached claims,
" described " and "the" are also intended to including most forms, unless context clearly shows that other meanings.
The utility model embodiment provides a kind of display panel, as shown in Figure 1, the display panel includes being located at viewing area
Data line 3 in 1, the driving chip 4 in non-display area 2 and with multiple data lines 3 correspondingly control switch 5.
Wherein, the first end of multiple data lines 3 is connected with driving chip 4, the second end of data line 3 and the of corresponding control switch 5
Two ends are connected, and the first end of control switch 5 is connected with power supply signal line 6, and the control terminal of control switch 5 is connected with driving chip 4.
It is understood that during the driving of display panel, the drive cycle of a frame includes multiple display time intervals, root
According to the brightness of the picture shown needed for display panel, in different display time intervals, driving chip 4 exports different voltage letters
Number, voltage signal is transmitted to via data line 3 in corresponding sub-pixel, to control the light that sub-pixel sends out different brightness.
In general, in a upper display time interval, driving chip output size is the voltage signal of V1', voltage letter
Number write-in data line, through in data line transfer to corresponding sub-pixel.In next display time interval, driving chip output size
It is influenced by trace resistances and parasitic capacitance in the display time interval for the voltage signal of V2', voltage signal on data line
Size slowly change from V1' to V2'.But for the display panel of high pixel density, each display time interval
Duration is shorter, if differing larger between V1' and V2', on data line voltage signal grown when shorter in can not be changed to V2', i.e.,
There is the problem of data-signal is unable to fully write-in.
And in the present embodiment, by adding control switch 5 and power supply signal line 6 in display panel, it is based on data
Connection relation between line 3, control switch 5 and power supply signal line 6 can carry out both end power supplying, to accelerate data to data line 3
The write time of voltage signal on line 3.Specifically, each display time interval includes the first sub-period and the second sub-period, each
In first sub-period of display time interval, driving chip 4 exports first voltage signal to the first end of data line 3, that is, driving chip
4 are powered to the first end of data line 3, meanwhile, driving chip 4 controls multiple control switches 5 and is connected, and makes power supply signal line 6
The second voltage signal transmission of output to data line 3 second end, that is, power supply signal line 6 is supplied to the second end of data line 3
Electricity carries out both end power supplying by driving chip 4 and power supply signal line 6 to realize in the first sub-period to data line 3, this
When, the voltage signal that the voltage signal on data line 3 can be written by a upper display time interval quickly be changed to second voltage letter
Number.In the second sub-period, driving chip 4, which controls multiple control switches 5, to be ended, the second voltage for making power supply signal line 6 export
Signal can not be transmitted in data line 3, meanwhile, driving chip 4 continues to provide first voltage signal to data line 3, at this point, data
Voltage signal on line 3 is by second voltage signal intensity to first voltage signal, so that sub-pixel is in first voltage signal
Driving under shine.
Therefore compared with prior art, in the present embodiment, data line 3, control switch 5 and power supply signal are based on
Connection relation between line 6 can by carrying out both end power supplying to data line 3 in the first sub-period of each display time interval
The delay for improving voltage signal to a certain extent is shortened the whole write time of the voltage signal on data line 3, and then is ensured
Voltage signal on data line 3 is fully written within a short period of time, makes sub-pixel can be in the first electricity that driving chip 4 is exported
Normal luminous under the driving of signal is pressed, the problem of picture brightness unevenness is avoided the occurrence of.Therefore, it is provided using the present embodiment aobvious
Show panel, ensures that the voltage signal on data line is fully written in the display time interval that can be grown when shorter, to preferably fit
Display device for high pixel density.
Moreover, it is assumed that being V to the ceiling voltage signal set by driving chip 4max, minimum voltage signal is Vmin.It is setting
When the duration of fixed first sub-period, the duration of the first sub-period can be set as the voltage signal transmitted on data line 3 by
Ceiling voltage signal VmaxIt is reduced to minimum voltage signal VminDuring, by ceiling voltage signal VmaxIt is reduced to medium voltage
Signal VmedDuration used, wherein
With reference to signal timing diagram shown in Fig. 2, the driving method progress to the display panel that the present embodiment is provided
It illustrates.Wherein, the first voltage signal and power supply signal line 6 that signal timing diagram shown in Fig. 2 is exported by driving chip 4
The sequence diagram of the second voltage signal exported.
First, it is assumed that the drive cycle of a frame includes N number of display time interval, and the ceiling voltage letter set by driving chip 4
Number size be vm1, the size of minimum voltage signal is vm2, the size of intermediate voltage signal is vm3。
In first display time interval T1The first sub-period t1Interior, 4 output size of driving chip is v1First voltage letter
Number, meanwhile, driving chip 4 exports conductivity control signal to control switch 5, and control switch 5 is connected, what power supply signal line 6 exported
Size is vm3Second voltage signal via control switch 5 be transmitted in data line 3, the voltage signal on data line 3 is fast by 0V
Speed is changed to vm3；In the second sub-period t2Interior, it is v that driving chip 4, which continues to output size,1First voltage signal, make data line 3
On voltage signal by vm3It is changed to v1。
In second display time interval T2The first sub-period t1Interior, 4 output size of driving chip is v2First voltage letter
Number, meanwhile, driving chip 4 exports conductivity control signal to control switch 5, and control switch 5 is connected, what power supply signal line 6 exported
Size is vm3Second voltage signal via control switch 5 be transmitted in data line 3, the voltage signal on data line 3 is by v1Soon
Speed is changed to vm3；In the second sub-period t2Interior, it is v that driving chip 4, which continues to output size,2First voltage signal, make data line 3
On voltage signal by vm3It is changed to v2。
In third display time interval T3The first sub-period t1Interior, 4 output size of driving chip is v3First voltage letter
Number, meanwhile, driving chip 4 exports conductivity control signal to control switch 5, and control switch 5 is connected, what power supply signal line 6 exported
Size is vm3Second voltage signal via control switch 5 be transmitted in data line 3, the voltage signal on data line 3 is by v2Soon
Speed is changed to vm3；In the second sub-period t2Interior, it is v that driving chip 4, which continues to output size,3First voltage signal, make data line 3
On voltage signal by vm3It is changed to v3。
And so on.
In n-th display time interval TNThe first sub-period t1Interior, 4 output size of driving chip is vNFirst voltage signal,
Meanwhile driving chip 4 exports conductivity control signal to control switch 5, control switch 5 is connected, the size that power supply signal line 6 exports
For vm3Second voltage signal via control switch 5 be transmitted in data line 3, the voltage signal on data line 3 is by vN-1Quickly become
Change to vm3；In the second sub-period t2Interior, it is v that driving chip 4, which continues to output size,NFirst voltage signal, make on data line 3
Voltage signal is by vm3It is changed to vN。
Optionally, referring again to Fig. 1, power supply signal line 6 can be connected with driving chip 4, alternatively, power supply signal line 6
It can be connected with the fixation potential end in display panel.When power supply signal line 6 is connected with driving chip 4,6 institute of power supply signal line
The second voltage signal of output is provided by driving chip 4, when power supply signal line 6 is connected with fixed potential end, power supply signal line 6
The second voltage signal exported is provided by fixing potential end.
As shown in figure 3, when power supply signal line 6 is connected with driving chip 4, power supply signal line 6 specifically may include the first confession
Electricity walk line segment 61, second power supply walk line segment 62 and third power supply walk line segment 63.Wherein, first power supply walk line segment 61 respectively with it is multiple
The first end for controlling switch 5 is connected；Second power supply walk line segment 62 one end with first power supply walk line segment 61 be connected, second power walk
The other end of line segment 62 is connected with driving chip 4；One end of line segment 63 is walked in third power supply and the first line segment 61 of powering is connected, and the
The other end that line segment 63 is walked in three power supplies is connected with driving chip 4.
Compared to the second voltage signal transmission for only being exported driving chip 4 by a cabling to multiple control switches 5,
Using above-mentioned set-up mode, when driving chip 4 exports second voltage signal, second voltage signal is walked by the second power supply simultaneously
Line segment 62 and third power supply, which walk line segment 63 and walk line segment 61 to the first power supply, to be transmitted, so as to shorten second voltage signal transmission to complete
Time used in the control switch 5 in portion, and further reduced decaying of the second voltage signal in transmission process.
Further, referring again to Fig. 3, non-display area 2 includes 21 He of left side non-display area arranged along line direction
Right side non-display area 22.The power supply of line segment 61, second is walked including the first power supply walk line segment 62 and third power supply when power supply signal line 6
When walking line segment 63, the second power supply can be enabled to walk line segment 62 and be located at left side non-display area 21, third power supply walks line segment 63 and is located at the right side
Side non-display area 22.
Compared to enable the second power supply walk line segment 62 and third power supply walk line segment 63 be located in the non-display area of the same side, order
The two is located at left side non-display area 21 and right side non-display area 22, on the one hand can reduce unilateral border width,
On the other hand, additionally it is possible to avoid by second power supply walk line segment 62 and third power supply walk 63 hypotelorism of line segment and generate coupling electricity
Hold, and then avoids coupled capacitor and harmful effect is generated to second voltage signal.
Further, since control switch 5 is connected with the second end of data line 3, in order to reduce control switch 5 and data line
Track lengths between 3 reduce wiring complexity, can will control switch 5 and be arranged in non-display area 2 close to data line 3
The position of second end.Based on this, referring again to Fig. 3, it includes that left side non-display area 21 and right side are non-display that non-display area 2, which removes,
Further include the upside non-display area 23 arranged along column direction and downside non-display area 24 outside region 22, core is driven in setting
When piece 4 and control switch 5, driving chip 4 can be arranged in downside non-display area 24, multiple control switches 5 are arranged
In upside non-display area 23.
As shown in figure 4, the control terminal of control switch 5 can be connected by control signal wire 7 with driving chip 4, signal is controlled
Line 7 is for the conductivity control signal that driving chip 4 exports to be transmitted in corresponding control switch 5.Control signal wire 7 specifically may be used
Including first control walk line segment 71, second control walk line segment 72 and third control walk line segment 73.Wherein, line segment 71 is walked in the first control
It is connected respectively with the control terminal of multiple control switches 5；Second control walk line segment 72 one end with first control walk line segment 71 be connected,
The other end that line segment 72 is walked in second control is connected with driving chip 4；One end and the first control cabling of line segment 73 are walked in third control
Section 71 is connected, and the other end that line segment 73 is walked in third control is connected with driving chip 4.
Compared to the conductivity control signal that driving chip 4 exports only is transmitted to multiple control switches 5 by a cabling,
Using above-mentioned set-up mode, when driving chip 4 exports conductivity control signal, conductivity control signal can pass through the second control simultaneously
System walks line segment 72 and third control walks line segment 73 and walks the transmission of line segment 71 to the first control, so as to shorten conductivity control signal transmission
It is avoided to the time used in whole control switches 5 so that whole control switches 5 simultaneously turns on by controlling switch 5
Turn-on time differ it is larger caused by data line 3 be written first voltage signal duration impact.
Further, referring again to Fig. 4, when control signal wire 7 includes that the control cabling of line segment 71, second is walked in the first control
When line segment 73 is walked in section 72 and third control, the second control can be enabled to walk line segment 72 and be located at left side non-display area 21, third control
It walks line segment 73 and is located at right side non-display area 22.
Compared to enable the second control walk line segment 72 and third control walk line segment 73 be located in the non-display area of the same side, order
The two is located at left side non-display area 21 and right side non-display area 22, on the one hand can reduce unilateral border width,
On the other hand, additionally it is possible to avoid by second control walk line segment 72 and third control walk 73 hypotelorism of line segment and generate coupling electricity
Hold, and then avoids coupled capacitor and harmful effect is generated to conductivity control signal.
Optionally, the concretely thin-film transistor structure of switch 5 is controlled.When it is thin film transistor (TFT) to control switch 5, such as scheme
Shown in 5, the grid of thin film transistor (TFT) is connected with driving chip 4, and the first pole of thin film transistor (TFT) is connected with power supply signal line 6, thin
Second pole of film transistor is connected with the second end of corresponding data line 3.
Specifically, multiple thin film transistor (TFT)s can be P-type TFT, also can be N-type TFT.Work as film
When transistor is P-type TFT, driving chip 4 need to provide low level conductivity control signal to P-type TFT.
When thin film transistor (TFT) is N-type TFT, the conducting that driving chip 4 need to provide high level to thin film transistor (TFT) controls letter
Number.
It is, of course, understood that control switch 5 is that thin film transistor (TFT) is only schematically illustrate, control switch 5 is alternatively
Other constructions of switch, the present embodiment are not especially limited this.
The present embodiment additionally provides a kind of display device, which includes above-mentioned display panel.Wherein, display surface
The concrete structure and driving method of plate are described in detail in the above-described embodiments, and details are not described herein again.Of course, it is possible to
Understand, the display device that the present embodiment is provided can be such as mobile phone, tablet computer, laptop, electric paper book
Or any electronic equipment with display function such as television set.
Since the display device that the present embodiment is provided includes above-mentioned display panel, using the display device, it is based on
Connection relation in display panel between data line, control switch and power supply signal line, can be the first of each display time interval
Both end power supplying is carried out to data line in sub-period, shortens the whole write time of the voltage signal on data line, ensures data
Voltage signal on line is fully written within a short period of time, makes sub-pixel can be in the first voltage signal that driving chip is exported
Driving under normal luminous, avoid the occurrence of the problem of picture brightness unevenness.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Within the spirit and principle of utility model, any modification, equivalent substitution, improvement and etc. done should be included in the utility model
Within the scope of protection.
Claims (10)
1. a kind of display panel, which is characterized in that the display panel includes：
Multiple data lines positioned at viewing area；
Switch is controlled correspondingly positioned at the driving chip of non-display area and with a plurality of data line；
Wherein, the first end of the data line is connected with the driving chip, the second end of the data line and corresponding control
The second end of switch is connected, and the first end of the control switch is connected with power supply signal line, control terminal that the control switchs and
The driving chip is connected.
2. display panel according to claim 1, which is characterized in that the power supply signal line and the driving chip phase
Even.
3. display panel according to claim 2, which is characterized in that the power supply signal line includes the first power supply cabling
Section, the second power supply walk line segment and line segment is walked in third power supply；
Wherein, first power supply walks line segment and is connected respectively with the first end of multiple control switches；Second power supply is walked
One end of line segment walks line segment with first power supply and is connected, and the other end of line segment and the driving chip phase are walked in second power supply
Even；One end that line segment is walked in third power supply walks line segment with first power supply and is connected, and the third is powered the another of line segment
End is connected with the driving chip.
4. display panel according to claim 3, which is characterized in that the non-display area includes along the left side that line direction arranges
Side non-display area and right side non-display area；
The second power supply cabling section is located at the left side non-display area, and it is non-that the third power supply cabling section is located at the right side
Display area.
5. display panel according to claim 1, which is characterized in that the non-display area include arranged along column direction it is upper
Side non-display area and downside non-display area；
Multiple control switches are located at upside non-display area, and the driving chip is located at the downside non-display area
Domain.
6. display panel according to claim 1, which is characterized in that the control terminal of the control switch is by controlling signal
Line is connected with the driving chip, and the control signal wire includes that line segment is walked in the first control, line segment and third control are walked in the second control
System walks line segment；
Wherein, first control walks line segment and is connected respectively with the control terminal of multiple control switches；Second control is walked
One end of line segment walks line segment with first control and is connected, and the other end of line segment and the driving chip phase are walked in second control
Even；The third controls one end of line segment and first control walks line segment and is connected, and the another of line segment is walked in the third control
End is connected with the driving chip.
7. display panel according to claim 6, which is characterized in that the non-display area includes along the left side that line direction arranges
Side non-display area and right side non-display area；
The second control cabling section is located at the left side non-display area, and it is non-that the third control cabling section is located at the right side
Display area.
8. display panel according to claim 1, which is characterized in that the control switch is thin film transistor (TFT)；
The grid of the thin film transistor (TFT) is connected with the driving chip, the first pole of the thin film transistor (TFT) with it is described for telecommunications
Number line is connected, and the second pole of the thin film transistor (TFT) is connected with the second end of corresponding data line.
9. display panel according to claim 8, which is characterized in that multiple thin film transistor (TFT)s are that p-type film is brilliant
Body pipe；Or, multiple thin film transistor (TFT)s are N-type TFT.
10. a kind of display device, which is characterized in that the display device includes as claim 1~9 any one of them is shown
Panel.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820284922.3U CN207895834U (en) | 2018-02-28 | 2018-02-28 | A kind of display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820284922.3U CN207895834U (en) | 2018-02-28 | 2018-02-28 | A kind of display panel and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256099A (en) * | 2018-09-30 | 2019-01-22 | 惠科股份有限公司 | A kind of driving circuit and driving method of display panel |
| WO2022133909A1 (en) * | 2020-12-24 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel and display device |
-
2018
- 2018-02-28 CN CN201820284922.3U patent/CN207895834U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256099A (en) * | 2018-09-30 | 2019-01-22 | 惠科股份有限公司 | A kind of driving circuit and driving method of display panel |
| WO2022133909A1 (en) * | 2020-12-24 | 2022-06-30 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN115004292A (en) * | 2020-12-24 | 2022-09-02 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN115004292B (en) * | 2020-12-24 | 2024-01-30 | 京东方科技集团股份有限公司 | Display panel and display device |
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