CN207867873U - A kind of LED display control assembly using IEEE 802.3BP technologies - Google Patents
A kind of LED display control assembly using IEEE 802.3BP technologies Download PDFInfo
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- CN207867873U CN207867873U CN201820185621.5U CN201820185621U CN207867873U CN 207867873 U CN207867873 U CN 207867873U CN 201820185621 U CN201820185621 U CN 201820185621U CN 207867873 U CN207867873 U CN 207867873U
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Abstract
The utility model is related to a kind of LED display control assemblies using IEEE 802.3BP technologies, sending card and reception including interconnection are blocked, it is loaded with the PHY chip for supporting IEEE 802.3BP standards respectively on the fpga chip of the sending card and reception card, the PHY chip of sending card passes through two pairs of twisted pair line connections with the PHY chip blocked is received.Compared with prior art, using IEEE 802.3BP) technology communicates as transmitting terminal with the PHY layer of receiving terminal, replace original IEEE 802.3ab and Ethernet II, communication is only with two pairs of twisted-pair feeders between the PHY layer of sending card and the PHY layer for receiving card, transmission rate is up to 1000Mbps, PHY layer medium is connected under full duplex transmission state becomes two pairs of twisted pair medias, greatly reduce transmission line line group, solve the problems, such as that connecting line is of high cost with connector simultaneously, line processed is mixed with power supply conducive to signal, improves end product competitiveness.
Description
Technical field
The utility model is related to the hardware structures of LED display control cards, more particularly, to a kind of application IEEE 802.3BP
The LED display control assembly of technology.
Background technology
In practical Large size LED Display System, due to LED display high resolution, Refresh Data frequency is high, needs to transmit
Data volume it is huge, be traditionally used for control LED show reception card in data transmission scheme in, mainly utilize 1000M
PHY layer chip and IEEE 802.3ab (10base-T, 100BASE-TX, 1000BASE-T) and Ethernet II.The program is deposited
In following problem：The problem of Ethernet transmission bandwidth highest 1000Mbps；4 pairs of twisted-pair feeders are needed, line processed is of high cost, tie point
Reliability is low, is especially applied to the water-proof connector of highly reliable outdoor communication.After traditional GIGAPHY layer chips can not solve
Product is held to be needed in the Physical Links Layer of high reliability transport.
Utility model content
The purpose of this utility model is exactly to be provided a kind of using IEEE to overcome the problems of the above-mentioned prior art
The LED display control assembly of 802.3BP technologies.
The purpose of this utility model can be achieved through the following technical solutions：
A kind of LED display control assembly using IEEE 802.3BP technologies, including the sending card of interconnection and connect
Card is received, is loaded with the PHY chip for supporting IEEE 802.3BP standards, hair on the fpga chip that the sending card and reception block respectively
The PHY chip of card feed and the PHY chip for receiving card pass through two pairs of twisted pair line connections.
The reception card is to be cascaded in series for structure, and the PHY chip of adjacent reception card passes through two pairs of twisted pair line connections.
The fpga chip of the sending card is connect by RGMII interfaces or SGMII interfaces with PHY chip.
The fpga chip of the reception card is connect by RGMII interfaces or SGMII interfaces with PHY chip.
The fpga chip of the sending card is equipped with for believing with the DVI picture signals interface and COM orders of external connection
Number interface.
The PHY chip is 88Q2110 chips or 88Q2112 chips.
Compared with prior art, the utility model has the following advantages：
(1) IEEE 802.3BP are applied) technology communicates as transmitting terminal with the PHY layer of receiving terminal, replace original IEEE
It is communicated only with two pairs of twisted-pair feeders between the PHY layer that 802.3ab and Ethernet II, the PHY layer of sending card and reception block and is
Can, transmission rate is up to 1000Mbps, and connection PHY layer medium becomes two pairs of twisted pair medias under full duplex transmission state, significantly
Transmission line line group is reduced, while solving the problems, such as that connecting line is of high cost with connector, line processed is mixed with power supply conducive to signal, is improved
End product competitiveness.
(2) card is received to be cascaded in series for structure, and the PHY chip of adjacent reception card passes through two pairs of twisted pair line connections, connecting line
It is at low cost, simplify it is reliable.
Description of the drawings
Fig. 1 is the structural schematic diagram of the present embodiment control assembly；
Fig. 2 is the structural schematic diagram of the present embodiment sending card；
Fig. 3 is the structural schematic diagram that the present embodiment receives card.
Specific implementation mode
The utility model is described in detail in the following with reference to the drawings and specific embodiments.The present embodiment is with the utility model
Implemented premised on technical solution, gives detailed embodiment and specific operating process, but the guarantor of the utility model
Shield range is not limited to following embodiments.
Embodiment
The present embodiment application IEEE 802.3BP (1000BASE-T1PHY) technologies are as sending card 1 and reception card 2
PHY layer communicates, and replaces original IEEE 802.3ab (10base-T, 100BASE-TX, 1000BASE-T) and Ethernet
II；The present embodiment fpga chip 4 and 3 two kinds of connection types of PHY chip：
1, RGMII interfaces, RGMII mode clock frequencies are ddr125MHz, transmission rate 1Gbps.
2, the communication of SGMII interfaces, FPGA and PHY layer is respectively to receive and dispatch two pairs of differential lines；Clock frequency is 1.25GHz,
Transmission rate is 1Gbps；
The PHY chip 3 of 2 cascades of card is communicated and received between the PHY chip 3 of sending card 1 and the PHY layer for receiving card 2
Between communication only with two pairs of twisted-pair feeders.
As shown in Figure 1, sending card 1 it is onboard support IEEE 802.3BP standards PHY chip 3 (such as： 88Q2110/
88Q2112), sending card 1 is communicated with 2 communication of reception card using two pairs of twisted-pair feeders, is cascaded between reception card 2 and is also used two pairs of multiple twins
Line.Sending card 1 with receive 2 message transmission rates of card up to 1000Mbps, receive card 2 and receive message transmission rate between card 2
Up to 1000Mbps.
As shown in Fig. 2, passing through SGMII RGMII interface phases between the fpga chip 4 of sending card 1 and PHY chip 3
Even, full duplex；PHY chip 3 is connect by two pairs of twisted-pair feeders with external networks, and communications protocol is IEEE 802.3BP；FPGA cores
Piece 4 receives external DVI, COM signal.
Pass through SGMII RGMII interface phases between 2 fpga chip 4 and PHY chip 3 as shown in figure 3, receiving and blocking
Even, full duplex；PHY chip 3 is connect by two pairs of twisted-pair feeders with external networks, and communications protocol is IEEE 802.3BP.
Claims (6)
1. a kind of LED display control assembly using IEEE 802.3BP technologies, including the sending card of interconnection and reception
Card, which is characterized in that be loaded with respectively on the fpga chip of the sending card and reception card and support IEEE 802.3BP standards
PHY chip, the PHY chip of sending card and the PHY chip for receiving card pass through two pairs of twisted pair line connections.
2. a kind of LED display control assembly using IEEE 802.3BP technologies according to claim 1, feature exist
In the reception card is to be cascaded in series for structure, and the PHY chip of adjacent reception card passes through two pairs of twisted pair line connections.
3. a kind of LED display control assembly using IEEE 802.3BP technologies according to claim 1, feature exist
In the fpga chip of the sending card is connect by RGMII interfaces or SGMII interfaces with PHY chip.
4. a kind of LED display control assembly using IEEE 802.3BP technologies according to claim 1, feature exist
In the fpga chip of the reception card is connect by RGMII interfaces or SGMII interfaces with PHY chip.
5. a kind of LED display control assembly using IEEE 802.3BP technologies according to claim 1, feature exist
In the fpga chip of the sending card is equipped with to be connect for the DVI picture signals interface and COM command signals with external connection
Mouthful.
6. a kind of LED display control assembly using IEEE 802.3BP technologies according to claim 1, feature exist
In the PHY chip is 88Q2110 chips or 88Q2112 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820185621.5U CN207867873U (en) | 2018-02-02 | 2018-02-02 | A kind of LED display control assembly using IEEE 802.3BP technologies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820185621.5U CN207867873U (en) | 2018-02-02 | 2018-02-02 | A kind of LED display control assembly using IEEE 802.3BP technologies |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207867873U true CN207867873U (en) | 2018-09-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820185621.5U Active CN207867873U (en) | 2018-02-02 | 2018-02-02 | A kind of LED display control assembly using IEEE 802.3BP technologies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207867873U (en) |
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2018
- 2018-02-02 CN CN201820185621.5U patent/CN207867873U/en active Active
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