CN207690062U - A kind of high reliability solid state disk - Google Patents
A kind of high reliability solid state disk Download PDFInfo
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- CN207690062U CN207690062U CN201721838695.6U CN201721838695U CN207690062U CN 207690062 U CN207690062 U CN 207690062U CN 201721838695 U CN201721838695 U CN 201721838695U CN 207690062 U CN207690062 U CN 207690062U
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Abstract
The utility model is related to technical field of memory, the utility model provides a kind of high reliability solid state disk, including:Front end host communication interface, solid-state hard disk controller and NAND flash storage medium chips, the front end host communication interface is connected with solid-state hard disk controller, the solid-state hard disk controller, it is connected with host communication interface, also it is connected with the NAND Flash memory chips in more than two channels, data transmission, order transmission and the reading to disc, programming, the control for wiping business operation for controlling entire solid state disk disc.Whereby, the utility model is up in some special application scenarios such as environment temperatures to 40 DEG C~100 DEG C for solid state disk, is avoided solid state disk under hot conditions and is entered abnormal patterns, prevents excessive temperature from solid state disk being caused to burn out, cause loss of data.The utility model embedded high-temperature protection circuit in solid-state hard disk controller, enhances the reliability of solid state disk, solves the application technology difficult point of solid state disk at high temperature.
Description
Technical field
The utility model is related to electronic memory technical field, more particularly to a kind of high reliability solid state disk.
Background technology
With the continuous development of electronic information technology, the demand of big data storage constantly drives flash memories rapidly
Develop to more extensive, more high density, higher reliability direction.Solid state disk (SSD, Solid State Driver) is one
The non-volatile storage device of kind possesses and preserves data for a long time, quickly update the data, store the characteristics such as mass data, meets
Big data storage demand in every profession and trade.Solid state disk using high density, large capacity NAND Flash as storage medium, have
The advantages that access speed is fast, memory capacity is big is widely used in the numerous areas such as military affairs, space flight, consumption, industry control, monitoring.
Solid state disk is mainly made of host communication interface, SSD controller, NAND flash storage mediums and power supply interlock circuit,
In, host communication interface, SSD controller, NAND flash storage mediums directly decide the performance of solid state disk.Host communication
Communication interface of the interface as host and solid state disk completes command interaction, data-transformation facility, instantly the mainstream of solid state disk
Communication interface has SATA, AHCI, NVME etc..SSD controller is mainly used for host communication interface to NAND flash storage mediums
Between data transfer；NAND flash storage mediums realize that the storage to data, the performance of NAND flash storage mediums exist
It is played a crucial role in solid state disk, directly restricts the performance of entire solid state disk.
As solid state disk application scenarios become increasingly complex, when its operating ambient temperature is at 60~100 DEG C, it is contemplated that Gu
State hard disk oneself power consumption, the disc temperature of solid state disk may be more than the maximum operation of solid-state hard disk controller or storage medium
Temperature causes solid state disk cisco unity malfunction, leads to user data loss, or even solid state disk permanent damages occurs.Solid-state
Itself generated power consumption causes when the excessively high mainly operating ambient temperature of hard disc temperature and disc business operation, building ring
Border temperature is determined by user, then needing solution disc that can work normally in the high temperature environment, while taking into account disc performance as possible,
It can only achieve the goal by adjusting the performance of disc.
Solid state disk disc performance is mainly reflected in bandwidth, and disc bandwidth is controlled primarily by host communication interface, solid-state
The performance of rear the sort command concurrent capability and NAND flash storage mediums of hard disk controller, the bandwidth of solid state disk disc include
Data transfer bandwidth and order transmission bandwidth, since solid state disk is mainly transmission data, data transfer bandwidth is mainly made
About disc bandwidth.And it is substantially fixed for the rear sort command concurrent capability of specified its solid-state hard disk controller of disc.
In existing technology, mainly reduce host communication interface I/O concurrencies come achieve the purpose that reduce disc temperature, still,
When disc work environment temperature on 80 DEG C it is difficult to ensure that disc can work normally, and can cause disc performance inconsistency compared with
Greatly, bandwidth amplitude is very big, to substantially reduce the performance of solid state disk, seriously limits the extensive use of solid state disk.
In conclusion in the actual use of solid state disk, the environment temperature of solid state disk work is often to go out at 80 DEG C
It is existing, such as enterprise uses server for a long time, or situations such as use in the environment of hot weather solid state disk, to ensure
Disc remains to normal and efficient operation under high temperature, and meets high reliability, is highly desirable to propose that a kind of solid-state is hard
Disk solves the technical bottleneck of solid state disk high performance operation under hot environment.The reliability of solid state disk is improved, is realized more wide
General application, makes it possible the solid state disk of manufacture high reliability.
Invention content
In view of the foregoing drawbacks, technical problem to be solved by the utility model is to provide a kind of high reliability solid state disk,
By in solid-state hard disk controller Module-embedding high-temperature protection circuit, reaching higher in disc temperature, effectively dropping
Main frame piece temperature to improve the reliability of solid state disk, and takes into account other performances of disc as possible, ensures that solid state disk is high
Safe, reliable, efficient work under temperature.To achieve the above object, current solid state disk technical bottleneck in a high temperauture environment is solved,
The utility model provides a kind of high reliability solid state disk, including：
Front end host communication interface, solid-state hard disk controller and NAND flash storage medium chips；
The front end host communication interface is connected with solid-state hard disk controller, is used between host computer and disc into line number
It is controlled to host or by the data transmission of host to solid state disk according to the data transmission of the interface of transmission, including solid state disk
Device；
The solid-state hard disk controller is connected with host communication interface, is also deposited with the NAND Flash in more than two channels
It stores up chip to be connected, for controlling the data transmission of entire solid state disk disc, order is transmitted and reading, programming, wiping to disc
Except the control of business operation；
NAND flash storage medium chips, are connected with solid-state hard disk controller.
The front end host communication interface includes SATA interface or PCIE interfaces.
The solid-state hard disk controller, including：
Temperature sensing circuit module generates temperature detection trigger signal and is connected to the temperature read module, for connecing
Control signal in shrinkage temperature read module, triggering temperature sensing circuit module carry out temperature detection, and periodically by temperature
Value information is sent to high temperature Control for Speed Limitation module；
Temperature read module generates temperature reading control signal and is connected to the temperature sensing circuit module and periodically touches
Power Generation Road, the temperature level for reading solid state disk disc in real time；
Timing trigger circuit generates periodically timing pip and is connected to high temperature Control for Speed Limitation module and temperature reading
Modulus block gives temperature read control circuit for the trigger mechanism as temperature detection by period transmission timing pip；
High temperature Control for Speed Limitation module, the signal for generating control clocked flip are connected to the timing trigger circuit, generate
Control for Speed Limitation order is connected to the NAND Flash controllers, and the temperature information value of reception is sent to the high temperature speed limit
Maker module is more than set temperature level for the temperature when solid state disk disc, high temperature limit is carried out to solid state disk
Speed control；
NAND Flash controllers receive the Control for Speed Limitation order of high temperature Control for Speed Limitation module transmission, and it is logical to generate adjustment
The control signal and data amount of bandwidth of road and NAND Flash memory chip data bandwidths to NAND Flash memory chips connect
Mouth circuit, the programming or reading for controlling entire solid state disk disc or erasing operation, and control the biography of data and order
It passs, and receives the high temperature speed limit logic control signal and NAND Flash memory chip speed-limiting bandwidthes of the transmission of high temperature speed limit module
Value；
NAND Flash memory chip interface circuits receive the control signal and data of the transmission of NAND Flash controllers,
It generates the programming for accessing NAND flash storage chips or erasing or read operation sequential is sent to NAND Flash storage cores
Piece；
High temperature speed limit maker module generates NAND Flash readings or the latency values size transmission of program command
To high temperature Control for Speed Limitation module, for receiving the obtained different temperatures value of information of high temperature Control for Speed Limitation module, and NAND is generated
Flash is read or the latency values size of program command.
The NAND flash storage mediums chip uses 8 NAND flash storage medium chip cascades, constitutes one
NAND Flash memory channels, altogether 4 NAND Flash memory channels.
The NAND flash storage mediums chip includes that SLC NAND Flash memory chips, MLC NAND Flash are deposited
Store up chip, TLC NAND Flash memory chips, 3D NAND Flash memory chips.
The timers trigger circuit, including counter are realized by counter and are counted, when the triggering week for counting up to setting
Phase generates trigger signal and is sent to temperature read control circuit.
The temperature sensing circuit module includes：
Temperature signal is sent to temperature conversion circuit by temperature sensor, is used for measuring temperature information, generates temperature letter
Number；
Temperature conversion circuit receives the temperature signal of the temperature sensor transmission, generates voltage signal to the height
Warm Control for Speed Limitation module, for temperature signal to be converted to voltage signal；
Trigger module is detected, detection trigger signal is generated and is connected with the temperature conversion circuit, for generating detection
Trigger signal is simultaneously sent to the temperature conversion circuit；
Temperature data register, the operating temperature for storing solid state disk are connected with the high temperature Control for Speed Limitation module
It connects.
The NAND Flash are read or the latency values size of program command, include to NAND Flash memory chips
The operating time of reading or program command, for controlling NAND flash storage chip operation data transfer bandwidths.
Description of the drawings
Fig. 1 shows the solid state disk of the addition high-temperature protection circuit according to the utility model embodiment.
Fig. 2 shows the internal structure block diagrams according to the temperature sensing circuit module of the utility model embodiment.
Fig. 3 shows the high temperature Control for Speed Limitation module map according to the utility model embodiment.
Fig. 4 shows a kind of solid state disk high-temperature protection method overview flow chart according to the utility model embodiment.
Fig. 5 shows to adjust process discs bandwidth curve figure in speed limit according to the solid state disk of the utility model embodiment.
Specific implementation mode
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with the accompanying drawings and specifically
Embodiment is described in further detail the utility model.It should be appreciated that specific embodiment described herein is only used
To explain the utility model, it is not used to limit the utility model.
Referring to Fig. 1, according to the utility model embodiment provide one kind add high-temperature protection circuit solid state disk (SSD,
Solid State Driver) device, under the environment that reaches a high temperature high-performance and it is high can reliability solid state disk.Including front end master
Machine communication interface, solid-state hard disk controller and NAND flash storage medium chips.The operation service of solid state disk is total to be divided into
Programming business reads business and erasing business.Entire Ssd apparatus realization stores the data that host issues to NAND
In flash storage particle, it can also realize the digital independent that stores NAND flash storages to host.The preceding end main frame
Communication interface is connected with solid-state hard disk controller, the interface for carrying out data transmission between host computer and disc, including solid
The data transmission of state hard disk is to host or by the data transmission of host to solid-state hard disk controller；For by the number of solid state disk
According to being sent to host or by the data transmission of host to solid-state hard disk controller.The front end host communication interface includes SATA
Interface or PCIE interfaces can support SATA3.0 (Serial ATA, the serial ATA) interfaces or PCIE of current mainstream
(Peripheral Component Interconnect Express) interface.Solid-state hard disk controller connection host communication connects
Mouthful, for receiving or uploading data to host communication interface, solid-state hard disk controller is the core of entire solid state disk, is used for
Control data transmission, order transmission and the reading to disc, programming, the operation for wiping business of entire solid state disk disc.Gu
State hard disk controller is connected to NAND Flash memory chips, is used for when to solid state disk read operation, from NAND Flash
The data transmission that storage chip is read will be read to solid-state hard disk controller, then by the operation and control of solid-state hard disk controller
Data be sequentially delivered to host communication interface circuit, be finally uploaded to host；Solid-state hard disk controller includes temperature detection electricity
Road module generates temperature detection trigger signal and is connected to the temperature read module, for receiving in temperature read module
Signal is controlled, triggering temperature sensing circuit module carries out temperature detection, and temperature value information is periodically sent to high temperature limit
Fast control module；
Temperature read module generates temperature reading control signal and is connected to the temperature sensing circuit module and periodically touches
Power Generation Road, the temperature level for reading solid state disk disc in real time；
Timing trigger circuit generates periodically timing pip and is connected to high temperature Control for Speed Limitation module and temperature reading
Modulus block gives temperature read control circuit for the trigger mechanism as temperature detection by period transmission timing pip；
High temperature Control for Speed Limitation module, the signal for generating control clocked flip are connected to the timing trigger circuit, generate
Control for Speed Limitation order is connected to the NAND Flash controllers, and the temperature information value of reception is sent to the high temperature speed limit
Maker module is more than set temperature level for the temperature when solid state disk disc, high temperature limit is carried out to solid state disk
Speed control；
NAND Flash controllers receive the Control for Speed Limitation order of high temperature Control for Speed Limitation module transmission, and it is logical to generate adjustment
The control signal and data amount of bandwidth of road and NAND Flash memory chip data bandwidths to NAND Flash memory chips connect
Mouth circuit, the programming or reading for controlling entire solid state disk disc or erasing operation, and control the biography of data and order
It passs, and receives the high temperature speed limit logic control signal and NAND Flash memory chip speed-limiting bandwidthes of the transmission of high temperature speed limit module
Value；
NAND Flash memory chip interface circuits receive the control signal and data of the transmission of NAND Flash controllers,
It generates the programming for accessing NAND flash storage chips or erasing or read operation sequential is sent to NAND Flash storage cores
Piece；NAND Flash memory chips interface circuit can support asynchronous, ONFI protocol interfaces and Toggle protocol interfaces.This field
Technical staff is it is found that ONFI (Open NAND Flash Interface) agreements and Toggle synchronous protocols are NAND Flash
The international protocol that memory particle manufacturer marks jointly, different vendor use different agreement.
High temperature speed limit maker module generates NAND Flash readings or the latency values size transmission of program command
To high temperature Control for Speed Limitation module, for receiving the obtained different temperatures value of information of high temperature Control for Speed Limitation module, and NAND is generated
Flash is read or the latency values size of program command.Temperature sensing circuit module described in the utility model embodiment, temperature
Spend read module, timing trigger circuit module, high temperature Control for Speed Limitation module, high temperature speed limit module, NAND Flash controllers
(NAND Flash Controller, NFC) and NAND flash storage interface circuits are all made of digital integrated electronic circuit,
For the chip circuit module of physical presence.
Solid state disk rear end includes NAND Flash memory chips interface circuit in NAND Flash controllers and mostly logical
The NAND Flash memory chips in road.Solid state disk rear end is made of multichannel in the utility model embodiment, in this way can be real
The massive store of existing data and the efficient storage of data.Per channel generally by being more than two NAND Flash memory chip structures
At the chips of NAND flash storage mediums described in the present embodiment use 8 NAND flash storage medium chip cascades, constitute
One NAND Flash memory channel, altogether 4 NAND Flash memory channels.Wherein NAND flash storage mediums chip
Including SLC NAND Flash memory chips, MLC NAND Flash memory chips, TLC NAND Flash memory chips, 3D
NAND Flash memory chips.SLC NAND Flash (Single Level Cell, single layer cell flash memory) storage chip, that is, every
A array device stores 1 bit data, each array device of MLC NAND Flash (Multi-Level Cell) storage chips
2 bit datas are stored, each array device of TLC NAND Flash (Triple-Level Cell) storage chip stores 3 bits
Data.Its array structure of 3D NAND Flash memory chips uses current foreword technology three-dimensional storage, substantially increases and deposits
Store up capacity.When to solid state disk programming operation, solid-state hard disk controller receives the data and life transmitted by host communication interface
It enables, and corresponding time sequential routine circuit is generated according to operational order, data are sent to NAND according to programming operation sequential
Flash memory chip specifies address, completes the programming operation to solid state disk.Host communication interface uses SATA (Serial
Advanced Technology Attachment, serial ATA interface specification) interface protocol, it realizes and is ordered with SATA host
Enable interaction and data transmission.The core component of solid state disk be solid-state hard disk controller and NAND flash storage medium chips,
Solid-state hard disk controller, which is used to control from host, is sent to the data transmission of front end interface circuit to solid-state hard disk controller, and controls
System realize from host transmit into data be programmed to NAND flash storage chips, or control is realized and is deposited to NAND Flash
The erasing operation of memory chip, or realize and read data to front end interface circuit from NAND flash storage chips.
NAND Flash memory chips are used to store as data.The Ssd apparatus of the utility model embodiment is to solid state disk control
Device processed is improved, and high-temperature protection circuit control module is added, and the high temperature protection to solid state disk is realized, in smaller influence solid-state
Solid state disk is dramatically improved under the premise of hard disk performance ground stability.Fig. 1 is shown according to the utility model embodiment
Be added method for limiting speed after solid state disk circuit device, wherein solid-state hard disk controller includes temperature sensing circuit module, temperature
Spend read module, timing trigger circuit module, high temperature Control for Speed Limitation module, high temperature speed limit module, NAND Flash controllers
(NAND Flash Controller, NFC) and NAND flash storage interface circuits.Temperature sensing circuit module and temperature
Read module, timing trigger circuit module, high temperature Control for Speed Limitation module, high temperature speed limit module are sequentially connected；High temperature speed limit control
Molding block is sequentially connected with NAND Flash controllers, NAND Flash memory chip interface circuits.Wherein, temperature detection electricity
Road module generates temperature detection trigger signal and is connected to the temperature read module, for receiving the control in temperature read module
Signal, triggering temperature sensing circuit module carries out temperature detection, and temperature value information is periodically sent to high temperature speed limit control
Molding block.Temperature sensing circuit module includes an analog-digital converter, and analog signal source is temperature sensing circuit module.Temperature
Detection circuit is converted to the realization module of electric signal as physical signal, and core devices are PT100 temperature sensors in module,
Temperature signal is transmitted to corresponding detection circuit by medium and is converted to electric signal by it.Temperature read module for reading in real time
Take the temperature level of solid state disk disc.Trigger mechanism of the timers trigger circuit as temperature detection is transmitted by the period and is triggered
Signal gives temperature read module, triggering period that can mainly be completed by increasing a main-machine communication order by User Defined
Trigger the update in period.The triggering period is handed down to timer circuit by CPU, and timer circuit includes counter, by counter reality
It now counts, when the triggering period for counting up to setting, that is, generates trigger signal and be sent to temperature read module.High temperature Control for Speed Limitation mould
Block be used for when solid state disk disc temperature be more than set temperature level, according to the utility model implement high temperature algorithm into
Row high temperature speed limit.Wherein, the method for high temperature speed limit is the data transfer bandwidth of adjustment NAND Flash, including to NAND
The data throughput of the concurrent number of channels of order and/or NAND Flash interfaces in Flash controllers is adjusted.High temperature limits
Fast value maker module for receiving the obtained difference values of information of high temperature Control for Speed Limitation module, including the first temperature of disc T1,
Disc second temperature T2, the first read access time Cr1 of disc third temperature T3, NAND Flash and the first programming time Cw1,
The the second read access time Crmax2 and the second programming time Cwmax2 of NAND Flash.High temperature speed limit maker module receives high
After the calculated high-temperature control parameter of warm Control for Speed Limitation module institute, the actual program generated to NAND flash storage mediums is calculated
Time Cwrite and/or read operation time Cread time values size to NAND flash storage mediums, will finally calculate
The actual program time Cwrite and/or the value size of Cread times read operation time to NAND flash storage mediums
It is sent to high temperature Control for Speed Limitation module, its value size is sent to NAND Flash controllers by the control of high temperature Control for Speed Limitation module.
NAND Flash controllers are used to control the transmission of programming, reading, erasing operation and the data and order of entire disc, and connect
Receive the high temperature speed limit logical signal and NAND Flash memory chip limited speed belt width values that high temperature speed limit module is transmitted.By NAND
Flash controllers access NAND Flash according to the value size control NAND Flash memory chip interface circuits, final regulation and control
The data bandwidth of storage chip, to reach the excessively high scheme for carrying out speed limit of temperature, temperature, which reduces, restores data bandwidth.NAND
Flash memory chip interface circuit receives the control signal and data of the transmission of NAND Flash controllers, generates and access NAND
The sequential of flash storage chip is sent to NAND Flash storage chips.Therefore, in other works for not influencing solid state disk
Make efficiently solve solid state disk work problem in a high temperauture environment in the case of performance indicator, substantially increases solid state disk
Reliability.
Secondly, the solid state disk of the utility model embodiment has 4 channels, and each channel can be with 8 NAND of carry
The massive store and higher bandwidth of data, multichannel may be implemented in the solid state disk of Flash storage medium chips, multichannel
The problem of solid state disk co-operation causes solid state disk disc temperature rise is also the reason of the utility model causes high temperature,
Meet multichannel progress big data transmission and multi-channel data transmission causes the raised contradictory problems of disc temperature to be also this reality
One of the problem of solved with New Scheme.High temperature speed limit circuit strategy is the data transfer bandwidth for adjusting NAND Flash,
Include the adjustment to the concurrent number of channels of order in NAND Flash controllers, high temperature Control for Speed Limitation module receives temperature
When the value of information size of read module, compares the disc temperature value and initial temperature threshold difference size of reading, work as solid state disk
Actual temperature be more than the initial temperature threshold value and higher than the disc temperature value of upper a cycle of setting, reduce NAND Flash
The concurrent number of channels of order in controller；When the actual temperature of solid state disk is more than initial temperature threshold value and than upper a cycle
Disc temperature value want low, increase NAND Flash controllers in the concurrent number of channels of order；When the practical temperature of solid state disk
Degree is less than initial temperature threshold value, restores the concurrent number of channels of order in the NAND Flash controllers of acquiescence.
The continuous development of solid state disk, integrated level is higher and higher, not in the case where being only suitable for ordinary room temperature environment, application
Scene becomes increasingly complex, under some special application scenarios, if environment temperature is more than such as 60~100 degrees Celsius of ordinary temperature
When, then to the programming operation of solid state disk either read operation or when erasing operation, its own operating power consumption is very high, may
It is more than the technological temperature of its chip to cause the temperature of solid state disk itself, causes solid state disk disc abnormal work, leads to user
The case where loss of data, also results in solid state disk and burns out when serious.Fig. 1 is shown according to the utility model embodiment front end interface
Circuit uses SATA protocol, in order not to slow down the access rate of solid state disk and do not reduce other performance indicators, the utility model
Still front end interface is used to issue 32 I/O port orders simultaneously, i.e. the concurrency of front end I/O port is still 32, special with having before
The reduction instruction queue depth (reducing front end I/O port concurrency) that sharp CN201210475065 proposes high temperature protection is compared,
Although the scheme for having patent plays the role of protecting solid state disk to a certain extent, but causes the whole of solid state disk
Body performance is greatly reduced.The utility model proposes the high-temperature protection method of solid state disk a kind of well solved existing skill
The bottleneck of art, the protection under customer service hot environment to solid state disk, while well ensuring the superperformance of solid state disk,
Enhance the reliability of solid state disk.
Fig. 2 shows the internal structure block diagrams realized according to the temperature sensing circuit module of the utility model embodiment, including
Temperature sensor, temperature conversion circuit, temperature data register, detection trigger module.Wherein, temperature sensor, temperature transition
Circuit, temperature data register are sequentially connected, and detection trigger module is connected to temperature conversion circuit.Temperature sensor is used for will be warm
It spends in signal transmission to temperature conversion circuit, temperature sensor is constituted using special substance, for its application scenarios, uses the longevity
Life, precision have preferable effect.Temperature conversion circuit causes voltage's distribiuting according to the corresponding impedance variations of temperature sensor,
The main thermo-resistive effect using temperature sensor carries out, to obtain conversion of the temperature physical signal to voltage signal.Due to temperature
The particularity of degree sensor (PT100) needs temperature-compensation circuit, and main function is calibrated to it, for using
The temperature value arrived is more accurate.Just directly digital signal can be obtained after temperature signal is converted to voltage signal by analog-to-digital conversion
Value, conversion benchmark carry out as the following formula：
Temperature value=Vout/Cbase
In above formula, temperature value is final exact value, and Vout is the value of electrical signals that temperature conversion circuit obtains, and Cbase is
Temperature reference value, the i.e. linear relationship of the variation of voltage value caused by every degree Celsius of variation.In actual application, sensor
The temperature resistance efficiency of part is unlikely to be linear relationship, but after overcompensation, can approximation see linear relationship as, thus can calculate
To the operating temperature of solid state disk.And operating temperature is temporarily stored into temperature data register, temperature data register includes
Digital circuit register realizes that solid state disk operating temperature is written in the register by the master control of solid state disk, is finally existed
Needs go to access the base address of the data register with specific time sequence when obtaining the value, and the work of solid state disk is got with this
Make temperature.Temperature detection trigger module is passive type for generating detection trigger signal and being sent to the temperature conversion circuit
Triggering, needs specified trigger signal, so, the acquisition of the temperature of solid state disk is passive type, only provide trigger signal to
After temperature detection trigger module, temperature detection could really work with conversion interlock circuit, and otherwise temperature register preserves
Be last detection result.
For temperature sensor for detecting solid state disk disc temperature, what it got is physical signal, and it is direct to obtain result
Send temperature conversion circuit to.Temperature conversion circuit main function is that physical signal is converted to electric signal, because electric signal is
Actually can sampled signal, electrical signal data is then sent to processor.Data after processor calculates are actual solid-state
Hard disc temperature value, processor are finally deposited in newest temperature value in the temperature register of solid-state address, and user can be straight
It connected the address and gets the current disc temperature value of solid state disk.Detection trigger module is that the sampling solid-state that specially designs is hard
The circuit of disk temperature, user can be applied to the module by simple level triggers, which can automatic trigger temperature transition electricity
Road works and new data is sent to processor.
Fig. 3 shows the high temperature Control for Speed Limitation module map according to the utility model embodiment, including：Temperature acquisition signal, temperature
Degree acquisition register, high temperature Control for Speed Limitation module, the channels NAND Flash, the temperature acquisition register, high temperature Control for Speed Limitation
Module, the channels NAND Flash are all made of digital integrated electronic circuit, are the tangible chip integrated circuits manufactured.
Wherein：
The temperature acquisition signal is connected to the high temperature Control for Speed Limitation module, the temperature acquisition for triggering solid state disk
Circuit works；
The temperature acquisition register is connected to the high temperature Control for Speed Limitation module, for storing disc temperature value；
The high temperature Control for Speed Limitation module is connected to the channels the NAND Flash, for complete according to disc temperature value information
It limits and controls at high temperature；
The channels the NAND Flash are connected to the high temperature Control for Speed Limitation module, for as NAND Flash orders or
The transmission channel of data.
The high temperature Control for Speed Limitation module includes：Temperature acquisition signal generator module, temperature value validation checking module, temperature
Spend times of collection statistical module, temperature analysis module, temperature and threshold value comparison module, high temperature speed limit starts determination module, NFC is ordered
Operating time acquisition module, NFC command operation available time analysis modules and NFC command operation time configuration modules are enabled,
In：
The temperature acquisition signal generator module is connected to the temperature RMS to DC module, for periodically sending out
Temperature detection signal, and temperature value information is received, and it is transmitted to temperature RMS to DC module；Herein, NFC (NAND Flash
Controller, NAND Flash controllers) specialized vocabulary known to those skilled in the art.
The temperature RMS to DC module is connected to the temperature acquisition number statistical module, for temperature value information
It is detected, is directly abandoned if detecting Current Temperatures information in vain；Otherwise, effective temperature information is transmitted to temperature acquisition
Number statistical module；
The temperature acquisition number statistical module is connected to the temperature analysis module, for obtaining multiple temperature information
Value, and count the timestamp information of temperature value；
The temperature analysis module is connected to the temperature and threshold value comparison module, for foundation timestamp information to all
Temperature information analyzed, obtain a maximum temperature value；
The temperature is connected to the high temperature speed limit with threshold value comparison module and starts determination module module, is used for comparison temperature
Value and given threshold, it further includes compared with the upper Periodic Temperature value of information that this, which compares operation,；
The high temperature speed limit starts determination module and is connected to the NFC command operations time-obtaining module, for judging height
Whether warm speed limit, which will start, starts, and generates an enabling signal；
The NFC command operations time-obtaining module is connected to the NFC command operations available time analysis module, uses
According to the actual operating time that the temperature transition currently got is NFC orders；
The NFC command operations available time analysis module is connected to NFC command operation time configuration modules, for pair
The validity of the actual operating time of NFC orders is analyzed, mainly identify current NFC orders actual operating time whether
It transfinites；
The NFC command operations time configuration module is connected to the channels NAND Flash, for storing current NFC orders
Actual operating time, and continuously effective, the operating time until getting new NFC orders.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that can to the temperature of disc into
The real-time acquisition operations of row.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that obtained based on disc temperature
To the actual operating time of NFC read commands.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that obtained based on disc temperature
To the actual operating time of NFC write orders.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that described that disc temperature is believed
It ceases validity and carries out intelligent measurement.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that described to NFC command operations
Time is stored.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that when the NFC command operations
Between can the new operating time replaced.
A kind of high temperature speed-limiting control device for solid-state hard disk controller, which is characterized in that the NFC orders include：
To the order of NAND flash storage read operations, programming operation order, erasing operation order, read states order, pattern switching
Id command is read in order.
A kind of shown solid state disk high temperature protection overview flow charts according to the utility model embodiment of Fig. 4, including with
Lower step：
Step 1：Temperature sensing circuit detects the disc temperature of solid state disk；
Step 2：Clocked flip temperature sensing circuit is set；
Step 3：The initial temperature threshold value of solid state disk is set；
Step 4：Start clocked flip task；
Step 5：The actual temperature information of timing acquisition solid state disk；
Step 6：The actual temperature of solid state disk is compared with the initial temperature threshold value of setting, obtains the difference of the two
Value；
Step 7：According to the difference between the actual temperature and the initial temperature threshold value of setting of solid state disk, solid state disk is adjusted
Bandwidth.
Difference between the actual temperature and the initial temperature threshold value of setting according to solid state disk, adjusts solid state disk
Bandwidth.By detecting the initial temperature difference of temperature and setting, the bandwidth of solid state disk is adjusted to adjust the behaviour of solid state disk
Make the time cycle, to have the function that reduce temperature.The bandwidth of solid state disk includes data transfer bandwidth and order transmission belt
Width, due to being mainly the storage of data to the operation of solid state disk, and order relative data very little, therefore influence solid state disk band
Width is mainly determined by data transfer bandwidth.
The setting clocked flip temperature sensing circuit includes T1 interrupt cycle of the timing circuit of configuration solid state disk,
Start timer, and periodically to temperature sensing circuit transmission timing trigger signal as unit of T1.Temperature sensing circuit mould
Block generates temperature detection trigger signal and is connected to the temperature read module, for receiving the control in temperature read module
Signal, triggering temperature sensing circuit module carries out temperature detection, and temperature value information is periodically sent to high temperature speed limit control
Molding block.
The setting clocked flip temperature sensing circuit includes T1 interrupt cycle of the timing circuit of configuration solid state disk,
Start timer, and periodically trigger signal is sent to temperature sensing circuit as unit of T1.When the practical temperature of solid state disk
When degree reaches the temperature initiation threshold of setting, start to carry out bandwidth limitation to solid state disk.Temperature set by solid state disk rises
For beginning threshold value by user setting, usual embodiment is 70 degrees Celsius.It is originated when temperature sensing circuit detection disc reaches setting temperature
Threshold value then starts to limit solid state disk bandwidth.
The timed task can periodically send trigger signal to temperature sensing circuit, and it is anti-to obtain temperature sensing circuit
The actual temperature of the solid state disk of feedback.The actual temperature of solid state disk is compared with the initial temperature threshold value of setting, is obtained
The difference of the two.Solid state disk actual temperature as the temperature sensing circuit obtained in embodiment is fed back is T1, the starting of setting
Temperature threshold is T2, then finds out the size of T1-T2.It is promoted or is limited by adjusting the data transfer bandwidth of NAND Flash
Solid state disk bandwidth.
The data transfer bandwidth of the adjustment NAND Flash, includes concurrently leading to the order in NAND Flash controllers
The data throughput of road quantity and/or NAND Flash interfaces is adjusted.
The concurrent number of channels of order in the adjustment NAND Flash controllers, including：When the practical temperature of solid state disk
Degree is reduced more than the initial temperature threshold value and higher than the disc temperature value of upper a cycle of setting in NAND Flash controllers
The concurrent number of channels of order；When the actual temperature of solid state disk is more than initial temperature threshold value and than the disc temperature of upper a cycle
Angle value wants low, increases the concurrent number of channels of order in NAND Flash controllers；When the actual temperature of solid state disk is less than
Beginning temperature threshold restores the concurrent number of channels of order in the NAND Flash controllers of acquiescence.
The data throughput of the adjustment NAND Flash interfaces, including：When the actual temperature of solid state disk is more than setting
Initial temperature threshold value and higher than the disc temperature value of upper a cycle, reduce the data throughput of NAND Flash interfaces；
When the actual temperature of solid state disk is more than initial temperature threshold value and, promotion NAND lower than the disc temperature value of upper a cycle
The data throughput of Flash interfaces；When the actual temperature of solid state disk is more than initial temperature threshold value and than the disk of upper a cycle
When piece temperature value wants low, promoted NAND Flash interfaces data throughput to ensure solid state disk integrated operation performance boost,
I.e. when temperature reduction is gone down, solid state disk bandwidth cannot be limited always, therefore uses the data for promoting NAND Flash interfaces
Throughput promotes solid state disk bandwidth, to greatly promoting solid state disk performance.When the actual temperature of solid state disk is less than
Beginning temperature threshold restores the data throughput of the NAND Flash of acquiescence.
It is described adjustment NAND Flash interfaces data throughput, using to NAND flash storage mediums reading or volume
The operating time of journey order is adjusted.It is described to be to the reading of NAND flash storage mediums or the operating time of program command
To the incubation period of NAND Flash memory chips operation.Include the reading to NAND Flash memory chips or program command
Operating time, for controlling NAND flash storage chip operation data transfer bandwidths.
It is described adjustment NAND flash storage mediums reading or programming the business operation time include：
Step 1：The disc temperature for periodically obtaining solid state disk, is denoted as the first temperature of disc T1；
Step 2：The temperature initiation threshold of operating ambient temperature setting disc residing for disc, is denoted as the second temperature of disc
Spend T2；
Step 3：According to the technological temperature upper limit of solid state disk main control chip, set temperature allowance, and calculate solid state disk
The upper limit of disc temperature is denoted as disc third temperature T3；The technological temperature of the solid state disk main control chip is by line of production technology
It is determined, usually 125 degrees Celsius.Such as technological temperature is 125 degrees Celsius in embodiment, temperature allowance is 25 degrees Celsius, then
The upper limit for calculating the disc temperature of solid state disk is the technological temperature upper limit-set temperature allowance=125-25=100 degrees Celsius.Gu
The upper limit of the disc temperature of state hard disk is maximum disc temperature during the adjustment no more than, even hot environment temperature at this time
Degree is 71 degrees Celsius, and the temperature initiation threshold of setting is also 70 degrees Celsius, then starts to adjust solid state disk bandwidth this moment, and to allow
The upper limit 100 degree Celsius of the solid state disk disc temperature no more than disc temperature.
Step 4：The basic operation time that reading or program command are obtained inside NAND flash storage mediums, remember respectively
For the first read access time Cr1 and the first programming time Cw1 of NAND Flash；It obtains and reads inside NAND flash storage mediums
It takes or the basic operation time of program command can be directly by NAND Flash memory chip operation manual, according to chip operation
Handbook sends corresponding order to obtain the first read access time Cr1 and the first programming time Cw1 of NAND Flash.
Step 5：When the first temperature of disc T1 of solid state disk rises to disc third temperature T3, setting NAND Flash are deposited
The reading of storage media or the program command maximum operating time are denoted as the second read access time Crmax2 and the of NAND Flash respectively
Two programming time Cwmax2；
Step 6：According to Cr1 and Crmax2, Cw1 and Cwmax2 obtain the reading of NAND flash storage mediums or programming operation
When, the operating time difference of corresponding order is denoted as the third read access time Cr3 and third programming time of NAND Flash respectively
Cw3；That is Cr3 is the difference of Cr1 and Crmax2 values, and Cw3 is the difference of Cw1 and Cwmax2 values.
Step 7：The actual temperature range difference of solid state disk is obtained according to T2 and T3, is denoted as the first temperature gap of disc
T4；That is T4 is the size of T2-T3.
Step 8：According to T4 and Cr3, T4 and Cw3, the NAND caused by averagely each degree Celsius of temperature change is obtained
The changing value of flash storage medium command operation time, the 4th read cycle Cr4 and the 4th for being denoted as NAND Flash respectively are compiled
Journey period Cw4；
Step 9：If T1 is more than or equal to T2, starts to adjust solid state disk bandwidth, obtain the difference (T1-T2) of T1 and T2, and
This operation service type to NAND flash storage mediums is obtained, operation service type includes programming operation business and reading
Operation service.In conjunction with Cr4 and Cw4 respectively obtain NAND flash storage mediums reading or program command practical operation when
Between.When this is reading order, the actual operating time Cread of NAND flash storage mediums is met：
Cread=(T1-T2) * Cr4+Cr1
When this programming operation, the actual operating time Cwrite of NAND flash storage mediums is met：
Cwrite=(T1-T2) * Cw4+Cw1
If T1 is less than T2, stop adjustment solid state disk bandwidth, the at this time reading of NAND flash storage mediums or programming life
The operating time of order uses the basic operation time.To the actual operating time of the read operation of NAND flash storage mediums
Cread meets：
Cread=Cr1
The actual operating time Cwrite of the programming operation of NAND flash storage mediums is met：
Cwrite=Cw1.
Claims (8)
1. a kind of high reliability solid state disk, which is characterized in that including：Front end host communication interface, solid-state hard disk controller and
NAND flash storage medium chips；
The front end host communication interface is connected with solid-state hard disk controller, for carrying out data biography between host computer and disc
Defeated interface, including solid state disk data transmission to host or by the data transmission of host to solid-state hard disk controller；
The solid-state hard disk controller is connected with host communication interface, also stores core with the NAND Flash in more than two channels
Piece is connected, data transmission, order transmission and the reading to disc, programming, erasing industry for controlling entire solid state disk disc
The control of business operation；
The NAND flash storage mediums chip, is connected with solid-state hard disk controller.
2. high reliability solid state disk as described in claim 1, which is characterized in that the front end host communication interface includes
SATA interface or PCIE interfaces.
3. high reliability solid state disk as described in claim 1, which is characterized in that the solid-state hard disk controller, including：
Temperature sensing circuit module generates temperature detection trigger signal and is connected to the temperature read module, for receiving temperature
The control signal in read module is spent, triggering temperature sensing circuit module carries out temperature detection, and periodically believes temperature value
Breath is sent to high temperature Control for Speed Limitation module；
Temperature read module generates temperature reading control signal and is connected to the temperature sensing circuit module and clocked flip electricity
Road, the temperature level for reading solid state disk disc in real time；
Timing trigger circuit generates periodically timing pip and is connected to high temperature Control for Speed Limitation module and temperature reading mould
Block gives temperature read control circuit for the trigger mechanism as temperature detection by period transmission timing pip；
High temperature Control for Speed Limitation module, the signal for generating control clocked flip are connected to the timing trigger circuit, generate speed limit
Control command is connected to the NAND Flash controllers, and the temperature information value of reception, which is sent to the high temperature speed limit, to be generated
Device module is more than set temperature level for the temperature when solid state disk disc, high temperature speed limit control is carried out to solid state disk
System；
NAND Flash controllers, receive high temperature Control for Speed Limitation module transmission Control for Speed Limitation order, generate adjustment channel and
The control signal and data amount of bandwidth of NAND Flash memory chip data bandwidths is electric to NAND Flash memory chips interface
Road, the programming or reading for controlling entire solid state disk disc or erasing operation, and the transmission of data and order is controlled, and
Receive the high temperature speed limit logic control signal and NAND Flash memory chip limited speed belt width values that high temperature speed limit module is transmitted；
NAND Flash memory chip interface circuits receive the control signal and data of the transmission of NAND Flash controllers, generate
The programming or erasing of access NAND flash storage chips or read operation sequential are sent to NAND Flash memory chips；With
And
High temperature speed limit maker module, the latency values size transmission for generating NAND Flash readings or program command are supreme
Warm Control for Speed Limitation module for receiving the obtained different temperatures value of information of high temperature Control for Speed Limitation module, and generates NAND
Flash is read or the latency values size of program command.
4. high reliability solid state disk as described in claim 1, which is characterized in that the NAND flash storage mediums chip
Using 8 NAND flash storage medium chip cascades, a NAND Flash memory channel is constituted, altogether 4 NAND
Flash memory channels.
5. high reliability solid state disk as described in claim 1, which is characterized in that the NAND flash storage mediums chip
Including SLC NAND Flash memory chips, MLC NAND Flash memory chips, TLC NAND Flash memory chips, 3D
NAND Flash memory chips.
6. high reliability solid state disk as claimed in claim 3, which is characterized in that the timing trigger circuit, including count
Device is realized by counter and is counted, and when the triggering period for counting up to setting, that is, is generated trigger signal and is sent to temperature reading control electricity
Road.
7. high reliability solid state disk as claimed in claim 3, which is characterized in that the temperature sensing circuit module includes：
Temperature signal is sent to temperature conversion circuit by temperature sensor, is used for measuring temperature information, generates temperature signal；
Temperature conversion circuit receives the temperature signal of the temperature sensor transmission, generates voltage signal to the high temperature and limit
Fast control module, for temperature signal to be converted to voltage signal；
Trigger module is detected, detection trigger signal is generated and is connected with the temperature conversion circuit, for generating detection triggering
Signal is simultaneously sent to the temperature conversion circuit；
Temperature data register, the operating temperature for storing solid state disk are connected with high temperature Control for Speed Limitation module.
8. high reliability solid state disk as claimed in claim 2, which is characterized in that the NAND Flash are read or programming life
The latency values size of order, includes the operating time of the reading to NAND Flash memory chips or program command, for controlling
NAND flash storage chip operation data transfer bandwidths.
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| CN201721838695.6U CN207690062U (en) | 2017-12-25 | 2017-12-25 | A kind of high reliability solid state disk |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107977169A (en) * | 2017-12-25 | 2018-05-01 | 成都信息工程大学 | A kind of high reliability solid state hard disc |
| CN110289027A (en) * | 2019-06-28 | 2019-09-27 | 深圳忆联信息系统有限公司 | Storage particle method for excessive heating protection and device based on solid state hard disk |
| CN113377179A (en) * | 2021-06-10 | 2021-09-10 | 深圳忆联信息系统有限公司 | Method and device for reducing working temperature of solid state disk, computer equipment and medium |
| WO2022037565A1 (en) * | 2020-08-21 | 2022-02-24 | 中兴通讯股份有限公司 | Access method and system for memory, memory access management module, energy efficiency ratio controller and computer-readable storage medium |
-
2017
- 2017-12-25 CN CN201721838695.6U patent/CN207690062U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107977169A (en) * | 2017-12-25 | 2018-05-01 | 成都信息工程大学 | A kind of high reliability solid state hard disc |
| CN110289027A (en) * | 2019-06-28 | 2019-09-27 | 深圳忆联信息系统有限公司 | Storage particle method for excessive heating protection and device based on solid state hard disk |
| WO2022037565A1 (en) * | 2020-08-21 | 2022-02-24 | 中兴通讯股份有限公司 | Access method and system for memory, memory access management module, energy efficiency ratio controller and computer-readable storage medium |
| CN113377179A (en) * | 2021-06-10 | 2021-09-10 | 深圳忆联信息系统有限公司 | Method and device for reducing working temperature of solid state disk, computer equipment and medium |
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