CN207652596U

CN207652596U - Video compression system based on FPGA

Info

Publication number: CN207652596U
Application number: CN201820062375.4U
Authority: CN
Inventors: 张锋顺
Original assignee: Hangzhou Honghui Electronic Technology Co Ltd
Current assignee: Chengdu Dingyi Information Technology Co., Ltd.
Priority date: 2018-01-15
Filing date: 2018-01-15
Publication date: 2018-07-24
Anticipated expiration: 2028-01-15

Abstract

The utility model discloses the Video compression systems based on FPGA,Dsp processor including FPGA processor and its connection,The FPGA processor is connected with SRAM memory cell and clock module,The dsp processor and FPGA processor are respectively connected with power module,The FPGA processor is connected with video encoder,The video encoder connects video input module by analog to digital conversion circuit,Analog-digital conversion circuit as described is connected with dsp processor,The dsp processor is connected with host computer,The power module includes the system power supply being connected with each other and power control circuit,The system power supply connects FPGA processor,The power control circuit is connect with dsp processor,The utility model uses calculation processing module of the FPGA processor as video data,With flexible and efficient,The characteristics of convenient for applying,And it uses and connect the performance advantage for further increasing FPGA processor jointly with dsp processor,Improve code efficiency,With low in energy consumption,The efficient feature of data processing,It is continuously transmitted suitable for image,The larger Image Acquisition occasion of data volume.

Description

Video compression system based on FPGA

Technical field

The utility model is related to field of video processing, are the Video compression systems based on FPGA specifically.

Background technology

With making rapid progress for science and technology, video monitoring market is also developed rapidly, and video monitoring is intuitive with it, square Just, the information content is abundant and be widely used in many occasions, in recent years, with internet it is a wide range of popularize and computer, The rapid development of network and image procossing, transmission technology, Video Supervision Technique also have significant progress, video monitoring to ooze Thoroughly to the multiple field such as education, government, public place of entertainment, hospital, hotel, sports buildings, urban public security, with the development of economy with The range that the improvement of people's living standards, video and image processing techniques are applied in life is more and more wider, so people are to new The development problem of situation hypograph and video processing technique is more paid close attention to, and digital video and digital picture than traditional image and regard Frequency division resolution wants high, and processing is convenient, easily operated and arrangement, but in application video image processing technology since operating technology is asked Topic or objective factor etc. can all be brought a negative impact to the application of Computer Vision process, reduce the level for the treatment of technology And it is horizontal to improve treatment technology so needing to increase research dynamics for quality.

Image Compression is also a link important in video image processing technology, is determining what image procossing relied on When being the effect of image processing algorithm and processing, since the data volume of video data increases, it is necessary to carry out data compression, but Using multiple applications compressing image data, data volume is still huge, this is just to processor processing speed, transmission medium and storage Medium proposes higher requirement, and therefore, key technology one of of the data compression as data and image processing is further to improve Image Compression Coding Technology has important value.

Utility model content

The purpose of this utility model is to provide the Video compression system based on FPGA, have it is small, low in energy consumption, Video handles efficient feature, is continuously transmitted suitable for image, the Image Acquisition occasion that data volume is larger.

The utility model is achieved through the following technical solutions：Video compression system based on FPGA, including at FPGA It manages device and its dsp processor of connection, the FPGA processor is connected with SRAM memory cell and clock module, the DSP Processor and FPGA processor are respectively connected with power module, and the FPGA processor is connected with video encoder, and the video is compiled Code device connects video input module by analog to digital conversion circuit, and analog-digital conversion circuit as described is connected with dsp processor, the DSP Processor is connected with host computer, and the scheme that system is combined by using dsp processor with FPGA processor makes respective advantage obtain It gives full play to and the address decoding and operation of mutual aid in treatment, wherein FPGA processor for data information, control SRAM is deposited Digital picture of the storage unit caching by analog to digital conversion circuit conversion.

Further is that the utility model is better achieved, and especially uses following setting structures：The power module includes The system power supply and power control circuit of interconnection, the system power supply connect FPGA processor, the power control circuit It is connect with dsp processor, the power control circuit receives the control whistle control system guarantee of power system fortune of dsp processor Capable power supply state, system power supply are responsible for the direct power supply of system.

Further is that the utility model is better achieved, and especially uses following setting structures：The dsp processor connection There are SDRAM, USB port and house dog, the house dog to be connect with power control circuit, SDRAM extends out number for dsp processor According to storage, USB port connects external input unit as input port, and the house dog is timer circuit, is for preventing There is a situation where endless loops for system, when system starts are run, export a signal every one end time and are given to house dog Input terminal feeds dog end, give watchdog zero clearing, and when occurring more than the stipulated time and not inputted, then house dog timing is super When, a reset signal is sent out to dsp processor, and dsp processor reset is made to prevent from crashing.

Further is that the utility model is better achieved, and especially uses following setting structures：The SRAM memory list Member includes the first SRAM memory and the second SRAM memory, and the dsp processor is connected upper by RS232 serial ports Machine is wherein provided with the Buffered Serial mouth of multichannel on dsp processor, video data is carried out in the Buffered Serial mouth of multichannel The compression of signaling traffic.

Further is that the utility model is better achieved, and especially uses following setting structures：The FPGA processor is adopted With, the dsp processor uses type processor, the TMS320VC5509 types processor to have flexible, efficient application characteristic, In conjunction with EP1C6Q240C8 type processors, performance advantage is preferably played, code efficiency is preferably improved, ensure that video figure As the needs handled in real time.

The utility model compared with prior art, has the following advantages and advantageous effect：

The utility model use calculation processing module of the FPGA processor as video data, with it is flexible and efficient, be convenient for Using the characteristics of, and using the performance advantage for further increasing FPGA processor connect jointly with dsp processor, improve coding and imitate Rate meets the needs handled in real time.

Video acquisition, data processing and compressed data by being combined in integrated module by the utility model, then passes through RS232 Video data compression result is transferred to host computer progress video and shown by serial ports, using FPGA processor as Digital Signal Processing Core, can ensure can still be completed efficiently to handle when image data amount is larger and have relatively low cost of manufacture.

Description of the drawings

Fig. 1 is the structural schematic diagram of the utility model.

Specific implementation mode

The utility model is described in further detail with reference to embodiment, but the embodiment of the utility model is not It is limited to this.

It is worth noting that, in the practical application of the utility model, it is inevitably applied to software program, but Shen Ask someone it is hereby stated that, the software program which is applied in the specific implementation is all the prior art, in this application, no It is related to the change and protection of software program, only the protection to the hardware structure designed for realization goal of the invention.

Embodiment 1：

Video compression system based on FPGA, including FPGA processor and its dsp processor of connection, the FPGA Processor is connected with SRAM memory cell and clock module, and the dsp processor and FPGA processor are respectively connected with power supply mould Block, the FPGA processor are connected with video encoder, and the video encoder connects video input by analog to digital conversion circuit Module, analog-digital conversion circuit as described are connected with dsp processor, and the dsp processor is connected with host computer；System by using The scheme that dsp processor is combined with FPGA processor makes respective advantage be not fully exerted and mutual aid in treatment, wherein FPGA Address decoding and operation of the processor for data information, control SRAM memory cell caching are converted by analog to digital conversion circuit Digital picture, the clock module provides clock service for FPGA processor, and clock is provided by clock crystal oscillator, defeated by video Enter module and collected video data signal is transmitted to analog to digital conversion circuit progress data modulus acquisition and A/D conversions, completes Data signal transmission to video encoder is subjected to coded treatment after A/D conversions, then is cached to SRAM and is stored by FPGA processor Device unit, dsp processor carry out compression processing, and communications are carried out by the ports RS232 and host computer.

Embodiment 2：

The present embodiment is further optimized based on the above embodiments, as shown in Figure 1, further is preferably real Existing the utility model, especially uses following setting structures：The dsp processor is connected with SDRAM, USB port and house dog, institute It states house dog to connect with power control circuit, SDRAM extends out data storage for dsp processor, and USB port is as input port External input unit is connected, the dsp processor connects host computer by RS232 serial ports, is wherein arranged on dsp processor The Buffered Serial mouth for having multichannel carries out the compression of stream of video data signals amount in the Buffered Serial mouth of multichannel, described to see Door dog is timer circuit, and for anti-locking system, there is a situation where endless loops, when system starts are run, when one end Between one signal of output be given to the input terminal of house dog, that is, feed dog end, give watchdog zero clearing, do not have occurring more than the stipulated time When being inputted, then house dog timing time-out, sends out a reset signal to dsp processor, so that dsp processor reset is prevented dead Machine；When carrying out compression of images since data volume is larger, it is desirable that the memory of processor is big as far as possible, to avoid to external storage The read-write of device, dsp processor use 128 memory spaces, can carry out operation processing twice to it in each period, significantly Increase the utilization rate of memory, while dsp processor also controls register circuit to it by connection analog to digital conversion circuit and reads Write operation further increases the working efficiency of analog to digital conversion circuit.

Further is that the utility model is better achieved, and especially uses following setting structures：The SRAM memory list Member includes the first SRAM memory and the second SRAM memory, and the dsp processor is connected upper by RS232 serial ports Machine；The TMS320VC5509 types processor has flexible, efficient application characteristic, in conjunction with EP1C6Q240C8 type processors, more Good performance performance advantage, preferably improves code efficiency, ensure that the needs of real-time video processing.

Further is that the utility model is better achieved, and especially uses following setting structures：The FPGA processor is adopted With EP1C6Q240C8 type processors, the dsp processor uses TMS320VC5509 type processors, the TMS320VC5509 There is type processor flexible, efficient application characteristic preferably to play performance advantage in conjunction with EP1C6Q240C8 type processors, compared with Good improves code efficiency, ensure that the needs of real-time video processing.

The above is only the preferred embodiment of the utility model, not does limit in any form to the utility model System, any simple modification made by the above technical examples according to the technical essence of the present invention, equivalent variations, each falls within Within the scope of protection of the utility model.

Claims

1. the Video compression system based on FPGA, it is characterised in that：DSP processing including FPGA processor and its connection Device, the FPGA processor are connected with SRAM memory cell and clock module, and the dsp processor and FPGA processor connect It is connected to power module, the FPGA processor is connected with video encoder, and the video encoder is connected by analog to digital conversion circuit Video input module is connect, analog-digital conversion circuit as described is connected with dsp processor, and the dsp processor is connected with host computer.

2. the Video compression system according to claim 1 based on FPGA, it is characterised in that：The power module packet The system power supply and power control circuit of interconnection are included, the system power supply connects FPGA processor, the power supply control electricity Road is connect with dsp processor.

3. the Video compression system according to claim 1 or 2 based on FPGA, it is characterised in that：The DSP processing Device is connected with SDRAM, USB port and house dog, and the house dog connect with power control circuit.

4. the Video compression system according to claim 3 based on FPGA, it is characterised in that：The SRAM memory Unit includes the first SRAM memory and the second SRAM memory.

5. the Video compression system according to claim 4 based on FPGA, it is characterised in that：The dsp processor Host computer is connected by RS232 serial ports.

6. the Video compression system according to claim 5 based on FPGA, it is characterised in that：The FPGA processor Using EP1C6Q240C8 type processors.

7. the Video compression system according to claim 6 based on FPGA, it is characterised in that：The dsp processor Using TMS320VC5509 type processors.