CN207612256U - A kind of analog to digital conversion circuit - Google Patents

Abstract

The utility model embodiment provides a kind of analog to digital conversion circuit, which includes：With reference to Postponement module, input delay module, with reference to trigger module, input trigger module, judgment module and coding module；Include with reference to Postponement module：2^mA reference signal end, is defined as the 1st to the 2nd successively^mReference signal end；Input delay module includes：2^mA signal end, is defined as the 1st to the 2nd successively^mSignal end；With reference to trigger module, with the 1st to the 2nd^mIt is connected with reference to output end；Trigger module is inputted, with the 1st to the 2nd^mSignal end connects；Judgment module is connect with reference to trigger module and input trigger module；Coding module is connect with judgment module, the mutual cooperation that the technical solution of the utility model passes through above-mentioned each module so that analog to digital conversion circuit is simple in structure, and implements and more facilitate.

Description

A kind of analog to digital conversion circuit

Technical field

The utility model is related to chip design fields, and in particular to a kind of analog to digital conversion circuit.

Background technology

The world today is the society of an advanced IT application, and digital communication technology with rapid changepl. never-ending changes and improvements pushes society's high speed to send out Exhibition carries out information processing using digital information processing system and has become universal selection, but various realities with the real world Object and signal are simulations, and therefore, it is necessary to complete conversion of the analog signal to digital signal using analog to digital conversion circuit.

Specifically, analog-to-digital conversion (Analog-to-digital converter, abbreviation ADC) circuit be it is a kind of will simulation Signal is converted into digital signal, and circuit structure directly proportional therebetween.Analog signal is converted to digital signal, is generally divided into Four steps carry out：It samples, keep, quantify and encodes.The first two steps are completed in sample and hold circuit, rear two step Then completed in adc circuit.Quantization and coding be exactly actual transfer process, by discrete semaphore be converted to closest to two into Code output processed.Existing adc circuit includes：Integral form adc circuit, compares type/string simultaneously at SAR ADC circuit parallel Row type adc circuit and capacitor array gradually comparison A/D C circuits.

Through inventor the study found that existing adc circuit not only structure is more complicated, but also implement also more complex.

Utility model content

In order to solve the above-mentioned technical problem, the utility model provides a kind of analog to digital conversion circuit, to solve existing ADC Not only structure is more complicated for circuit, but also implements also more complex technical problem.

In order to reach the utility model aim, the utility model provides a kind of analog to digital conversion circuit, including：With reference to delay Module, input delay module, with reference to trigger module, input trigger module, judgment module and coding module；

It is described to include with reference to Postponement module：2^mA reference signal end, is defined as the 1st to the 2nd successively^mReference signal end；

The input delay module includes：2^mA signal end, is defined as the 1st to the 2nd successively^mSignal end；

It is described to refer to trigger module, with the 1st to the 2nd^mIt is connected with reference to output end；

The input trigger module, with the 1st to the 2nd^mSignal end connects；

The judgment module is connect with described with reference to trigger module and the input trigger module；

The coding module is connect with the judgment module.

Optionally, described to further include with reference to Postponement module：Cascade 2^mIt is a with reference to delay cell, high reference voltage end and low Reference voltage end, by 2^mIt is a to be defined as the 1st to the 2nd successively with reference to delay cell^mWith reference to delay cell；

The input terminal of 1st reference delay cell is connect with high reference voltage end and low reference voltage end,

The input terminal of i-th reference delay cell is connect with low reference voltage end, and output end is connect with the i-th reference signal end, Wherein, 1≤i≤2^m。

Optionally, described to further include with reference to Postponement module：First external circuits；

First external circuits and the 2nd^mIt is connected with reference to the output end of delay cell

Optionally, the input delay module further includes：Cascade 2^mIt is -1 input delay unit, input signal end, low Reference voltage end, by 2^m- 1 input delay unit is defined as the 1st to the 2nd successively^m- 1 input delay unit；

The input terminal of 1st input delay unit is connect with input signal end, the 1st signal end and low reference voltage end；

The input terminal of i-th input delay unit and low reference voltage end, output end are connect with i+1 signal end, wherein 1 ≤i≤2^m-1。

Optionally, the input delay module further includes：Second external circuits；

Second external circuits and the 2nd^mThe output end of -1 input delay unit connects.

Optionally, described to include with reference to delay cell：First phase inverter, the second phase inverter and capacitance；

The input terminal of first phase inverter connects as the input terminal with reference to delay cell with the high reference voltage end It connects, the output end of first phase inverter, connects respectively with the first end of the input terminal of second phase inverter and the capacitance It connects；

The output end of second phase inverter is as the output end with reference to delay cell；

The second end of the capacitance is connect with the low reference voltage end.

Optionally, the input delay unit includes：First phase inverter, the second phase inverter and capacitance；

Input terminal of the input terminal of first phase inverter as input delay unit, connect with the input signal end, The output end of first phase inverter is connect with the first end of the input terminal of second phase inverter and the capacitance respectively；

Output end of the output end of second phase inverter as input delay unit；

The second end of the capacitance is connect with the low reference voltage end.

Optionally, described to include with reference to trigger module：2^mIt is a to refer to trigger, it is defined as the 1st to the 2nd successively^mWith reference to triggering Device；

Described 1st to the 2nd^mWith reference to trigger and the 1st to the 2nd^mReference signal end is correspondingly connected with.

Optionally, the input trigger module includes：2^mA input trigger, is defined as the 1st to the 2nd successively^mInput triggering Device；

Described 1st to the 2nd^mInput trigger and the 1st to the 2nd^mSignal end is correspondingly connected with.

Optionally, the judgment module includes：2^mA and door, is defined as the 1st to the 2nd successively^mWith door；

Described 1st to the 2nd^mWith the first input end of door and the 1st to the 2nd^mIt is correspondingly connected with reference to the output end of trigger；

Described 1st to the 2nd^mWith the second input terminal of door and the 1st to the 2nd^mThe output end of input trigger is correspondingly connected with；

Described 1st to the 2nd^mIt is connect with coding module with the output end of door.

The utility model provides a kind of analog to digital conversion circuit, which includes：With reference to Postponement module, input delay module, With reference to trigger module, input trigger module, judgment module and coding module；Include with reference to Postponement module：2^mA reference signal end, It is defined as the 1st to the 2nd successively^mReference signal end；Input delay module includes：2^mA signal end, is defined as the 1st to the 2nd successively^m Signal end；With reference to trigger module, with the 1st to the 2nd^mIt is connected with reference to output end；Trigger module is inputted, with the 1st to the 2nd^mSignal end connects It connects；Judgment module is connect with reference to trigger module and input trigger module；Coding module is connect with judgment module, this practicality is new The mutual cooperation that the technical solution of type passes through above-mentioned each module so that analog to digital conversion circuit is simple in structure, and implements more It is convenient.

Certainly, implement the utility model any product or method it is not absolutely required to and meanwhile reach all the above Advantage.Other features and advantages of the utility model will illustrate in subsequent specification embodiment, also, partly from explanation It becomes apparent in book embodiment, or is understood by implementing the utility model.The purpose of the utility model embodiment and Other advantages can be realized and be obtained by specifically noted structure in specification, claims and attached drawing.

Description of the drawings

Attached drawing is used for providing further understanding technical solutions of the utility model, and a part for constitution instruction, With for explaining the technical solution of the utility model, do not constituted to technical solutions of the utility model together with embodiments herein Limitation.

Fig. 1 is one of the structural schematic diagram of analog to digital conversion circuit that the utility model embodiment provides；

Fig. 2 is the second structural representation for the analog to digital conversion circuit that the utility model embodiment provides；

Fig. 3 is the equivalent circuit diagram for the analog to digital conversion circuit that the utility model embodiment provides.

Specific implementation mode

To make the purpose of this utility model, technical solution and advantage be more clearly understood, below in conjunction with attached drawing to this The embodiment of utility model is described in detail.It should be noted that in the absence of conflict, embodiment in the application and Feature in embodiment mutually can be combined arbitrarily.

Step shown in the flowchart of the accompanying drawings can be in the computer system of such as a group of computer-executable instructions It executes.Also, although logical order is shown in flow charts, and it in some cases, can be with suitable different from herein Sequence executes shown or described step.

Embodiment

Fig. 1 is one of the structural schematic diagram of analog to digital conversion circuit that the utility model embodiment provides, as shown in Figure 1, this Utility model embodiment provide analog to digital conversion circuit include：With reference to Postponement module 10, input delay module 20, with reference to trigger mode Block 30, input trigger module 40, judgment module 50 and coding module 60.

In the present embodiment, include with reference to Postponement module 10：2^mA reference signal end (not shown), is defined as successively 1st to the 2nd^mReference signal end, for carrying out delay disposal to reference signal.

Input delay module 20 includes：2^mA signal end, is defined as the 1st to the 2nd successively^mSignal end (not shown) is used In to input signal progress delay disposal.

Specifically, it should be noted that different input signals corresponds to different delay times, the voltage of input signal is got over Small, delay time is longer.

With reference to trigger module 30, with the 1st to the 2nd^mIt is connected with reference to output end, for receiving the letter sent with reference to Postponement module Number, to generate corresponding first digital signal.

It should be noted that being " 1 " with reference to the first digital signal that trigger module generates.

Trigger module 40 is inputted, with the 1st to the 2nd^mSignal end connects, the signal for receiving the transmission of input delay module, To generate corresponding second digital signal.

Specifically, the second digital signal is " 1 " or " 0 ".

Judgment module 50 is connect with reference to trigger module 30 and input trigger module 40, for according to reference to trigger module The second digital signal that the first digital signal and output trigger module 40 of 30 outputs export, generates corresponding third number letter Number.

Specifically, judgment module 50 judges whether the first digital signal and the second digital signal are " 1 ", if the first number Signal is " 1 ", and the second digital signal is " 1 ", then it is " 1 ", otherwise, third digital signal to generate corresponding third digital signal then It is then " 0 ".

Coding module 60 is connect with judgment module 50, and the third digital signal for being exported according to judgment module 50 generates The corresponding binary coding of input signal.Specifically, coding module 60 can be encoder, the utility model does not make this any It limits.

The above-mentioned analog to digital conversion circuit that the utility model embodiment provides passes through delay time caused by input voltage and ginseng The delay time for examining signal compares, and obtains the corresponding binary coding of analog signal, by the mutual cooperation of above-mentioned each module, So that analog to digital conversion circuit is simple in structure, and implements and more facilitate.

Fig. 2 is the second structural representation for the analog to digital conversion circuit that the utility model embodiment provides, as shown in Fig. 2, ginseng Examining Postponement module 10 further includes：Cascade 2^mA reference delay cell, high reference voltage end Vref and low reference voltage end VGL, By 2^mIt is a to be defined as the 1st to the 2nd successively with reference to delay cell^mWith reference to delay cell.

Specifically, the 1st input terminal and high reference voltage end Vref and low reference voltage end VGL companies with reference to delay cell It connecing, the input terminal of the i-th reference delay cell is connect with low reference voltage end VGL, and output end is connect with the i-th reference signal end Mi, Wherein, 1≤i≤2^m。

Optionally, further include with reference to Postponement module 10：First external circuits；First external circuits and the 2nd^mIt is single with reference to delay The output end connection of member.

In the specific implementation, each single with reference to delay in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides The pre-set delay duration of member can be with all same；Or can also part it is identical, part is different；Or it can also be all different.This It needs to be related to determining according to actual application environment, not limit herein.

Optionally, input delay module 20 further includes：Cascade 2^m- 1 input delay unit, input signal end Vin and Low reference voltage end VGL, by 2^m- 1 input delay unit is defined as the 1st to the 2nd successively^m- 1 input delay unit.

Specifically, the input terminal of the 1st input delay unit and input signal end Vin, the 1st signal end N1 and low reference voltage Hold VGL connections；The input terminal of i-th input delay unit and low reference voltage end VGL, output end connect with i+1 signal end Ni+1 It connects, wherein 1≤i≤2^m-1。

Optionally, input delay module further includes：Second external circuits；Second external circuits and the 2nd^m- 1 input delay list The output end connection of member.

In the specific implementation, in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides, each input delay list The pre-set delay duration of member can be with all same；Or can also part it is identical, part is different；Or it can also be all different.This It needs to be related to determining according to actual application environment, not limit herein.

Fig. 3 is the equivalent circuit diagram for the analog to digital conversion circuit that the utility model embodiment provides, as shown in figure 3, with reference to prolonging Unit includes late：First phase inverter 11, the second phase inverter 12 and capacitance C.

Specifically, the input terminal of the first phase inverter as with reference to delay cell input terminal, the output end of the first phase inverter, It is connect respectively with the first end of the input terminal of the second phase inverter and capacitance；The output end of second phase inverter is used as single with reference to delay The output end of member；The second end of capacitance C is connect with low reference voltage end VGL.

Specifically, the input terminal of the first phase inverter of the first reference delay cell is connect with high reference voltage end, the i-th reference The input terminal of first phase inverter of delay cell is connect with the output end of the (i-1)-th reference delay cell, wherein 2≤i≤2^m, the 1st To the 2nd^mIt is respectively C1 to C2 with reference to the capacitance in delay cell^m。

In the specific implementation, each single with reference to delay in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides Capacitance in member can be with all same；Or can also part it is identical, part is different；Or it can also be all different.This is needed It is related to determining according to actual application environment, does not limit herein.

In the specific implementation, in the analog to digital conversion circuit that the utility model embodiment provides, the first phase inverter, second are instead Phase device and capacitance form the reference delay cell with delayed-action.Operation principle is specially：It is input to the first phase inverter The signal of input terminal is first to capacitor charging by the second phase inverter, before the voltage at capacitance both ends reaches preset threshold voltage, Second phase inverter exports low level signal, after the voltage at capacitance both ends reaches preset threshold voltage, the output of the second phase inverter The signal of high level, wherein it is the pre- of delay cell that capacitance reaches the time used in preset threshold voltage from open charging If postponing duration.Such as by taking default adjacent voltage is 0.9V as an example, in the level of the signal for the input terminal for inputting the first phase inverter For high level when, signal is by the first phase inverter first to capacitor charging, and when voltage after capacitor charging is less than 0.9V, second is anti- Phase device exports low level signal, and when the voltage after capacitor charging is greater than or equal to 0.9V, the second phase inverter exports high level Signal.Voltage of the capacitance from starting to charge up both ends is equal to the pre-set delay duration that the duration used in 0.9V is delay cell.

General phase inverter characterizes the rate of its input and output using average delay time, in the specific implementation, in this reality In above-mentioned analog to digital conversion circuit with new embodiment offer, it can be adjusted by the way that the average delay time of the first phase inverter is arranged The pre-set delay duration of delay cell where saving it.In practical applications, with reference to the default of Postponement module and input delay module Duration needs are related to determining, not limit herein according to actual application environment.

In the specific implementation, in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides, in the first reverser, the When two phase inverters and its capacitance form the reference delay cell with delayed-action, the first phase inverter and the second phase inverter it is specific Structure can with can realize that the concrete structure of delay feature is identical in the prior art, and the concrete structure of above-mentioned capacitance can be with Identical as the realization concrete structure of capacitance of delay feature in the prior art, these are those skilled in the art should understand that having , this will not be repeated here, also should not be taken as the limitation of the utility model.

Optionally, input delay unit includes：First phase inverter, the second phase inverter and capacitance CST.

Specifically, input terminal of the input terminal of the first phase inverter as input delay unit, the output end of the first phase inverter It is connect respectively with the first end of the input terminal of the second phase inverter and capacitance CST；The output end of second phase inverter prolongs as input The output end of slow unit；The second end of capacitance CST is connect with low reference voltage end VGL.

Specifically, the input terminal of the first phase inverter of the first input delay unit is connect with input signal end Vin, i-th is defeated The input terminal for entering delay cell is connect with the output end of the (i-1)-th input delay unit, wherein 2≤i≤2^m- 1, the 1st to the 2nd^m-1 Capacitance in input delay unit is respectively CST1 to CST2^m-1。

In the specific implementation, in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides, each input delay list The capacitance of capacitance in member can be with all same；Or can also part it is identical, part is different；Or it can also be all different. This needs is related to determining, not limit herein according to actual application environment.

In the specific implementation, in the analog to digital conversion circuit that the utility model embodiment provides, the first phase inverter, second are instead Phase device and capacitance form the input delay unit with delayed-action.Operation principle is specially：It is input to the first phase inverter The signal of input terminal is first to capacitor charging by the second phase inverter, before the voltage at capacitance both ends reaches preset threshold voltage, Second phase inverter exports low level signal, after the voltage at capacitance both ends reaches preset threshold voltage, the output of the second phase inverter The signal of high level, wherein it is the pre- of delay cell that capacitance reaches the time used in preset threshold voltage from open charging If postponing duration.Such as by taking default adjacent voltage is 0.9V as an example, in the level of the signal for the input terminal for inputting the first phase inverter For high level when, signal is by the first phase inverter first to capacitor charging, and when voltage after capacitor charging is less than 0.9V, second is anti- Phase device exports low level signal, and when the voltage after capacitor charging is greater than or equal to 0.9V, the second phase inverter exports high level Signal.Voltage of the capacitance from starting to charge up both ends is equal to the pre-set delay duration that the duration used in 0.9V is delay cell.

General phase inverter characterizes the rate of its input and output using average delay time, in the specific implementation, in this reality In above-mentioned analog to digital conversion circuit with new embodiment offer, it can be adjusted by the way that the average delay time of the first phase inverter is arranged The pre-set delay duration of delay cell where saving it.In practical applications, with reference to the default of Postponement module and input delay module Duration needs are related to determining, not limit herein according to actual application environment.

In the specific implementation, in the above-mentioned analog to digital conversion circuit that the utility model embodiment provides, in the first reverser, the Two phase inverters and its capacitance form the input delay unit with delayed-action, the specific knot of the first phase inverter and the second phase inverter Structure can with can realize that the concrete structure of delay feature is identical in the prior art, and the concrete structure of above-mentioned capacitance can be with Realize that the concrete structure of the capacitance of delay feature is identical in the prior art, these are those skilled in the art should understand that having , this will not be repeated here, also should not be taken as the limitation of the utility model.

Optionally, include with reference to trigger module：2^mIt is a to refer to trigger, it is defined as the 1st to the 2nd successively^mWith reference to trigger.

Specifically, the 1st to the 2nd^mWith reference to the input terminal of trigger and the 1st to the 2nd^mReference signal end is correspondingly connected with.

Optionally, input trigger module includes：2^mA input trigger, is defined as the 1st to the 2nd successively^mInput trigger.

Specifically, the 1st to the 2nd^mThe input terminal of input trigger and the 1st to the 2nd^mSignal end is correspondingly connected with.

Optionally, judgment module includes：2^mA and door, is defined as the 1st to the 2nd successively^mWith door.

Specifically, the 1st to the 2nd^mWith the first input end of door and the 1st to the 2nd^mIt is correspondingly connected with reference to the output end of trigger； 1st to the 2nd^mWith the second input terminal of door and the 1st to the 2nd^mThe output end of trigger is correspondingly connected with；1st to the 2nd^mWith the output of door End is connect with encoder.

In the specific implementation, the utility model embodiment provide analog to digital conversion circuit in door, only its first When the level of input terminal and the second input terminal is high level, output end exports the signal of high level；As long as its first input end Level at least one input terminal in the second input terminal is level, and output end exports low level signal.Also, with door Concrete structure can with it is in the prior art identical as door concrete structure, these are those skilled in the art should understand that having , this will not be repeated here.Also limitations of the present invention be should not be taken as.

It is false below by the analog to digital conversion circuit of course of work further instruction the utility model of analog to digital conversion circuit If the reference voltage at high reference voltage end is 1.8V.

Before analog to digital conversion circuit start-up operation, to output signal end Vin input reference voltages, that is, 1.8V, encoder is determined Output is all delay reference time Tref when 1, when analog to digital conversion circuit is started to work, inputs and believes to input signal end Vin Number, it by taking 1.5V as an example, obtains in delay reference time Tref, the location of input delay unit that input signal reaches K is enabled Input delay unit the 1st to K input delays unit before the input delay unit exports high level, input later Delay cell K+1 to the 2nd^m- 1 input delay unit exports low level, at this point, the 1st exports to K input triggers " 1 ", K+1 to the 2nd^mInput trigger exports " 0 ", since all outputs with reference to trigger are " 1 ", the 1st to Two input terminals of K and door are high level, export " 1 ", K+1 to the 2nd^mIt is high level with door first input end, the Two input terminals are low level, export " 0 ", the number of encoder statistics " 1 ", and according to the number of " 1 ", export input signal pair The binary coding answered.

In addition, it is necessary to explanation, analog to digital conversion circuit provided by the utility model can also be by input delay mould Another delay cell is set before 1st input delay unit of block so that the analog to digital conversion circuit becomes Window-type analog-to-digital conversion Circuit, specifically, Window-type analog to digital conversion circuit refers to for a certain section of voltage in the input voltage within 0~reference voltage Quantified, for example, when reference voltage is 1.8V, the voltage of 1.0V~1.2V is quantified, by the way that delay cell is arranged So that being all " 1 " more than 1.2V outputs, it is all " 0 " less than 1.0V outputs, as long as input delay unit is suitably arranged Achieve that Window-type analog to digital conversion circuit.

Although the embodiment disclosed by the utility model is as above, the content only the utility model for ease of understanding And the embodiment used, it is not limited to the utility model.Technical staff in any the utility model fields, Under the premise of not departing from the spirit and scope disclosed by the utility model, it can be carried out in the form and details of implementation any Modification and variation, but the scope of patent protection of the utility model, still should be subject to the scope of the claims as defined in the appended claims.

Claims (10)

1. a kind of analog to digital conversion circuit, which is characterized in that including：With reference to Postponement module, input delay module, with reference to trigger mode Block, input trigger module, judgment module and coding module；

It is described to include with reference to Postponement module：2^mA reference signal end, is defined as the 1st to the 2nd successively^mReference signal end；

The input delay module includes：2^mA signal end, is defined as the 1st to the 2nd successively^mSignal end；

It is described to refer to trigger module, with the 1st to the 2nd^mIt is connected with reference to output end；

The input trigger module, with the 1st to the 2nd^mSignal end connects；

The judgment module is connect with described with reference to trigger module and the input trigger module；

The coding module is connect with the judgment module.

2. analog to digital conversion circuit according to claim 1, which is characterized in that described to further include with reference to Postponement module：Cascade 2^mA reference delay cell, high reference voltage end and low reference voltage end, by 2^mIt is a to be defined as the 1st successively with reference to delay cell To the 2nd^mWith reference to delay cell；

The input terminal of 1st reference delay cell is connect with high reference voltage end and low reference voltage end,

The input terminal of i-th reference delay cell is connect with low reference voltage end, and output end is connect with the i-th reference signal end, wherein 1≤i≤2^m。

3. analog to digital conversion circuit according to claim 2, which is characterized in that described to further include with reference to Postponement module：First External circuits；

First external circuits and the 2nd^mIt is connected with reference to the output end of delay cell.

4. analog to digital conversion circuit according to claim 2 or 3, which is characterized in that the input delay module further includes：Grade The 2 of connection^m- 1 input delay unit, input signal end and low reference voltage end, by 2^m- 1 input delay unit is defined as successively 1st to the 2nd^m- 1 input delay unit；

The input terminal of 1st input delay unit is connect with input signal end, the 1st signal end and low reference voltage end；

The input terminal of i-th input delay unit and low reference voltage end, output end are connect with i+1 signal end, wherein and 1≤i≤ 2^m-1。

5. analog to digital conversion circuit according to claim 4, which is characterized in that the input delay module further includes：Second External circuits；

Second external circuits and the 2nd^mThe output end of -1 input delay unit connects.

6. analog to digital conversion circuit according to claim 5, which is characterized in that described to include with reference to delay cell：First is anti- Phase device, the second phase inverter and capacitance；

The input terminal of first phase inverter divides as the input terminal with reference to delay cell, the output end of first phase inverter It is not connect with the first end of the input terminal of second phase inverter and the capacitance；

The output end of second phase inverter is as the output end with reference to delay cell；

The second end of the capacitance is connect with the low reference voltage end.

7. analog to digital conversion circuit according to claim 6, which is characterized in that the input delay unit includes：First is anti- Phase device, the second phase inverter and capacitance；

Input terminal of the input terminal of first phase inverter as input delay unit, the output end of first phase inverter, point It is not connect with the first end of the input terminal of second phase inverter and the capacitance；

Output end of the output end of second phase inverter as input delay unit；

The second end of the capacitance is connect with the low reference voltage end.

8. analog to digital conversion circuit according to claim 7, which is characterized in that described to include with reference to trigger module：2^mA reference Trigger is defined as the 1st to the 2nd successively^mWith reference to trigger；

Described 1st to the 2nd^mWith reference to trigger and the 1st to the 2nd^mReference signal end is correspondingly connected with.

9. analog to digital conversion circuit according to claim 8, which is characterized in that the input trigger module includes：2^mA input Trigger is defined as the 1st to the 2nd successively^mInput trigger；

Described 1st to the 2nd^mInput trigger and the 1st to the 2nd^mSignal end is correspondingly connected with.

10. analog to digital conversion circuit according to claim 9, which is characterized in that the judgment module includes：2^mA and door, according to It is secondary to be defined as the 1st to the 2nd^mWith door；

Described 1st to the 2nd^mWith the first input end of door and the 1st to the 2nd^mIt is correspondingly connected with reference to the output end of trigger；

Described 1st to the 2nd^mWith the second input terminal of door and the 1st to the 2nd^mThe output end of input trigger is correspondingly connected with；

Described 1st to the 2nd^mIt is connect with coding module with the output end of door.