CN207611118U - FPGA power supply configuration circuits and device - Google Patents
FPGA power supply configuration circuits and device Download PDFInfo
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- CN207611118U CN207611118U CN201721475025.2U CN201721475025U CN207611118U CN 207611118 U CN207611118 U CN 207611118U CN 201721475025 U CN201721475025 U CN 201721475025U CN 207611118 U CN207611118 U CN 207611118U
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Abstract
A kind of FPGA power supply configuration circuit and device, including power supply circuit, the configuration circuit for being provided with data download interface, the connection circuit that is connect with configuration fpga chip to be powered and to the test circuit to be powered for configuring fpga chip and being tested；Connection circuit is connect with power supply circuit, configuration circuit and test circuit respectively.Above-mentioned FPGA power supply configuration circuits and device, power supply circuit, configuration circuit and test circuit is set to be connect respectively with configuration fpga chip to be powered by connecting circuit, so that can be connected with the Target Board for having welded fpga chip by connecting the winding displacement of circuit, so as to directly carry out preliminary judgement to whether FPGA is welded successfully by test circuit in first time, realize timely, the quick test of FPGA welding, and eliminate welding peripheral circuit loading procedure judged take, be conducive to improve development efficiency.
Description
Technical field
The utility model is related to the technical field of circuit design based on FPGA, more particularly to a kind of power supply of fpga chip
Configuration circuit and device.
Background technology
FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) is as special integrated
A kind of semi-custom circuit in the field circuit (ASIC, Application Specific Integrated Circuit) occurs
, it had not only solved the deficiency of custom circuit, but also overcame the limited disadvantage of original programming device gate circuit number, had simultaneously
Powerful parallel processing capability, thus receive the favor of numerous research staff.But the peripheral circuit of FPGA is relative complex：FPGA
Need three or more power supplys to be powered, it is also necessary to download circuit interface is provided, and need 3 to 4 with layout line to downloading mould
Formula is configured.
So in order to adapt to complicated peripheral circuit, FPGA itself provide for a large amount of IO (Input/Output, i.e.,
Input/output) pin, generally BGA (Ball Grid Array, ball grid array) is used to encapsulate to reduce the volume of chip.And this
Kind encapsulation is susceptible to the problem of rosin joint and short circuit, and this problem is difficult by naked eyes or ten thousand to the more demanding of welding
It is found with table, it is general only to be found by dedicated infrared detection instrument, and can not be found in first time.Traditional
In FPGA welding tests, most research staff is by the way that after to fpga chip power on configuration, can judgement normally download journey
What whether sequence was welded in place to detect FPGA, it needs to weld peripheral circuit, time-consuming for process, is unfavorable for improving development efficiency.
Utility model content
Based on this, it is necessary in view of the above-mentioned problems, provide one kind can in time, fast implement FPGA welding test, favorably
In the FPGA power supply configuration circuits and device that improve development efficiency.
A kind of FPGA powers configuration circuit, including power supply circuit, be provided with data download interface configuration circuit, with wait supplying
The connection circuit of electricity configuration fpga chip connection and the test circuit that the configuration fpga chip to be powered is tested；
The connection circuit is connect with the power supply circuit, the configuration circuit and the test circuit respectively.
In one embodiment, the power supply circuit includes external power interface, generates the first pressure regulation electricity of first voltage
Road and the second regulating circuit for generating second voltage；
The external power interface, first regulating circuit and second regulating circuit are sequentially connected respectively, described
Second regulating circuit is electrically connected with the connection circuit.
In one embodiment, the external power interface includes usb circuit, power adapter circuit and terminals
At least one of sub-circuit.
In one embodiment, first regulating circuit includes LM2596S chips.
In one embodiment, second regulating circuit includes AMS1117 chips.
In one embodiment, second regulating circuit include AMS1117-1.2 chips, AMS1117-2.5 chips and
AMS1117-3.3 chips, AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips are respectively with described
One regulating circuit connects.
In one embodiment, the power supply circuit further includes that digital voltage is converted to the isolation electricity for generating analog voltage
Road, the isolation circuit are connected with second regulating circuit and the connection circuit respectively.
In one embodiment, the data download interface includes AS download interfaces and JTAG download interfaces, the configuration
Circuit further includes configuration result indicating circuit and the switching circuit for switching downloading mode；
The AS download interfaces are connect with the switching circuit and the configuration result indicating circuit respectively, under the JTAG
Interface is carried to connect with the switching circuit and the configuration result indicating circuit respectively.
In one embodiment, the test circuit includes crystal oscillating circuit and test result indicating circuit, the crystal oscillator electricity
Road and the test result indicating circuit are connect with the power supply circuit respectively.
A kind of FPGA power supplies configuration device, including fpga chip and FPGA as described above power supply configuration circuits, it is described
Fpga chip is electrically connected with the connection circuit in FPGA power supply configuration circuits.
Above-mentioned FPGA power supply configuration circuit and device, including power supply circuit, configuration circuit, connection circuit and to test electricity
Road makes power supply circuit, configuration circuit and test circuit be connect respectively with configuration fpga chip to be powered by connecting circuit so that
It can be connected with the Target Board for having welded fpga chip by connecting the winding displacement of circuit, so as to pass through test at the first time
Circuit directly carries out preliminary judgement to whether FPGA is welded successfully, and realizes timely, the quick test of FPGA welding, and saves
What welding peripheral circuit loading procedure was judged takes, and is conducive to improve development efficiency.
Description of the drawings
Fig. 1 is traditional FPGA board design diagram；
Fig. 2 is the circuit diagram of the FPGA power supply configuration circuits of one embodiment of the utility model；
Fig. 3 is the FPGA power supply configuration circuits of one embodiment of the utility model and its corresponding FPGA Target Board circuits signal
Figure；
Fig. 4 is power supply circuit schematic diagram in the FPGA power supply configuration circuits of one embodiment of the utility model；
Fig. 5 is power supply circuit schematic diagram in the FPGA power supply configuration circuits of one embodiment of the utility model；
Fig. 6 be one embodiment of the utility model FPGA power configuration circuit in circuit diagram is isolated；
Fig. 7 is configuration and download interface circuit diagram in the FPGA power supply configuration circuits of one embodiment of the utility model；
Fig. 8 is test circuit schematic diagram in the FPGA power supply configuration circuits of one embodiment of the utility model；
Fig. 9 is target plate interface circuit diagram in the FPGA power supply configuration circuits of one embodiment of the utility model；
Figure 10 is the FPGA power supply configuration device structural schematic diagrams of one embodiment of the utility model.
Specific implementation mode
Fig. 1 is traditional FPGA board design diagram, as shown in Figure 1, in traditional FPGA circuitry design, power supply electricity
Road, configuration and the FPGA peripheral circuits such as download interface circuit and other circuits and fpga chip are integrated on same circuit board.
And FPGA itself provides a large amount of I/O pin, general to use BGA package to reduce the volume of chip, this encapsulation is for welding
It is more demanding, it is susceptible to the problem of rosin joint and short circuit, and this problem is difficult to be found by naked eyes or multimeter, generally only
Having could be found by dedicated infrared detection instrument.For traditional FPGA board, most research staff is substantially
It is, by giving fpga chip power on configuration, to judge after FPGA, power supply circuit and configuration and download interface circuit is first respectively welded
Can normally download what whether program was welded in place to detect FPGA.However, the rosin joint being susceptible to when traditional FPGA welding,
The problems such as solder skip and short circuit, cannot find in first time, general only to be found by dedicated infrared detection instrument, this
Not only time-consuming for process for sample, reduces development efficiency, also undoubtedly increases development cost.If without infrared detection, need
After the completion of the power supply circuit and configuration circuit of FPGA are welded, substantially it could determine whether FPGA welds by downloading program to FPGA
It is connected to position, can undoubtedly waste the more time in this way.And if find that fpga chip is not welded at this time, in the mistake for removing FPGA
The circuit devcie on side may be made a mess of in journey, cause the waste of material.
Fig. 2 is the circuit diagram of the FPGA power supply configuration circuits of one embodiment of the utility model, as shown in Fig. 2, a kind of
FPGA power configuration circuit, including power supply circuit 100, be provided with data download interface configuration circuit 200, with configuration to be powered
The connection circuit 400 of fpga chip connection and the test circuit 300 that the configuration fpga chip to be powered is tested；
The connection circuit 400 respectively with the power supply circuit 100, the configuration circuit 200 and the test circuit 300
Connection.
Power supply circuit 100 can provide the various power supplys of test process needs, including core supply voltage for fpga chip,
Phaselocked loop supply voltage, the supply voltages such as I/O port supply voltage.Configuration circuit 200 is equipped with data download interface, including JTAG connects
Mouth, AS interfaces, FPGA download the data such as test program by the data download interface, and configuration circuit 200 passes through several and configures
Line realizes operating mode handover configurations.Interconnection of the circuit 400 for realizing FPGA power supply configuration circuits and fpga chip is connected,
Cover FPGA work needed for supply voltage and configuration and download pin, connection circuit 400 may include can plug connector,
Corresponding pin in FPGA need to only be guided to interface pair by the row's of can specifically include needle socket when designing new FPGA Target Boards
The position answered, you can the power supply configuration circuit of Target Board and the present embodiment where realizing FPGA interconnects.Test circuit 300 can add
Sense command is carried, directly tests whether FPGA can work normally.Power supply circuit 100, configuration circuit 200, test circuit 300 and
Where connection circuit 400 can also be integrated in non-FPGA on the same circuit board of Target Board.
Above-mentioned FPGA powers configuration circuit, including power supply circuit, configuration circuit, connection circuit and to test circuit, leads to
Crossing connection circuit makes power supply circuit, configuration circuit and test circuit be connect respectively with configuration fpga chip to be powered so that can lead to
The winding displacement for crossing connection circuit is connected with the Target Board for having welded fpga chip, so as to pass through test circuit at the first time
Preliminary judgement directly is carried out to whether FPGA is welded successfully, realizes timely, the quick test of FPGA welding, and eliminates weldering
Connect that peripheral circuit loading procedure judged takes, and is conducive to improve development efficiency.
In one embodiment, the voltage that the power supply circuit 100 exports includes the core power supply electricity needed for fpga chip
At least one of pressure, phaselocked loop supply voltage and I/O port supply voltage.FPGA possesses powerful parallel processing capability, periphery
Circuit is relative complex, and first, FPGA needs three or more power supplys to be powered, including core supply voltage, phaselocked loop power supply electricity
Pressure, I/O port supply voltage etc..The general voltage of core supply voltage is all very low, and specific voltage is different according to chip type, often at present
FPGA is in 1.2V or so.The inside various logic power supply that core supply voltage is FPGA, electric current is from hundreds of milliamperes to several
Peace differs, and is specifically dependent upon the operating clock rate of internal logic and occupied logical resource, for this power supply,
One height capacitive reactances when load, it is very high to the transient response requirement of power supply, and since the low operating current of driving voltage is big,
It is very sensitive to the routing resistance of PCB, trace width is paid particular attention to, reduces the loss that routing resistance is brought as far as possible.Lock
Phase ring supply voltage is for driving FPGA phase-locked loop operations.FPGA often will be with the chip communication of a variety of varying level interfaces, institute
Usually can all support very more level standards, I/O port supply voltage drives various I/O input/output interfaces, to ensure difference
The I/O of level demand can be worked normally.Power supply circuit 100 can be exported as the various voltages needed for FPGA test process,
To ensure the normal realization of FPGA welding tests.
In one embodiment, as shown in figure 3, Fig. 3 be one embodiment of the utility model FPGA power configuration circuit and
It corresponds to FPGA Target Board circuit diagrams.Power supply circuit 100, configuration circuit 200, test circuit 300 and connection circuit 400 collect
At on same general-purpose circuit board.It is powered where connection circuit and fpga chip in configuration circuit on Target Board by FPGA
Power supply configuration plate interface realize power supply configuration plate interconnection of the Target Board with the present invention, may then pass through general FPGA power supplies
The welding test that plate carries out FPGA is configured, timely, the Universal-purpose quick test of FPGA welding are realized, and eliminates welding periphery electricity
What road loading procedure was judged takes, and is conducive to improve development efficiency.
In one embodiment, as shown in figure 4, power supply circuit 100 includes from external power interface 110, generates the first electricity
First regulating circuit 120 of pressure and the second regulating circuit 130 for generating second voltage；The external power interface 110, described
One regulating circuit 120 and second regulating circuit 130 are sequentially connected respectively, second regulating circuit 130 and the connection
Circuit 400 is electrically connected.First regulating circuit 120 may include LM2596S chips or other power supply chips that can generate 5V voltages,
Likewise, the second regulating circuit 130 may include AMS1117 chips or other can realize that the power supply chip of identical function replaces.
Power supply circuit 100 is introduced from outside into power supply by external power interface 110, is handled by the first regulating circuit 120 and generates first
Voltage, first voltage drive the second regulating circuit 130 to generate second voltage, wherein second voltage includes needed for FPGA work
Various voltages, such as core supply voltage, phaselocked loop supply voltage, I/O port supply voltage etc..
In one embodiment, the external power interface 110 includes usb circuit, power adapter circuit and connects
At least one of line end sub-circuit.USB interface is a kind of common PC interfaces, there was only 4 lines, two power supplys, two letters
Number, therefore signal is serial transmission, USB interface is also referred to as serial port, and the speed of USB2.0 can reach 480Mbps, Ke Yiman
The various industry of foot and civilian needs.The output voltage and electric current of USB interface are+5V, 500mA respectively, actually there is error, maximum
No more than +/- 0.2V, that is, 4.8-5.2V, power supply can be introduced from the ends PC by usb circuit.Power supply adaptor is again
It is external power supply, is the supply voltage conversion equipment of small portable electronic device and electronic apparatus, operation principle is by exchanging
Input is converted to direct current output.Connecting terminal be for convenience conducting wire connection and apply, it in fact be exactly one section be enclosed in absolutely
Sheet metal inside edge plastics, both ends have hole that conducting wire can be inserted, and have screw to be used to fasten or unclamp, for example two are led
Line, it is sometimes desirable to connect, need to disconnect again sometimes, at this moment they can be connected with terminal, and can break at any time
It opens, it is convenient and efficient without they are welded or are intertwined, and it is suitble to a large amount of wire interconnection, in electric power
It is connecting terminal entirely above that industry, which just has special terminal block, terminal box, single layer, double-deck, electric current, voltage, commonly
, can break etc., certain compression joint area and is guaranteed through enough electric currents to ensure reliable contacts.It is external
Power interface 110 is introduced from outside by least one of usb circuit, power adapter circuit and connecting terminal circuit
The work of the first regulating circuit of power drives 120 generates first voltage.
In one embodiment, the first regulating circuit 120 includes LM2596S chips.LM2596 is step down supplies management
The regulator of monolithic integrated optical circuit, can export the driving current of 3A, while there is linear well and load to adjust
Save characteristic.It, which fixes output version, has 3.3V, 5V, 12V, tunable versions that can export the various voltages less than 37V.External power supply
Circuit 110 is introduced from outside into power supply can export 5V voltages by LM2596S chips.
In one embodiment, second regulating circuit 130 includes AMS1117 chips.AMS1117 series voltage-stablizers have
Adjustable version and a variety of fixed voltage versions, are designed to provide for 1A output currents and operting differential pressure can be down to 1V, fixed output voltage
For 1.5V, 1.8V, 2.5V, 2.85V, 3.0V, 3.3V, 5.0V, there is 1% precision；The precision that fixed output voltage is 1.2V
It is 2%.In maximum output current, the minimum differntial pressure of AMS1117 devices ensures to be no more than 1.3V, and with the reduction of load current
And it continuously decreases.
In one embodiment, second regulating circuit 130 includes AMS1117-1.2 chips, AMS1117-2.5 chips
With AMS1117-3.3 chips, AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips respectively with it is described
First regulating circuit connects.Select three kinds of AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips chips
The second regulating circuit is formed, can export to obtain the voltage of 1.2V, 2.5V and 3.3V respectively, can be tested respectively as FPGA
Core supply voltage, phaselocked loop supply voltage and the I/O port supply voltage of Cheng Suoxu.
In one embodiment, as shown in figure 5, to power in the FPGA power supply configuration circuits of one embodiment of the utility model
100 schematic diagram of circuit.In the present embodiment, external power interface 110 includes 2.54 spacing connecting terminal circuits, power supply adaptor electricity
Road and USB circuit, for being introduced from outside into power supply；First regulating circuit 120 includes LM2596S-5V1 chips, by external power supply
The power supply processing that interface 110 is introduced from outside into generates the first voltage of 5V, and exports 3A electric currents；Second regulating circuit 130 includes
Three AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips chips, it is respectively that LM2596S-5V1 is defeated
The first voltage processing of the 5V gone out generates 1.2V, and the second voltage of 2.5V, 3.3V correspond respectively to the core supply voltage of FPGA
VCCINT_1.2V, phaselocked loop supply voltage VCC_2.5V and I/O port supply voltage VCCIO_3.3V.In the present embodiment,
It is also associated between LM2596S-5V1 chips and AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips
Switch selection circuit and LED light circuit, for selecting output and working status indication.Power supply circuit in the present embodiment carries
A variety of power supply interfaces have been supplied, the 5V power supplies of USB can be used, power supply adaptor or 2.54 common spacing terminals can also be passed through
Son introduces power supply and generates 5V power supplies using power management chip LM2596S-5V1, then again by power management chip
Tri- chips of AMS1117-1.2, AMS1117-2.5, AMS1117-3.3 generate 1.2V, the voltage of 2.5V, 3.3V, difference respectively
Core supply voltage VCCINT_1.2V, phaselocked loop supply voltage VCC_2.5V, I/O port supply voltage VCCIO_ are provided to FPGA
3.3V。
In one embodiment, power supply circuit 100 further includes that digital voltage is converted to the isolation circuit for generating analog voltage,
The isolation circuit is connected with second regulating circuit 130 and the connection circuit 400 respectively.Phase-locked loop is a kind of feedback
Control circuit, abbreviation phaselocked loop (PLL, Phase-Locked Loop).The characteristics of phaselocked loop is：Utilize externally input reference
The frequency and phase of signal control loop internal oscillation signal.Because output signal frequency may be implemented to input signal frequency in phaselocked loop
Rate from motion tracking, so phaselocked loop is commonly used in Closed loop track circuit.Phaselocked loop in the process of work, when output signal
When frequency is equal with the frequency of input signal, the phase difference value that output voltage and input voltage are kept fixed, i.e. output voltage with
The phase of input voltage is lockable.The supply voltage of phaselocked loop is analog voltage, and 130 output voltage of the second regulating circuit is
Digital voltage, by connecting an isolation circuit after the second regulating circuit 130, the number that the second regulating circuit 130 can be generated
The conversion of word voltage generates the analog voltage needed for phaselocked loop power supply.
In one embodiment, as shown in fig. 6, to be isolated in the FPGA power supply configuration circuits of one embodiment of the utility model
Circuit diagram.In the present embodiment, inductance L2 is separately connected the ends VCC_2.5V and the ends VCC_APLL, and inductance L3 is separately connected GND
End and the ends GNDA_PLL, shunt capacitance C6 and capacitance C7 between the ends VCC_APLL and the ends GNDA_PLL.In second regulating circuit
The VCC_2.5V digital voltage input isolation circuits of AMS1117-2.5 chips output obtain the simulation power supply electricity needed for phaselocked loop
Press VCC_APLL.
In one embodiment, data download interface includes AS download interfaces and JTAG download interfaces, the configuration circuit
200 further include the switching circuit and configuration result indicating circuit for switching downloading mode, the AS download interfaces respectively with institute
Switching circuit is stated to connect with the configuration result indicating circuit, the JTAG download interfaces respectively with the switching circuit and described
Configuration result indicating circuit connects.Switching circuit is used to switch configuration of the downloading mode realization to downloading mode, and switching circuit can
To manually select control downloading mode, configured according to different downloading modes, as a result indicating circuit can be light emitting diode,
It is used to indicate FPGA configuration results；Data download interface is for downloading FPGA programs, wherein AS download interfaces and JTAG downloads connect
Mouth is worked by power supply circuit 100 for electric drive.By switching circuit and data download interface, configuration circuit 200 can be realized
FPGA is downloaded into line program and operating mode configuration.
In one embodiment, as shown in fig. 7, to be configured in the FPGA power supply configuration circuits of one embodiment of the utility model
The schematic diagram of circuit.In the present embodiment, S1 in switching circuit is 4 way switch, for manually control MSEL0, MSEL1,
The low and high level of MSEL2, MSEL3 can be switched different downloading modes and realizes configuration.D2 is light emitting diode, is used to indicate
FPGA configuration results.AS1 and JTAG1 is the download interface of FPGA, for downloading FPGA programs.Wherein AS interfaces directly use
The VCCIO_3.3V power supplies that AMS1117-3.3 chips generate, jtag interface are direct using the 2.5V that AMS1117-2.5 chips generate
Power supply, is isolated with the 2.5V analog voltages needed for FPGA phaselocked loops by isolation circuit.
In one embodiment, the test circuit 300 includes crystal oscillating circuit and test result indicating circuit, crystal oscillating circuit
It is connect respectively with the power supply circuit 100 with test result indicating circuit.Test circuit 300 may include the crystal oscillator electricity of 50MHz
Can road and LED circuit normally work for directly testing FPGA, to realize the test for welding situation to FPGA.
In one embodiment, as shown in figure 8, to be tested in the FPGA power supply configuration circuits of one embodiment of the utility model
300 schematic diagram of circuit.In the present embodiment, test circuit 300 include 50MHz crystal oscillating circuits and LED circuit, crystal oscillating circuit with
AMS1117-3.3 chips connect, and oscillation generates the FPGA work of detection pulsed drive；LED is connected with circuit 400 is connect, instruction
Whether FPGA works normally.
In one embodiment, the connection circuit 400 includes FPGA supply voltages, configuration and various drawing needed for downloading
Foot, connection circuit 400 can be can plug connector, be specifically as follows row's needle socket, realize and power supply circuit 100, configuration electricity
Road 200, test circuit 300 and configuration fpga chip to be powered connection.Wherein, configuration circuit 200 for FPGA programs download and
Working method configures.Corresponding, connection circuit 400, which also contemplated FPGA work required supply voltage and configuration and download, to be drawn
Corresponding pin in FPGA need to only be guided to the corresponding position of interface by foot when designing new FPGA Target Boards, you can be realized
The power supply configuration plate interconnection of Target Board and the present embodiment where FPGA, for FPGA welding tests.
In one embodiment, as shown in figure 9, to be connected in the FPGA power supply configuration circuits of one embodiment of the utility model
400 schematic diagram of circuit.In the present embodiment, connection circuit 400 covers FPGA work required supply voltage and configuration and download
Pin, the interfaces such as including MSEL0, MSEL1, MSEL2, MSEL3, DCLK, CONF_DONE, nCONFIG, LED are realized and wait to supply
The connection of electricity configuration fpga chip, power supply circuit 100, configuration circuit 200 and test circuit 300, to realize test circuit 300
Work test is carried out to FPGA.
In addition, as shown in Figure 10, the utility model also provides a kind of FPGA power supplies configuration device, including 20 He of fpga chip
FPGA power supplies configuration circuit 10 as described above, FPGA power supply configuration circuits 10 include power supply circuit 100, are provided with data download
The configuration circuit 200 of interface, for connect it is to be powered configuration fpga chip connection circuit 400 and to the configuration to be powered
The test circuit 300 that fpga chip is tested, the connection circuit 400 are electric with the power supply circuit 100, the configuration respectively
Road 200, the test circuit 300 and the configuration fpga chip 20 to be powered connect.
Above-mentioned FPGA power supplies configuration device, when designing new FPGA circuitry, after having welded FPGA, the electricity to be used
Source, configuration pin are downloaded pin and are connected on an interface, original download interface is replaced with this interface, is being welded in this way
After FPGA, directly Target Board is connected with power supply configuration plate with winding displacement, you can whether the welding of preliminary test FPGA normal.If
Judge FPGA welding when something goes wrong, can directly remove fpga chip, without having to worry about damage peripheral circuit, reduces material wave
Take.Moreover, research staff is in first secondary design circuit, it might even be possible to not have to design power supply and configuration module on FPGA Target Boards
And download interface, it is directly replaced using the present invention, reduces the development time, electricity is just added when to the last needing to make product
Source and configuration module.And for the download interface on FPGA Target Boards, then it completely can be only with the power supply configuration plate of the present invention
Interface replaces, so as to realize above-mentioned function on the basis of not increasing FPGA Target Board circuit areas, to save out
The time is sent out, development cost is reduced, improves development efficiency.
Each technical characteristic of embodiment described above can be combined arbitrarily, to keep description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed,
But therefore it can not be interpreted as the limitation to utility model patent range.It should be pointed out that for the common skill of this field
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The scope of protection of the utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (10)
- The configuration circuit 1. a kind of FPGA powers, which is characterized in that including power supply circuit, be provided with the configuration electricity of data download interface Road, the connection circuit being connect with configuration fpga chip to be powered and the survey that the configuration fpga chip to be powered is tested Try circuit；The connection circuit is connect with the power supply circuit, the configuration circuit and the test circuit respectively.
- The configuration circuit 2. FPGA according to claim 1 powers, which is characterized in that the power supply circuit includes external power supply Interface, the first regulating circuit for generating first voltage and the second regulating circuit for generating second voltage；The external power interface, first regulating circuit and second regulating circuit are sequentially connected respectively, and described second Regulating circuit is electrically connected with the connection circuit.
- The configuration circuit 3. FPGA according to claim 2 powers, which is characterized in that the external power interface includes USB At least one of interface circuit, power adapter circuit and connecting terminal circuit.
- The configuration circuit 4. FPGA according to claim 2 powers, which is characterized in that first regulating circuit includes LM2596S chips.
- The configuration circuit 5. FPGA according to claim 2 powers, which is characterized in that second regulating circuit includes AMS1117 chips.
- The configuration circuit 6. FPGA according to claim 4 powers, which is characterized in that second regulating circuit includes AMS1117-1.2 chips, AMS1117-2.5 chips and AMS1117-3.3 chips, AMS1117-1.2 chips, AMS1117-2.5 Chip and AMS1117-3.3 chips are connect with first regulating circuit respectively.
- The configuration circuit 7. FPGA according to claim 2 powers, which is characterized in that the power supply circuit further includes will be digital Voltage conversion generates the isolation circuit of analog voltage, and the isolation circuit is electric with second regulating circuit and the connection respectively Road connects.
- The configuration circuit 8. FPGA according to claim 1 powers, which is characterized in that the data download interface includes under AS Carry interface and JTAG download interfaces, the configuration circuit further includes configuration result indicating circuit and for switching opening for downloading mode Powered-down road；The AS download interfaces are connect with the switching circuit and the configuration result indicating circuit respectively, and the JTAG downloads connect Mouth is connect with the switching circuit and the configuration result indicating circuit respectively.
- The configuration circuit 9. FPGA according to claim 1 powers, which is characterized in that the test circuit includes crystal oscillating circuit With test result indicating circuit, the crystal oscillating circuit and the test result indicating circuit are connect with the power supply circuit respectively.
- The configuration device 10. a kind of FPGA powers, which is characterized in that including fpga chip and such as claim 1 to 9 any one institute The FPGA power supply configuration circuits stated, the fpga chip are electrically connected with the connector circuit in FPGA power supply configuration circuits It connects.
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| CN201721475025.2U CN207611118U (en) | 2017-11-07 | 2017-11-07 | FPGA power supply configuration circuits and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110514900A (en) * | 2019-07-23 | 2019-11-29 | 河北远东通信系统工程有限公司 | Constant-temperature crystal oscillator aging Auto-Test System |
| CN113359005A (en) * | 2021-05-18 | 2021-09-07 | 深圳市海创嘉科技有限公司 | Clamp and method for testing needle points of PCBA (printed circuit board assembly) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110514900A (en) * | 2019-07-23 | 2019-11-29 | 河北远东通信系统工程有限公司 | Constant-temperature crystal oscillator aging Auto-Test System |
| CN113359005A (en) * | 2021-05-18 | 2021-09-07 | 深圳市海创嘉科技有限公司 | Clamp and method for testing needle points of PCBA (printed circuit board assembly) |
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