CN207528819U - A kind of FPGA solder joints resistance detecting circuit - Google Patents
A kind of FPGA solder joints resistance detecting circuit Download PDFInfo
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- CN207528819U CN207528819U CN201721636103.2U CN201721636103U CN207528819U CN 207528819 U CN207528819 U CN 207528819U CN 201721636103 U CN201721636103 U CN 201721636103U CN 207528819 U CN207528819 U CN 207528819U
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 43
- 238000012360 testing method Methods 0.000 claims abstract description 36
- 238000001514 detection method Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims description 21
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000012512 characterization method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
The utility model discloses a kind of FPGA solder joints resistance detecting circuits, it is made of internal detection circuitry and outer detecting circuit, the solder joint resistance of FPGA pins can be detected, while the pin can be used for the transmission of output signal Sig, and be rebuild at the output signal Sig_R of reconstruction.Based on time division multiplexing, control signal control multiple selector output is exported by test logic, detection process passes through electric discharge, charging external circuit by output detection signal, feedback signal（Mainly C1）And based on the charging time calculate solder joint resistance R0, without detection when by resistance R2, capacitance C2 Sig_R keep Sig signals, and provide driving load Rin needs energy.FPGA solder joint resistance detections based on the circuit, can be by pin to be measured for Functional Design, and has relatively low detection power consumption.
Description
Technical field
The utility model belongs to electronic technology and reliability engineering field, and in particular to a kind of FPGA solder joints resistance detection electricity
Road.
Background technology
With the development of electronic technology, FPGA comes into being, and the application in circuit system is also increasingly extensive.In space flight
The fields of grade, the use of FPGA are increasingly complicated also more and more because task.The specific demand of space industry, to Department of Electronics therein
The reliability requirement of the equipments such as system is very high.And micro-vibration, alternating temperature-changing stress of space product etc., easily make in circuit system
The solder joint of the particularly large-scale BGA package of solder joint fails.The look-ahead of butt welding point failure, can effective trouble saving hair
It is raw, play an important roll to the reliability promotion of system.
The fields such as failure and health control related research shows that, the failure of solder joint shows as the increasing of solder joint resistance early period
Add.Therefore, the solder joint resistance of FPGA is measured, FPGA solder joint failures can be effectively predicted, to the electronic system comprising FPGA
Reliability Assurance, play an important roll.The resource of aerospace system, finite energy, this requires detecting system use few as possible
System hardware resources, and with relatively low power consumption.
In order to meet the needs of above-mentioned resource, energy, current solder joint failure detection method is used for reference, proposes that one kind can will be by
Detect the FPGA solder joint resistance low-power consumption on-line checking circuits that solder joint is used for FPGA Functional Designs.
Invention content
The technical problem to be solved by the utility model is to provide a kind of FPGA solder joints resistance detecting circuits.
The FPGA solder joints resistance detecting circuit of the utility model includes internal detection circuitry and outer detecting circuit；
The internal detection circuitry, including inside FPGA test logic, multiple selector and connection circuit, based on when
Divide multiplexing, test logic output control signal controls multiple selector selection function signal Sig or detects signal, multi-path choice
The output of device is connected to test logic；
The time division multiplexing refers to fraction of time for testing, and the most of the time is used to export Sig；Described is small
Part-time refers to test logic and the solder joint resistance of FPGA pins is tested for testing；The test logic is to FPGA
The solder joint resistance of pin is tested, and refers to that test signal first exports low level signal, to pin parasitic capacitance C0 and external electrical
Road is discharged, and FPGA pin voltages are discharged into 0V, and then test signal output high level, FPGA pin voltages are improved,
Variation moment from low level to high level is detected by feedback signal, from be charged to the aforementioned variation moment time can dullness pass
The size of the characterization FPGA pin solder joint resistance R0 of increasing；The most of the time for exporting Sig, refers to multiple selector selection
Sig is output to FPGA pins；
The outer detecting circuit is made of a resistor R2 and two capacitors C1 and C2；The resistor R2
Both ends connect respectively with capacitor C1 and capacitor C2；The capacitor C1 and capacitor C2 without connect with R2 one
End ground connection；The resistor R2 is connected with the pin of capacitor C1 one end connecting and FPGA, resistor R2 and capacitor C2
One end of connection is Sig_R signals.
The FPGA solder joint resistance detecting circuits of the utility model have the following advantages：
1. the FPGA solder joints resistance detecting circuit of the utility model can carry out on-line checking, i.e. quilt to FPGA pins solder joint
The FPGA pins of detection solder joint resistance may be used as low frequency signal output pin, save the pin resource of FPGA.
2. the FPGA solder joints resistance detecting circuit of the utility model only detects a solder joint, it is only necessary to 3 non-essential resistances and
Capacitance, placement-and-routing have flexibility.
3. the FPGA solder joints resistance detecting circuit of the utility model has very low measured power, energy saving.
Description of the drawings
Fig. 1 is the structure chart of the FPGA solder joint resistance detecting circuits of the utility model；
Fig. 2 is the fundamental diagram of the internal detection circuitry of the FPGA solder joint resistance detecting circuits of the utility model；
Fig. 3 is between the time that the experiment that the FPGA solder joint resistance detecting circuits of the utility model provide measures and resistance
Relation schematic diagram.
Specific embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
The present embodiment does not limit the utility model in any form, the technical side that all modes for taking equivalent replacement are obtained
Case is all fallen in the scope of protection of the utility model.
The FPGA solder joint resistance detecting circuits detection circuit of the utility model includes internal detection circuitry and external detection electricity
Road；
The internal detection circuitry, including inside FPGA test logic, multiple selector and connection circuit, based on when
Divide multiplexing, test logic output control signal controls multiple selector selection function signal Sig or detects signal, multi-path choice
The output of device is connected to test logic；
The time division multiplexing refers to fraction of time for testing, and the most of the time is used to export Sig；Described is small
Part-time refers to test logic and the solder joint resistance of FPGA pins is tested for testing；The test logic is to FPGA
The solder joint resistance of pin is tested, and refers to that test signal first exports low level signal, to pin parasitic capacitance C0 and external electrical
Road is discharged, and FPGA pin voltages are discharged into 0V, and then test signal output high level, FPGA pin voltages are improved,
Variation moment from low level to high level is detected by feedback signal, from be charged to the aforementioned variation moment time can dullness pass
The size of the characterization FPGA pin solder joint resistance R0 of increasing；The most of the time for exporting Sig, refers to multiple selector selection
Sig is output to FPGA pins；
The outer detecting circuit is made of a resistor R2 and two capacitors C1 and C2；The resistor R2
Both ends connect respectively with capacitor C1 and capacitor C2；The capacitor C1 and capacitor C2 without connect with R2 one
End ground connection；The resistor R2 is connected with the pin of capacitor C1 one end connecting and FPGA, resistor R2 and capacitor C2
One end of connection is Sig_R signals.
Embodiment 1
The transformation range for taking detected solder joint resistance is 0-500 ohm.
The structure of circuit is as shown in Figure 1, R0 represents solder joint resistance to be measured, and C0 represents parasitic capacitance, and R2, C1, C2 are respectively
Resistance capacitance in external test circuitry, Rin are the input resistance of the driven load of simulation.
Table 1 gives outer detecting circuit parameter, and concrete analysis is as follows.In order to ensure measurement accuracy, C1 must be considerably larger than
Distribution capacity C0, however too big C1 will increase energy expense.In conventional PCB, C0 is generally several pF, C1 selection 1nF,
Value is more than 100 times of C0, therefore ignores C0.Experimental result based on XC6SLX9-TQG144BIV1141 is shown, when IO voltages are
During 3.3V, the leaping voltage that the threshold voltage of saltus step is about 1.7,1 to 0 from 0 to 1 is also about 1.7V, and temperature is Celsius in 10-85
The voltage is basically unchanged when between degree.Charge-discharge characteristic based on RC circuits is it is found that C1's puts（It fills）The electric time is with the increasing of R0
Add and increase, when R is 500 ohm of maximum value, put（It fills）Electric time longest, 1.7V is discharged into from 3.3V（It is charged to from 0V
1.7V）, at most need 0.5us.Test process output signal is kept by the wave filter that R2 and C2 are formed.Filter time constant
Bigger, the bandwidth of exportable signal is narrower.Here, 10 times that time constant is R0 and C1 are taken.Time constant is by R2 and C2
Product, too small C2 will reduce the driving force of signal Sig_R, and final choice C2 takes the identical values of C1,1nF；R2 takes R0's
10 times, i.e., 5.1 kilohms.Pulse is taken to put（It fills）The time scale of electricity is 1/8 (12.5%), then increases a put（It fills）Electric process is most
4us, it is assumed that input impedance is 1M ohm, due to input impedance RinThe voltage drop of formation（It rises）Up to 14mV, it is smaller, ignore
Disregard.
Solder joint resistance detection process is controlled by the test logic of internal detection circuitry, and test logic mainly includes 6 states
（state~state5）, principle is as shown in Figure 2.State0 is conventional output status, and signal Sig is output to PIN, Ran Hou
It is rebuild at Sig_R, Timer t is used to calculate the retention time that Sig stablizes one stationary value of output, when timer reaches
During 20us, that is, think that PIN has outputed one and determined value enough for a long time, C2 is almost completely discharged 0V（Charging
To 3.3V）.After the timer time 20us is more than, then into state1.In State1, by counter t1Clear 0, and state latch
The Sig signals currently exported are to Sig_r, it is assumed that Sig signals are high level 1（Low level 0）, then it is directly entered state2.
State2, PIN export a level 0 opposite with Sig_r（1）, discharge pin（Charging）, while by counter t2Clearly
0, subsequently enter state3.In state3, counter t2Cumulative, PIN output high resistants wait for C2 to charge in turn to pin.
Work as t2=6 make, into state3.State4 setting PIN are input, check PIN states, if not reaching threshold value, electricity
Flat is still 1（0）, i.e., it is identical with Sig_R, then it returns to state2 and continues to discharge（Charging）, otherwise, electric discharge（Charging）Terminate, meter
Number device t1It is cumulative, into state5.In State5, t1It is linear with discharge time, it can be according to t1Calculate R0（Also
It is related with Sig_R）.Since the level on PIN during the test changes, the electricity of C2 will be influenced, so by timer t
Clear 0, reclocking prepares to start to test next time.During system reset, state5 is also directly entered, by t clear 0.
XC6SLX9-TQG144BIV1141 FPGA based on Xilinx companies carry out experiment test to the detection circuit.
Fig. 3 gives the t measured under different R01, in the case of Sig=0 or Sig=1, t1Increase with the increase of R0.Table 2 is shown
The power of the detection method（4 test points are included altogether）, power consumption is about 8.6mW, and single solder joint detection disappears
The power of consumption is no more than 2.2mW.
Table 1
Table 2
Claims (1)
1. a kind of FPGA solder joints resistance detecting circuit, it is characterised in that：The detection circuit is including internal detection circuitry and outside
Portion's detection circuit；
The internal detection circuitry including test logic, multiple selector and the connection circuit inside FPGA, is answered based on the time-division
With, test logic output control signal control multiple selector selection function signal Sig or detection signal, multiple selector
Output is connected to test logic；
The time division multiplexing refers to fraction of time for testing, and the most of the time is used to export Sig；The fraction
Time for testing, refers to test logic and the solder joint resistance of FPGA pins is tested；The test logic is to FPGA pins
Solder joint resistance tested, refer to that test signal first exports low level signal, to pin parasitic capacitance C0 and external circuit into
Row electric discharge, 0V is discharged by FPGA pin voltages, and then test signal output high level, FPGA pin voltages is improved, by anti-
Feedback signal detects the variation moment from low level to high level, can be with monotonic increase from the time for being charged to the aforementioned variation moment
Characterize the size of FPGA pin solder joint resistance R0；The most of the time for exporting Sig, refers to multiple selector selection Sig
It is output to FPGA pins；
The outer detecting circuit is made of a resistor R2 and two capacitors C1 and C2；The two of the resistor R2
End is connect respectively with capacitor C1 and capacitor C2；The capacitor C1 and capacitor C2 without the termination that is connect with R2
Ground；The resistor R2 is connected with the pin of capacitor C1 one end connecting and FPGA, and resistor R2 is connect with capacitor C2
One end be Sig_R signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636103.2U CN207528819U (en) | 2017-11-30 | 2017-11-30 | A kind of FPGA solder joints resistance detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636103.2U CN207528819U (en) | 2017-11-30 | 2017-11-30 | A kind of FPGA solder joints resistance detecting circuit |
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| Publication Number | Publication Date |
|---|---|
| CN207528819U true CN207528819U (en) | 2018-06-22 |
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| CN201721636103.2U Withdrawn - After Issue CN207528819U (en) | 2017-11-30 | 2017-11-30 | A kind of FPGA solder joints resistance detecting circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807280A (en) * | 2017-11-30 | 2018-03-16 | 中国空气动力研究与发展中心超高速空气动力研究所 | A kind of FPGA solder joints resistance detecting circuit |
| CN109932639A (en) * | 2019-03-29 | 2019-06-25 | 北京唯实兴邦科技有限公司 | FPGA solder joint failure diagnostic method and diagnostic device based on single capacitor |
| CN107807280B (en) * | 2017-11-30 | 2024-05-31 | 中国空气动力研究与发展中心超高速空气动力研究所 | FPGA solder joint resistance detection circuit |
-
2017
- 2017-11-30 CN CN201721636103.2U patent/CN207528819U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807280A (en) * | 2017-11-30 | 2018-03-16 | 中国空气动力研究与发展中心超高速空气动力研究所 | A kind of FPGA solder joints resistance detecting circuit |
| CN107807280B (en) * | 2017-11-30 | 2024-05-31 | 中国空气动力研究与发展中心超高速空气动力研究所 | FPGA solder joint resistance detection circuit |
| CN109932639A (en) * | 2019-03-29 | 2019-06-25 | 北京唯实兴邦科技有限公司 | FPGA solder joint failure diagnostic method and diagnostic device based on single capacitor |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180622 Effective date of abandoning: 20240531 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20180622 Effective date of abandoning: 20240531 |