CN207503964U - Chip scale package structure - Google Patents
Chip scale package structure Download PDFInfo
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- CN207503964U CN207503964U CN201721646937.1U CN201721646937U CN207503964U CN 207503964 U CN207503964 U CN 207503964U CN 201721646937 U CN201721646937 U CN 201721646937U CN 207503964 U CN207503964 U CN 207503964U
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- Prior art keywords
- weld pad
- lead wire
- metal lead
- semiconductor chip
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model provides a kind of chip scale package structure, and the chip scale package structure includes：Semiconductor chip, the semiconductor chip front are formed with first to be connected with inside function device and connect weld pad；One substrate, the front of the substrate are formed with the second connection weld pad；Metal lead wire between the semiconductor chip and the substrate, and connect weld pad with described first with one end and is connected, and the other end connect weld pad with described second and is connected.The chip scale package structure of the utility model forms metal lead wire by routing technique in semiconductor chip surface, can realize being electrically connected for single semiconductor chip and substrate, can realize the plastic packaging of single semiconductor chip；Meanwhile can be controlled according to actual needs by the height of the metal lead wire that routing technique is formed, the sufficiently high metal lead wire of height can be obtained.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of chip scale package structure.
Background technology
In prior art, after several semiconductor chips are produced on wafer, partly led described
Body chip is carried out wafer-level packaging and (is first packaged semiconductor chip as unit of wafer, then again by packaged structure
Slice is in individual semiconductor chip one by one), at this point, the semiconductor chip can pass through copper post (Cu pillar
Bump it) is electrically connected with other structures.And if in special process, need to be packaged the single semiconductor chip after cutting
When, existing technique can not make copper post in the single semiconductor core on piece, can not be by existing packaging technology to single
Semiconductor chip is effectively encapsulated.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of chip size packages knots
Structure for solving that copper post can not be made on single semiconductor chip in the prior art, can not carry out single semiconductor chip
The problem of effectively encapsulating.
In order to achieve the above objects and other related objects, the utility model provides a kind of chip scale package structure, described
Chip scale package structure includes：
Semiconductor chip, the semiconductor chip front are formed with first to be connected with inside function device and connect
Weld pad；
One substrate, the front of the substrate are formed with the second connection weld pad；
Metal lead wire connect weld pad between the semiconductor chip and the substrate, and with one end with described first
It is connected, the other end connect weld pad with described second and is connected.
Preferably, the chip scale package structure further includes sealing layer, positioned at the semiconductor chip and the substrate
Between, and sealing is in each metal lead wire periphery.
Preferably, the material of the sealing layer includes scolding tin.
Preferably, the metal lead wire includes：
Convex block is connected, weld pad is connect with described first and is connected；
Metal wire on the connection convex block, is connected with the connection convex block and the second connection weld pad.
Preferably, the metal lead wire includes：
Convex block is connected, weld pad is connect with described second and is connected；
Metal wire on the connection convex block, is connected with the connection convex block and the first connection weld pad.
Preferably, the quantity of the first connection weld pad, the second connection weld pad and the metal lead wire is several
It is a, and the metal lead wire connect weld pad with described first and the second connection weld pad connects one to one.
Preferably, the chip scale package structure further includes underfill, is filled in the semiconductor chip and institute
Between stating substrate, and fill up the gap between the metal lead wire.
The utility model also provides a kind of preparation method of chip scale package structure, the chip scale package structure
Preparation method includes the following steps：
1) semiconductor chip is provided, the front of the semiconductor chip is formed with the first connection weld pad；
2) metal lead wire, the metal lead wire and described first are formed in the semiconductor chip front using routing technique
Connection weld pad is connected；
3) substrate is provided, the front of the substrate is formed with the second connection weld pad；
4) scolding tin is formed in the front of the substrate using silk-screen printing technique, the scolding tin is located at the described second connection and welds
The surface of pad；
5) the semiconductor chip upside-down mounting is installed in the front of the substrate, the metal lead wire connects with the scolding tin
It touches；
6) reflow treatment is carried out to the scolding tin, so that the metal lead wire is inserted into the scolding tin, and by the weldering
Tin is cured as sealing layer sealing in metal lead wire periphery.
Preferably, the semiconductor chip front being supplied in step 1) is formed with several the first connection welderings
Pad, step 2) is middle to be respectively formed the metal lead wire, the gold using routing technique in the surface of each first connection weld pad
Category lead connect weld pad with described first and connects one to one；The substrate front side provided in step 3) is formed with several institutes
State the second connection weld pad.
Preferably, it after step 6), further includes and forms underfill between the semiconductor chip and the substrate
The step of, the underfill fills up the gap between the metal lead wire.
As described above, the chip scale package structure of the utility model, has the advantages that：The core of the utility model
Chip size encapsulating structure forms metal lead wire by routing technique in semiconductor chip surface, can realize single semiconductor chip
With being electrically connected for substrate, the plastic packaging of single semiconductor chip can be realized；Meanwhile drawn by the metal that routing technique is formed
The height of line can be controlled according to actual needs, can obtain the sufficiently high metal lead wire of height.
Description of the drawings
Fig. 1 is shown as the flow of the preparation method of the chip scale package structure provided in the utility model embodiment one
Figure.
The preparation method that Fig. 2~Fig. 8 is shown as the chip scale package structure provided in the utility model embodiment one is each
The structure diagram that step is presented, wherein, Fig. 8 is shown as the structural representation of the chip scale package structure of the utility model
Figure.
Component label instructions
1 semiconductor chip
11 first connection weld pads
2 metal lead wires
21 connection convex blocks
22 metal wires
3 wire bonders
4 substrates
41 second connection weld pads
5 silk screens
51 openings
6 gauze brushes
7 sealing layers
71 scolding tin
8 underfills
Specific embodiment
Illustrate the embodiment of the utility model below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1~Fig. 8.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation method of chip scale package structure, the chip size packages
The preparation method of structure includes the following steps：
1) semiconductor chip is provided, the front of the semiconductor chip is formed with the first connection weld pad；
2) metal lead wire, the metal lead wire and described first are formed in the semiconductor chip front using routing technique
Connection weld pad is connected；
3) substrate is provided, the front of the substrate is formed with the second connection weld pad；
4) scolding tin is formed in the front of the substrate using silk-screen printing technique, the scolding tin is located at the described second connection and welds
The surface of pad；
5) the semiconductor chip upside-down mounting is installed in the front of the substrate, the metal lead wire connects with the scolding tin
It touches；
6) reflow treatment is carried out to the scolding tin, so that the metal lead wire is inserted into the scolding tin, and by the weldering
Tin is cured as sealing layer sealing in metal lead wire periphery.
In step 1), S1 steps and Fig. 2 in please referring to Fig.1 provide semiconductor chip 1, the semiconductor chip 1
Front be formed with the first connection weld pad 11.
As an example, the semiconductor chip 12 can be any one existing functional chip, do not limit herein.
As an example, it is described first connection weld pad 11 particular number can be set according to actual needs, in Fig. 2 with
12 front of semiconductor chip is formed there are four the described first connection weld pad 11 as example.
It should be noted that semiconductor chip 1 described herein refers to cut wafer after the completion of semiconducter process
The independent chip (die) obtained after piece.
In step 2), S2 steps and Fig. 3 in please referring to Fig.1, using routing technique in 1 front of semiconductor chip
Metal lead wire 2 is formed, the metal lead wire 2 connect weld pad 11 with described first and is connected.
Draw as an example, wire bonder 3 may be used and form metal on the surface of each first connection weld pad 11 successively
Line 2, during the metal lead wire 2 is formed, the height of the metal lead wire 2 can be intercepted according to actual needs.
As an example, the metal lead wire 2 can be a wires, or include as shown in Figure 3：Connect convex block
21 and metal wire 22, wherein, the connection convex block 21 connect weld pad 11 with described first and is connected, specifically, it is described connect it is convex
Block 21 is located at the upper surface of the described first connection weld pad 11；The metal wire 22 is located on the connection convex block 21, with the company
Convex block 21 is connect to be connected.
As an example, the width of the connection convex block 21 can be more than the width of the metal wire 22 as shown in Figure 3, by institute
It states metal lead wire 2 and is more than the connection convex block 21 of the metal wire 22 via width and connect weld pad 11 with described first and connect
It touches, the contact area that the metal lead wire 2 connect weld pad 11 with described first can be increased, so as to improve the metal lead wire 2
The contact performance for connecting weld pad 11 with described first.
Certainly, in other examples, the metal lead wire 2 can also connect weldering via the metal wire 22 with described first
Pad 11 is connected, i.e., in other examples, the metal wire 22 connect weld pad 11 with described first and is connected, the connection convex block
21 are located on the metal wire 22, and be connected with the metal wire 22.
As an example, the material of the metal lead wire 2 can be but be not limited only in copper, aluminium, tin, gold, titanium, thallium or silver etc.
At least one, it is preferable that in the present embodiment, the material of the metal lead wire 2 is copper, i.e., described connection convex block 21 and the gold
The material for belonging to line 22 is copper.
In step 3), S3 steps and Fig. 4 in please referring to Fig.1 provide a substrate 4, and the front of the substrate 4 is formed with
Second connection weld pad 41.
As an example, the substrate 4 can be any one existing substrate with connection structure or certain function, example
Such as, pcb board (printed circuit board).
As an example, the quantity of the second connection weld pad 41 that 4 front of substrate is equipped with can be according to actual needs
It is set, using the described second connection weld pad 41 there are four the front formation of the substrate 4 as example in Fig. 4.Preferably, originally
In embodiment, the quantity quantity that connect weld pad 11 with described first of the second connection weld pad 41 and the metal lead wire 2
Quantity all same.It should be noted that if connection structure or function element are formed with inside the substrate 4, second connection
Weld pad 41 is connected with the connection structure in the substrate 4 and function element.
In step 4), S4 steps and Fig. 5 in please referring to Fig.1, using silk-screen printing technique in the front of the substrate 4
Scolding tin 71 is formed, the scolding tin 71 is located at the surface of the described second connection weld pad 41.
Specifically, it is possible, firstly, to the silk screen 5 for having several openings 51 by one is set to 4 upper front of substrate, institute
It states the opening 51 on silk screen 5 and connect weld pad 41 with described second and correspond；Secondly, close to the 5 side table of silk screen
Face sets scolding tin 71, at this point, the scolding tin 71 is in flow-like (for example, deadlocked shape)；Then, it is set certainly using a gauze brush 6
The lateral opposite side for stating scolding tin 71 swipes the scolding tin 71 so that the scolding tin 71 is placed in each institute via 51 leakage of opening
The surface of the second connection weld pad 41 is stated, as shown in Figure 5.
In step 5), 1 upside-down mounting of semiconductor chip is installed in the base by S5 steps and Fig. 6 in please referring to Fig.1
The front of plate 4, the metal lead wire 2 are in contact with the scolding tin 71.
As an example, when 1 upside-down mounting of semiconductor chip is installed in the front of the substrate 4, the metal lead wire 2 with
The second connection weld pad 41 is correspondingly arranged up and down one by one, to ensure that the follow-up metal lead wire 2 can be connect with described second
Weld pad 41 corresponds contact.
It should be noted that after 1 upside-down mounting of semiconductor chip is installed in the front of the substrate 4, the metal draws
Line 2 can be inserted into the scolding tin 71 and be contacted with the upper surface of second weld pad 41 under gravity, or
It is only in contact in scolding tin 71 with the scolding tin 71 described in 2 partial insertion of metal lead wire.
It should be further noted that since flow-like can be presented in the scolding tin 71 at this time, the semiconductor chip 1 falls
The front for being installed in the substrate 4 can be clamped the semiconductor chip 1 and the substrate 4 by stationary fixture later,
To prevent the semiconductor chip 1 from being moved compared to the substrate 4, so as to cause the metal lead wire 2 and described second
Metal lead wire 2 misplaces.
In step 6), S6 steps and Fig. 7 in please referring to Fig.1 carry out reflow treatment, so that institute to the scolding tin 71
It states metal lead wire 2 to be inserted into the scolding tin 71, and the scolding tin 71 is cured as 7 sealing of sealing layer in outside the metal lead wire 2
It encloses.
As an example, in above-mentioned steps, there may be the metal lead wire 2 cannot be completely inserted into for the scolding tin 71
To connect the possibility that weld pad 41 is in contact, in this step, the structure that step 5) is obtained with described second in the scolding tin 71
It is placed in and is heated to reflux in device so that the liquid that can be flowed, in reflux course, the metal lead wire is presented in the scolding tin 71
2 may insure to be inserted into the scolding tin 71 under gravity, and connect weld pad 41 with described second and be in contact；It has flowed back
Device after reflow treatment is heated to reflux taking out cooling in device by Bi Hou from described, and the scolding tin 71 for being is cured as described
7 sealing of sealing layer is in 2 periphery of metal lead wire.
By setting the sealing layer 7 in 2 periphery of the metal lead wire, can reinforce the semiconductor chip 1 with it is described
The binding force of substrate 4, so as to avoid causing under external force the semiconductor chip 1 from being separated with the substrate 4.
As an example, as shown in figure 8, after step 6), further include between the semiconductor chip 1 and the substrate 4
The step of forming underfill 8, the underfill 8 fills up the gap between the metal lead wire 41.
As an example, it is specially with chemistry that underfill 8 is formed between the semiconductor chip 1 and the substrate 4
Glue (main component is epoxy resin) is filled between the semiconductor chip 1 and the substrate 4, using being heating and curing
Gap large area between the semiconductor chip 1 and the substrate 4 is filled up and (generally fills up more than 80%) by form, the bottom
The sealing layer 7 and the metal lead wire 2 are encapsulated plastic packaging by portion's filling glue 8, and the semiconductor core is further reinforced so as to reach
The purpose of piece 1 and the substrate 4 enhances the anti-dropping capability of encapsulating structure.
As an example, capillary filling (Capillary underfill) technique or molding filling (Molding may be used
Underfill, abbreviation MUF) technique forms the underfill 8 between the semiconductor chip 1 and the substrate 4.
The preparation method of the chip scale package structure of the utility model is by routing technique in 1 table of semiconductor chip
Face forms the metal lead wire 2, can realize being electrically connected for single semiconductor chip and the substrate 4, can realize single half
The plastic packaging of conductor chip；Meanwhile the height of the metal lead wire 2 formed by routing technique can carry out according to actual needs
Control can obtain the sufficiently high metal lead wire of height.
Embodiment two
Please continue to refer to Fig. 8, the present embodiment also provides a kind of chip scale package structure, the chip scale package structure
The preparation method as described in embodiment one may be used to be prepared, the chip scale package structure includes：Half is led
Body chip 1,1 front of semiconductor chip are formed with first to be connected with inside function device and connect weld pad 11；One base
Plate 4, the front of the substrate 4 are formed with the second connection weld pad 41；Metal lead wire 2, the metal lead wire 2 are located at the semiconductor
Between chip 1 and the substrate 4, and weld pad 11 being connect with described first with one end and being connected, the other end is connect with described second
Weld pad 41 is connected.
As an example, the semiconductor chip 12 can be any one existing functional chip, do not limit herein.
As an example, it is described first connection weld pad 11 particular number can be set according to actual needs, in Fig. 2 with
12 front of semiconductor chip is formed there are four the described first connection weld pad 11 as example.
It should be noted that semiconductor chip 1 described herein refers to cut wafer after the completion of semiconducter process
The independent chip (die) obtained after piece.
As an example, the metal lead wire 2 can be a wires, or include as shown in Figure 3：Connect convex block
21 and metal wire 22, wherein, the connection convex block 21 connect weld pad 11 with described first and is connected, specifically, it is described connect it is convex
Block 21 is located at the upper surface of the described first connection weld pad 11；The metal wire 22 is located on the connection convex block 21, with the company
Convex block 21 is connect to be connected.
As an example, the width of the connection convex block 21 can be more than the width of the metal wire 22 as shown in Figure 3, by institute
It states metal lead wire 2 and is more than the connection convex block 21 of the metal wire 22 via width and connect weld pad 11 with described first and connect
It touches, the contact area that the metal lead wire 2 connect weld pad 11 with described first can be increased, so as to improve the metal lead wire 2
The contact performance for connecting weld pad 11 with described first.
Certainly, in other examples, the metal lead wire 2 can also connect weldering via the metal wire 22 with described first
Pad 11 is connected, i.e., in other examples, the metal wire 22 connect weld pad 11 with described first and is connected, the connection convex block
21 are located on the metal wire 22, and be connected with the metal wire 22.
As an example, the material of the metal lead wire 2 can be but be not limited only in copper, aluminium, tin, gold, titanium, thallium or silver etc.
At least one, it is preferable that in the present embodiment, the material of the metal lead wire 2 is copper, i.e., described connection convex block 21 and the gold
The material for belonging to line 22 is copper.
As an example, the substrate 4 can be any one existing substrate with connection structure or certain function, example
Such as, pcb board (printed circuit board).
As an example, the quantity of the second connection weld pad 41 that 4 front of substrate is equipped with can be according to actual needs
It is set, using the described second connection weld pad 41 there are four the front formation of the substrate 4 as example in Fig. 4.Preferably, originally
In embodiment, the quantity quantity that connect weld pad 11 with described first of the second connection weld pad 41 and the metal lead wire 2
Quantity all same.It should be noted that if connection structure or function element are formed with inside the substrate 4, second connection
Weld pad 41 is connected with the connection structure in the substrate 4 and function element.
As an example, the quantity of the first connection weld pad 11, the second connection weld pad 41 and the metal lead wire 2 is equal
For several, and the metal lead wire 2 with described first connect weld pad 11 and it is described second connection weld pad 41 connect one to one.
As an example, the chip scale package structure further includes sealing layer 7, the sealing layer 7 is located at the semiconductor
Between chip 1 and the substrate 4, and sealing is in each 2 periphery of metal lead wire.Preferably, in the present embodiment, the sealing layer
7 material includes scolding tin.By setting the sealing layer 7 in 2 periphery of metal lead wire, the semiconductor chip can be reinforced
1 with the binding force of the substrate 4, so as to avoid causing under external force the semiconductor chip 1 from dividing with 4 phase of substrate
From.
As an example, the chip scale package structure further includes underfill 8, the underfill 8 is filled in
Between the semiconductor chip 1 and the substrate 4, and fill up the gap between the metal lead wire 2.The underfill 8
Specially with chemical glue (main component is epoxy resin), the underfill 8 using the form that is heating and curing will it is described partly
Gap large area between conductor chip 1 and the substrate 4 fills up and (generally fills up more than 80%), and the underfill 8 will
The sealing layer 7 and the metal lead wire 2 encapsulate plastic packaging, and the semiconductor chip 1 and the base are further reinforced so as to reach
The purpose of plate 4 enhances the anti-dropping capability of encapsulating structure.
In conclusion the chip scale package structure of the utility model, the chip scale package structure includes：Half is led
Body chip, the semiconductor chip front are formed with first to be connected with inside function device and connect weld pad；One substrate, institute
The front for stating substrate is formed with the second connection weld pad；Metal lead wire, between the semiconductor chip and the substrate, and with
One end connect weld pad with described first and is connected, and the other end connect weld pad with described second and is connected.The chip of the utility model
Size packaging structure by routing technique semiconductor chip surface formed metal lead wire, can realize single semiconductor chip with
The electrical connection of substrate can realize the plastic packaging of single semiconductor chip；Meanwhile the metal lead wire formed by routing technique
Height can be controlled according to actual needs, the sufficiently high metal lead wire of height can be obtained.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.
Claims (7)
1. a kind of chip scale package structure, which is characterized in that the chip scale package structure includes：
Semiconductor chip, the semiconductor chip front are formed with first to be connected with inside function device and connect weldering
Pad；
One substrate, the front of the substrate are formed with the second connection weld pad；
Metal lead wire between the semiconductor chip and the substrate, and connect weld pad with described first with one end and is connected
It connects, the other end connect weld pad with described second and is connected.
2. chip scale package structure according to claim 1, which is characterized in that the chip scale package structure also wraps
Sealing layer is included, between the semiconductor chip and the substrate, and sealing is in each metal lead wire periphery.
3. chip scale package structure according to claim 2, which is characterized in that the material of the sealing layer includes weldering
Tin.
4. chip scale package structure according to claim 1, which is characterized in that the metal lead wire includes：
Convex block is connected, weld pad is connect with described first and is connected；
Metal wire on the connection convex block, is connected with the connection convex block and the second connection weld pad.
5. chip scale package structure according to claim 1, which is characterized in that the metal lead wire includes：
Convex block is connected, weld pad is connect with described second and is connected；
Metal wire on the connection convex block, is connected with the connection convex block and the first connection weld pad.
6. chip scale package structure according to claim 1, which is characterized in that the first connection weld pad, described the
The quantity of two connection weld pads and the metal lead wire is several, and the metal lead wire connect weld pad and institute with described first
The second connection weld pad is stated to connect one to one.
7. chip scale package structure according to any one of claim 1 to 6, which is characterized in that the chip size
Encapsulating structure further includes underfill, is filled between the semiconductor chip and the substrate, and fills up the metal and draw
Gap between line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721646937.1U CN207503964U (en) | 2017-12-01 | 2017-12-01 | Chip scale package structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721646937.1U CN207503964U (en) | 2017-12-01 | 2017-12-01 | Chip scale package structure |
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| CN207503964U true CN207503964U (en) | 2018-06-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109980A (en) * | 2017-12-01 | 2018-06-01 | 中芯长电半导体（江阴）有限公司 | Chip scale package structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109980A (en) * | 2017-12-01 | 2018-06-01 | 中芯长电半导体（江阴）有限公司 | Chip scale package structure and preparation method thereof |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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